Memory management schemes for non-volatile memory devices

Information

  • Patent Grant
  • 8677054
  • Patent Number
    8,677,054
  • Date Filed
    Thursday, December 9, 2010
    13 years ago
  • Date Issued
    Tuesday, March 18, 2014
    10 years ago
  • Inventors
  • Original Assignees
  • Examiners
    • Bragdon; Reginald
    • Namazi; Mehdi
    Agents
    • Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
Abstract
A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.
Description
FIELD OF THE INVENTION

The present invention relates generally to data storage, and particularly to memory management in non-volatile storage devices.


BACKGROUND OF THE INVENTION

Some storage devices, such as Solid-State Disks (SSD), use arrays of analog memory cells for non-volatile data storage. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. This analog value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into intervals, each interval corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.


Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible programming levels. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible programming levels.


SUMMARY OF THE INVENTION

An embodiment of the present invention that is described herein provides a method, including:


storing data in a non-volatile memory that includes multiple memory blocks;


defining at least first and second regions in the non-volatile memory;


defining a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and defining a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region;


individually within each of the first and second regions and independently of the other region, compacting portions of the data by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.


In some embodiments, defining the first and second regions includes assigning the first region for storing parts of the data that change at a first frequency, and assigning the second region for storing portions of the data that change at a second frequency, smaller than the first frequency. In an embodiment, the method includes setting the first over-provisioning ratio to be larger than the second over-provisioning ratio.


In a disclosed embodiment, defining the first and second regions includes assigning the first region for storing frequently-changing data, and assigning the second region for storing rarely-changing data. In another embodiment, the first region is used for storing a computer file that is known to change frequently. In an embodiment, defining the first region includes detecting storage locations of the non-volatile memory in which the computer file is stored.


In some embodiments, defining the first and second regions includes assigning the first region for storing parts of the data that are written sequentially, and assigning the second region for storing portions of the data that are written non-sequentially. In an embodiment, the method includes modifying at least one of the first and second over-provisioning ratios over time. In another embodiment, compacting the portions of the data includes choosing the source memory blocks based on a selection criterion that equalizes wear of the non-volatile memory.


In yet another embodiment, storing the data includes accepting commands to store the data in logical addresses, translating the logical addresses into respective physical storage locations in the non-volatile memory and storing the data in the physical storage locations, and the method includes modifying translation of the logical addresses into the physical storage locations based on a criterion that equalizes wear of the non-volatile memory.


There is additionally provided, in accordance with an embodiment of the present invention, a method, including:


accepting from a host data belonging to a host data-set;


identifying, independently of the host, a portion of the data as belonging to a pre-specified host data-set item;


storing the identified portion in a non-volatile memory using a first number of bits per memory cell; and


storing the data other than the identified portion in the non-volatile memory using a second number of bits per memory cell, higher than the first number.


In some embodiments, the host data-set includes computer files, and the pre-specified host data-set item includes a pre-specified computer file. In an embodiment, identifying the portion includes automatically detecting that the portion of the data belongs to the pre-specified host data-set item without receiving from the host any notification that relates the portion of the data to the pre-specified host data-set item.


There is also provided, in accordance with an embodiment of the present invention, a method, including:


in a memory controller that stores data for a host in a memory, defining independently of the host execution priorities for two or more types of memory access tasks to be applied to the memory;


accepting multiple un-prioritized memory access tasks submitted by the host to the memory controller, each of the accepted memory access tasks belonging to a respective one of the types; and


applying the accepted memory access tasks to the memory in accordance with the defined execution priorities responsively to the respective types.


In some embodiments, defining the execution priorities includes giving precedence to memory readout tasks over tasks other than the memory readout tasks. In a disclosed embodiment, defining the execution priorities includes giving precedence to the memory access tasks relating to selected storage addresses over the memory access tasks relating to storage addresses other than the selected storage addresses. In another embodiment, defining the execution priorities includes giving precedence to the memory access tasks relating to a selected file type over the memory access tasks relating to file types other than the selected file type.


In yet another embodiment, defining the execution priorities includes causing the memory controller to execute a sequence of consecutive memory access tasks belonging to a given type. In an embodiment, causing the memory controller to execute the sequence includes queuing subsets of the memory access tasks belonging to the respective types in respective type-specific queues, and executing the sequence of the consecutive memory access tasks drawn from one of the type-specific queues. In an embodiment, defining the execution priorities includes modifying the execution priorities over time.


There is further provided, in accordance with an embodiment of the present invention, a method, including:


accepting from a host a computer file, and storing the computer file in a non-volatile memory;


identifying, automatically and independently of the host, a region of the non-volatile memory that holds a portion of the computer file that is not utilized by the host; and


releasing the identified region for use in management of the non-volatile memory while continuing to hold the computer file in the non-volatile memory.


In some embodiments, the computer file indicates attributes of other computer files stored in the non-volatile memory, and identifying the region includes identifying null entries in the computer file. In a disclosed embodiment, releasing the region includes assigning the released region to serve as over-provisioning memory space.


There is additionally provided, in accordance with an embodiment of the present invention, apparatus, including:


an interface, which is configured to accept data for storage in a non-volatile memory; and


a processor, which is configured to define at least first and second regions in the non-volatile memory, to define a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, to define a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region, and, individually within each of the first and second regions and independently of the other region, to compact portions of the data by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.


There is also provided, in accordance with an embodiment of the present invention, apparatus, including:


an interface, which is configured to accept from a host data belonging to a host data-set for storage in a non-volatile memory; and


a processor, which is configured to identify, independently of the host, a portion of the data as belonging to a pre-specified host data-set item, to store the identified portion in the non-volatile memory using a first number of bits per memory cell, and to store the data other than the identified portion in the non-volatile memory using a second number of bits per memory cell, higher than the first number.


There is further provided, in accordance with an embodiment of the present invention, apparatus, including:


an interface, which is configured to accept from a host memory access tasks for execution in a memory; and


a processor, which is configured to define, independently of the host, execution priorities for two or more types of the memory access tasks, to accept multiple un-prioritized memory access tasks submitted by the host, each of the accepted memory access tasks belonging to a respective one of the types, and to apply the accepted memory access tasks to the memory in accordance with the defined execution priorities responsively to the respective types.


There is also provided, in accordance with an embodiment of the present invention, apparatus, including:


an interface, which is configured to accept from a host a computer file for storage in a non-volatile memory; and


a processor, which is configured to store the computer file in the non-volatile memory, to identify, automatically and independently of the host, a region of the non-volatile memory that holds a portion of the computer file that is not utilized by the host, and to release the identified region for use in management of the non-volatile memory while continuing to hold the computer file in the non-volatile memory.


The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;



FIG. 2 is a diagram that schematically illustrates a process of compacting memory blocks, in accordance with an embodiment of the present invention;



FIG. 3 is a flow chart that schematically illustrates a method for compacting memory blocks, in accordance with an embodiment of the present invention;



FIG. 4 is a flow chart that schematically illustrates a method for data storage, in accordance with an embodiment of the present invention;



FIG. 5 is a flow chart that schematically illustrates a method for prioritized access to memory, in accordance with an embodiment of the present invention;



FIG. 6 is a diagram that schematically illustrates a process of prioritized execution of programming commands and read commands, in accordance with an embodiment of the present invention; and



FIG. 7 is a flow chart that schematically illustrates a method for automatic releasing of unutilized memory regions, in accordance with an embodiment of the present invention.





DETAILED DESCRIPTION OF EMBODIMENTS
Overview

Embodiments of the present invention provide improved methods and systems for memory management in memory systems comprising non-volatile memory devices. Although the embodiments described herein refer mainly to management of Solid State Disks (SSDs) by SSD controllers, the disclosed techniques can be applied in various other kinds of memory systems and by various other types of memory controllers.


In some of the disclosed techniques, a memory controller stores data in a non-volatile memory that includes multiple memory blocks. The memory controller applies a compaction (“garbage collection”) process that copies valid data from partially-filled memory blocks to new storage locations in order to clear memory blocks for erasure and new programming. In some embodiments, the memory controller defines two or more regions in the non-volatile memory, and carries out the compaction process separately and independently in each region. In an embodiment, the memory controller maintains different over-provisioning ratios (i.e., different ratios between the true physical capacity and of the memory and the capacity available to the host) in different regions. This technique is useful, for example, for assigning a high over-provisioning ratio to regions that store frequently-changing data, and a lower over-provisioning ratio to regions that store rarely-changing data.


In other disclosed techniques, the memory controller accepts from a host data belonging to one or more computer files or other host data-set items. The memory controller automatically identifies a portion of the data as belonging to a file (or other host data-set item) that is pre-specified as sensitive, such as an operating system Master File Table (MFT) or File Allocation Table (FAT) file whose corruption may have severe consequences on system performance. The memory controller stores the identified portion robustly using a relatively small number of bits per cell, and stores the data other than the identified portion using a higher number of bits per cell. The memory controller typically identifies the data portion in question independently of the host, i.e., without receiving any notification from the host that relates the data portion to the sensitive file.


In some disclosed techniques, the memory controller accepts memory access tasks (referred to as “threads”) for execution from the host. The memory controller assigns execution priorities to the threads, independently of the host, and executes the threads in accordance with the execution priorities. The memory controller may apply various policies using the execution priorities, such as giving precedence to readout commands over other commands or giving precedence to selected memory regions over others.


In other disclosed techniques, the memory controller accepts one or more computer files from the host, and stores the files in the non-volatile memory. The memory controller identifies, automatically and independently from the host, a memory region holding data that logically belongs to one of the files but is not actually utilized by the host. In an example embodiment, the file comprises a MFT or FAT file, and the identified region comprises one or more NULL entries in the file. Having identified the unutilized region, the memory controller releases the region for use in memory management, such as for increasing the over-provisioning overhead.


System Description


FIG. 1 is a block diagram that schematically illustrates a host system 20, in accordance with an embodiment of the present invention. In the present example, system 20 comprises a mobile computing device such as a notebook or laptop computer. Alternatively, the methods and systems described herein can be used in other computing devices such as Personal Digital Assistants (PDAs), in mobile communication terminals such as mobile phones, or in any other suitable host system.


Host system 20 comprises a host processor 24. The host processor typically runs a certain Operating System (OS), and may run any desired number of software applications. Host system 20 comprises a non-volatile storage device, in the present example a Solid-State Disk (SSD) 32. SSD 32 comprises a host interface 36 for communicating with host processor 24, an SSD controller 40, and one or more non-volatile memory devices 44. Each memory device 44 comprises an array 48 of multiple analog memory cells 52. A Read/Write (R/W) unit 56 writes data into memory cells 52 of array 48, and retrieves data from the memory cells.


In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Array 48 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and Charge Trap Flash (CTF) Flash cells, phase change RAM (PRAM, also referred to as Phase Change Memory—PCM), Nitride Read Only Memory (NROM), Ferroelectric RAM (FRAM), magnetic RAM (MRAM) and/or Dynamic RAM (DRAM) cells. Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.


NROM cells are described by Eitan et al., in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate,” Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.


The charge levels stored in memory cells 52 and/or the analog voltages or currents written into and read out of the memory cells are referred to herein collectively as analog values or storage values. The storage values may comprise threshold voltages, electrical charge levels, or any other suitable kind of storage values. R/W unit 56 stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming levels are selected from a finite set of possible levels, and each level corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming levels by writing one of four possible nominal storage values into the cell. Typically, R/W unit 56 converts data for storage in the memory device to analog storage values, and writes them into memory cells 52. When reading data out of array 48, R/W unit 56 converts the storage values of memory cells 52 into digital samples. Data is typically written to and read from the memory cells in groups that are referred to as pages. The R/W unit erases a block of cells 52 by applying one or more negative erasure pulses to the cells.


Some or all of the functions of SSD controller 40 may be implemented in hardware. Alternatively, SSD controller 40 may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements. In some embodiments, SSD controller 40 comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on non-transitory tangible media, such as magnetic, optical, or electronic memory.


The configuration of FIG. 1 is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. Elements that are not necessary for understanding the principles of the present invention have been omitted from the figure for clarity. In the example system configuration shown in FIG. 1, memory devices 44 and SSD controller 40 are implemented as two separate Integrated Circuits (ICs). In alternative embodiments, however, the memory devices and the SSD controller may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or System on Chip (SoC), and may be interconnected by an internal bus. Further alternatively, some or all of the SSD circuitry may reside on the same die on which one or more of the memory devices are disposed. Further alternatively, some or all of the functionality of SSD controller 40 can be implemented in software and carried out by host processor 24. In some embodiments, host processor 24 and SSD controller 40 may be fabricated on the same die, or on separate dies in the same device package.


In an example configuration of array 48, memory cells 52 are arranged in multiple rows and columns, and each memory cell comprises a floating-gate transistor. The gates of the transistors in each row are connected by word lines, and the sources of the transistors in each column are connected by bit lines. The memory array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Pages are sometimes sub-divided into sectors. In some embodiments, each page comprises an entire row of the array. In alternative embodiments, each row (word line) can be divided into two or more pages. For example, in some devices each row is divided into two pages, one comprising the odd-order cells and the other comprising the even-order cells. In a typical implementation, a two-bit-per-cell memory device may have four pages per row, a three-bit-per-cell memory device may have six pages per row, and a four-bit-per-cell memory device may have eight pages per row.


Erasing of cells is usually carried out in blocks that contain multiple pages. Typical memory devices may comprise several thousand erasure blocks. In some two-bit-per-cell MLC devices, each erasure block is on the order of thirty-two word lines, each comprising several tens of thousands of memory cells. Each word line of such a device is often partitioned into four pages (odd/even order cells, least/most significant bit of the cells). Three-bit-per cell devices having thirty-two word lines per erasure block would have 192 pages per erasure block, and four-bit-per-cell devices would have 256 pages per block. Alternatively, other block sizes and configurations can also be used. Some memory devices comprise two or more separate memory cell arrays, often referred to as planes. Since each plane has a certain “busy” period between successive write operations, data can be written alternately to the different planes in order to increase programming speed.


Typically, host processor 24 reads and writes data in SSD 32 by specifying logical addresses of the data (e.g., using Logical Block Addressing—LBA). SSD controller 40 translates the logical addresses into respective physical storage locations in memory devices 44. Typically, the host processor is unaware of the actual physical storage locations in which the data is stored, and the logical-to-physical address translation may change over time.


Independent Memory Block Compaction in Separate Memory Regions

In some embodiments, each memory array 48 is partitioned into multiple memory blocks, each block comprises multiple pages, and SSD controller 40 stores data by writing data pages into the memory. In a typical Flash memory, data can be programmed page-by-page, but erasure can only be performed on entire blocks. Therefore, SSD controller 40 typically uses logical-to-physical address translation. In such a scheme, storage commands received from host processor 24 typically specify logical addresses. SSD controller 40 translates the logical addresses into physical storage locations in memory devices 44.


In particular, when the data of a certain logical page is updated, the SSD controller writes the new data in a new physical page (since the old physical page holding the old data of that logical page cannot be erased individually). Over time, more and more physical pages in the memory blocks of SSD 32 gradually become invalid, since their data was updated and stored in other physical pages.


SSD controller 40 typically applies a compaction process, which copies valid data from partially-filled memory blocks (referred to as source blocks) to new physical locations (referred to as destination blocks) in a compact manner. The compaction process, which is also referred to as “garbage collection,” reduces regions of invalid data in the memory blocks and clears memory blocks for erasure and new programming.


In order to increase the efficiency of the garbage collection process, SSD 32 is typically over-provisioned in terms of memory size. In other words, the actual physical storage capacity of the SSD is larger than the specified logical capacity available to host processor 24. The aggregated size of the memory areas that do not hold valid data (“holes”) is referred to as an over-provisioning overhead. The over-provisioning overhead can be specified as an over-provisioning ratio, which is defined as a fraction of the specified system capacity. For example, when the SSD uses an over-provisioning ratio of 5% and the memory is full from the host's perspective, each memory block is only 95% programmed, on average.


When SSD 32 is over-provisioned, garbage collection can be performed more efficiently. In other words, the number of copy operations per block compaction can be reduced. The efficiency of the garbage collection process increases as a function of the over-provisioning ratio used in the system. Thus, increasing the over-provisioning ratio reduces the wearing of memory cells, and also increases the programming throughput. The effect of the over-provisioning overhead on cell wearing and storage throughput is particularly strong when the memory is full or nearly full.


In some embodiments of the present invention, SSD controller 40 defines two or more separate regions in memory devices 44, and carries out a separate and independent compaction process within each region. Each region comprises multiple blocks, and may be defined in a single memory device 44 or in multiple memory devices 44. Any desired number of regions may be defined. The regions may be specified in terms of logical or physical addresses. Typically, SSD controller 40 maintains different over-provisioning ratios in different regions.



FIG. 2 is a diagram that schematically illustrates a process of compacting memory blocks, in accordance with an embodiment of the present invention. In the present example, SSD controller 44 defines two memory regions denoted 60A and 60B in a certain memory device 44. Each region comprises multiple memory blocks. SSD controller 40 performs memory block compaction (“garbage collection”) separately in each of the two regions, independently of the compaction process carried out in the other region. In the example of FIG. 2, in region 60A the SSD controller compacts two source blocks 64A and 64B into a destination block 64C. In region 60B, the SSD controller compacts a source block 64D into a destination block 64E.


Applying compaction separately in different regions, and in particular setting different over-provisioning ratios in different regions, may improve the performance of SSD 32. For example, different data types may have different characteristics, which can be exploited by matching the over-provisioning ratio to the data type.


In an example embodiment, SSD controller 40 may define one region for storing data that changes frequently, and another region for data that changes rarely. The SSD controller may set a relatively high over-provisioning ratio in the region holding the frequently-changing data, and a relatively low over-provisioning ratio in the region holding the rarely-changing data. Matching the over-provisioning ratio to the frequency at which the data changes provides an improved compromise between storage capacity and storage throughput. Although the example above refers to two regions (holding frequently-changing and rarely-changing data), the SSD controller may alternatively define three or more regions corresponding to three or more update frequencies of the data. Each such region may be provided with a different over-provisioning ratio.


In an alternative embodiment, SSD controller 40 defines one region for storing data that is written in a sequential manner, i.e., to blocks of data that are written to successive storage addresses, and another region for data that is written non-sequentially. The SSD controller may assign different over-provisioning ratios to the two regions, e.g., a lower over-provisioning ratio to the region holding sequentially-written data.


In some embodiments, SSD controller 40 adapts the over-provisioning ratios of different memory regions over time in an adaptive manner. For example, the SSD controller may track the frequency-of-use of various memory regions over time, and assign each memory region a respective over-provisioning ratio based on the current frequency-of-use of that region. Further aspects of adaptive over-provisioning are addressed in U.S. patent application Ser. No. 12/822,207, which is assigned to the assignee of the present patent application and whose disclosure is incorporated herein by reference.


In some embodiments, certain computer files that are used by the OS of host processor 24 are modified frequently. Frequently-changing files may comprise, for example, File System (FS) files that indicate file storage locations and other file attributes in the host processor's file system. Such files may comprise, for example, a Master File Table (MFT) or File Allocation Table (FAT) file. As another example, files that store e-mail messages, calendar entries and related information also change frequently. Such files may comprise, for example, Personal Storage Table (PST) or Offline Storage Table (OST) files.


In some embodiments, SSD controller 40 recognizes a certain file as a frequently changing file, and assigns a high over-provisioning ratio to the memory region in SSD 32 in which this file is stored. The SSD controller may recognize any of the file type examples given above, or any other suitable type of file that changes frequently. Memory regions that hold other files are assigned lower over-provisioning ratios.


In some embodiments, SSD controller automatically identifies the memory region in which the file in question is stored, e.g., by detecting a file header or other characteristic that is indicative of the sought file. The automatic identification in these embodiments is performed by the SSD controller without any indication or guidance from host processor 24 as to the storage location of the file. In alternative embodiments, SSD controller 40 recognizes the file by accepting an indication from host processor 24 as to the storage location of the file.



FIG. 3 is a flow chart that schematically illustrates a method for compacting memory blocks, in accordance with an embodiment of the present invention. The method begins with SSD controller 40 defining multiple memory regions in memory devices 44, at a region definition step 70. The SSD controller defines a separate over-provisioning configuration for each memory region, at an over-provisioning definition step 74. The SSD controller compacts memory blocks independently in each region, at a compaction step 78. The compaction in each region is performed in accordance using the over-provisioning overhead defined for that region, and independently of the compaction that takes place in other regions.


When carrying out the compaction process in a given region, SSD controller 40 may choose memory blocks for compaction using any suitable criterion. In an embodiment, the SSD controller chooses memory blocks for compaction depending on the wear level and/or endurance of the memory blocks. For example, the SSD controller may prefer to compact memory blocks that have gone through relatively few Programming and Erasure (P/E) cycles, and which are expected to have high endurance.


In some embodiments, the SSD controller modifies the logical-to-physical address mapping in order to equalize the wear levels of the different physical memory blocks. For example, if certain LBAs are updated frequently, the SSD controller may re-map these LBAs to other physical memory blocks, in order to equalize the wearing of memory cells.


Reliable Storage of Sensitive Files

Some computer files used by the OS of host processor 24 may be sensitive to errors. Errors in some files may have severe consequences on the host system functionality or performance. Sensitive files may comprise, for example, file-system files such as MFT and FAT files, e-mail files such as PST and OST files, or any other suitable file.


(Some host systems may use various kinds of host data-sets that specify data-set items, not necessarily file systems that specify computer files. Host data-set items may comprise, for example, a file, a data structure, or any other suitable data item. In a given host data-set, certain data-set items may be regarded as sensitive. Although the example embodiments described herein refer mainly to computer files, the disclosed techniques can be used for reliable storage of any other suitable kind of host data-set items in any other suitable kind of host data-set.)


In some embodiments, SSD controller 40 automatically identifies incoming data that belongs to a file that is pre-specified as sensitive, and stores this data in a robust manner that is resilient to errors. This identification is carried out independently of the host, i.e., without relying on any notification from the host that relates the data to the sensitive file. For example, the SSD controller may store sensitive files using a small number of bits per cell, in comparison with the number of bits per cell used for storing other data. In an example embodiment, the SSD controller may store the data of a sensitive file at a density of one or two bits-per-cell, and store other data at a density of three bits-per-cell.



FIG. 4 is a flow chart that schematically illustrates a method for data storage, in accordance with an embodiment of the present invention. The method begins with SSD controller 40 accepts data for storage from host processor 24, at a data input step 80. The SSD controller checks whether the accepted data belongs to a sensitive file that was pre-specified for robust storage, at a checking step 84. If the data does not belong to a sensitive file, the SSD controller stores the data at a density of three bits-per-cell, at a normal storage step 88. If, on the other hand, the data is identified as belonging to a pre-specified sensitive file, the SSD controller stores the data at a density of two bits-per-cell, at a robust storage step 92.


The SSD controller may identify incoming data as belonging to a sensitive file using any suitable method, e.g., by identifying a file header or other characteristic data pattern.


Host-Independent Prioritization of Memory Access Tasks

In some embodiments, host processor 24 sends multiple memory access tasks to SSD controller 40 for execution in SSD 32. Each memory access task is referred to as a tag or thread, and may comprise, for example, a read command or a write command. The terms “memory access task,” “task,” “tag” and “thread” are all used interchangeably herein. The host processor sends subsequent threads without waiting for completion of previous threads, and the SSD controller has certain flexibility in defining the thread execution order.


In some embodiments, SSD controller 40 assigns execution priorities to incoming threads independently of the host, and executes the threads in SSD 32 in accordance with the assigned execution priorities. In some embodiments, each memory access task is of a certain type, and the SSD controller assigns the priority of each memory access task based on its type.


In an embodiment, SSD controller 40 assigns a high priority to readout tasks (i.e., to memory access tasks that request data readout from the memory), and lower priority to other tasks (e.g., programming tasks and status request tasks). In these embodiments, when multiple tasks are pending, the SSD controller gives precedence to execution of pending readout tasks. In many system configurations it is advantageous to give high priority to readout tasks, since the requested data may be needed for immediate use by the host system. Programming tasks are often less sensitive to delay, for example because the data to be programmed is already cached.


In another embodiment, the SSD controller assigns high priority to tasks relating to certain storage addresses. In an example embodiment, the SSD controller assigns high priority to one or more ranges of Logical Block Addresses (LBAs), and lower priorities to other LBAs. Memory access tasks relating to the high-priority LBAs will be executed first, at the expense of higher execution latency for memory access tasks relating to other LBAs.


In yet another embodiment, SSD controller 40 assigns high priority to tasks relating to certain files or file types. High-priority files may comprise, for example, file-system files such as MFT or FAT files, e-mail files such as PST or OST files, or any other suitable file type. SSD controller 40 will execute tasks relating to the high-priority files first, at the expense of higher execution latency for tasks relating to other files.


In alternative embodiments, SSD controller 40 may assign priorities to memory access tasks independently of the host processor based on any other suitable criteria. In some embodiments, the SSD controller may modify the priorities adaptively over time. For example, the SSD controller may identify, e.g., using statistical analysis, which memory regions are most important to the host processor, and increase the relative priority of tasks relating to these regions.



FIG. 5 is a flow chart that schematically illustrates a method for prioritized access to memory, in accordance with an embodiment of the present invention. The method begins with SSD controller 40 defining execution priorities for different types of memory access tasks, at a priority definition step 100. The SSD controller assigns the execution priorities independently of the host processor.


SSD controller 40 accepts from host processor 24 memory access tasks for execution in SSD 32, at a task input step 104. Each accepted task belongs to one of the above-defined types, and the host processor typically does not define execution priorities for the tasks. SSD controller 40 executes the accepted tasks in SSD 32, at a task execution step 108. The SSD controller executes the tasks in accordance with the execution priorities defined at step 100 above.


In some embodiments, SSD 32 is highly efficient in executing sequences of read commands or sequences of write commands, but is less efficient in executing sequences of intermixed read and write commands. In some embodiments, SSD controller 40 prioritizes the execution of memory access tasks such that multiple tasks of the same type (e.g., multiple readout tasks or multiple programming tasks) are executed consecutively. As a result, the overall throughput and efficiency of SSD 32 is improved.


In some embodiments, SSD controller 40 applies this sort of prioritization by queueing readout commands and programming commands in separate queues, and then selecting between the queues based on a certain selection criterion. The criterion typically causes the SSD controller to execute multiple readout tasks consecutively, or multiple programming tasks consecutively.



FIG. 6 is a diagram that schematically illustrates a process of prioritized execution of programming commands and read commands, in accordance with an embodiment of the present invention. A list 110 shows a sequence of memory access tasks in the order they are provided to SSD controller 40 by host processor 24. The example list comprises five programming commands and six readout commands.


SSD controller 40 separates the readout commands from the programming commands, and stores the programming commands in a write queue 114 and the readout commands in a read queue 118. At a selection step 122, the SSD controller selects the next task for execution from one of queues 114 and 118.


The selection criterion typically forms sequences of programming commands, and/or sequences of readout commands. For example, the selection criterion may define an order that serves M successive programming commands from queue 114, then N successive readout commands from queue 118, and so on. Selection of M and N enables setting of various trade-offs between execution efficiency and amount of re-ordering. Selection of M and N also enables setting different relative priority for readout commands vs. programming commands. At an execution step 126, the SSD controller executes the commands selected from the two queues.


As noted above, in some embodiments the SSD controller gives precedence to execution of readout tasks over other tasks. The queuing configuration of FIG. 6 can be used to implement this sort of prioritization, as well.


Host-Independent Trimming of Unused Memory Regions

In some embodiments, host processor 24 sends computer files for storage in SSD 32, and SSD controller 40 stores the files in memory devices 44. In some practical scenarios, some portions of the computer files are not actually utilized by the host processor. In some cases, certain regions in memory devices 44 logically belong to a valid computer file but do not contain data that is actually utilized by the host processor. In other cases, a file has been deleted (or rewritten to different logical addresses) by the host, leaving behind unutilized memory regions. In some embodiments, SSD controller 40 automatically identifies such unutilized memory regions, and releases (“trims”) them for use in memory management while continuing to hold the file in question in memory.


For example, in some embodiments the host processor stores a MFT or FAT file, which indicates storage locations and other attributes of files stored in SSD 32. Real-life MFT and FAT files often comprise many NULL entries that do not represent any active file. The NULL entries occupy storage space, but are not actually accessed by the host processor.


In some embodiments, SSD controller 40 automatically identifies the storage locations used for storing the MFT or FAT file, and identifies the NULL entries in the file. The identification of the storage locations and NULL entries is typically performed by the SSD controller independently of the host processor, i.e., without using any indication from the host processor as to the storage locations or NULL entries of the file.


Having identified the memory regions that hold the unutilized portions of the file, SSD controller 40 releases these memory regions for use in memory management. The released memory regions can be used, for example, as an additional over-provisioning overhead, or for any other suitable memory management function.


Although the embodiments described herein refer to MFT or FAT files, the disclosed technique can be used to release unutilized memory areas that logically belong to any other suitable file.



FIG. 7 is a flow chart that schematically illustrates a method for automatic releasing of unutilized memory regions, in accordance with an embodiment of the present invention. The method begins with SSD controller 40 accepting from host processor 24 data of one or more computer files for storage in SSD 32, at a file input step 130. The SSD controller stores the accepted data in memory devices 44.


The SSD controller automatically identifies memory regions that hold portions of the files that are not utilized by the host processor, at a region identification step 134. This identification is typically carried out independently of the host processor. The SSD controller then releases (“trims”) the identified memory regions, at a trimming step 138. The released memory regions are made available for increasing the over-provisioning ratio in SSD 32, or for carrying out any other memory management task by SSD controller 40.


It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

Claims
  • 1. A method, comprising: storing data in a non-volatile memory that includes multiple memory blocks;defining at least first and second regions in the non-volatile memory;defining a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and defining a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region;individually within each of the first and second regions and independently of the other region, compacting portions of the data by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.
  • 2. The method according to claim 1, wherein defining the first and second regions comprises assigning the first region for storing parts of the data that change at a first frequency, and assigning the second region for storing portions of the data that change at a second frequency, smaller than the first frequency.
  • 3. The method according to claim 2, and comprising setting the first over-provisioning ratio to be larger than the second over-provisioning ratio.
  • 4. The method according to claim 2, wherein defining the first and second regions comprises assigning the first region for storing frequently-changing data, and assigning the second region for storing rarely-changing data.
  • 5. The method according to claim 2, wherein the first region is used for storing a computer file that is known to change frequently.
  • 6. The method according to claim 5, wherein defining the first region comprises detecting storage locations of the non-volatile memory in which the computer file is stored.
  • 7. The method according to claim 1, wherein defining the first and second regions comprises assigning the first region for storing parts of the data that are written sequentially, and assigning the second region for storing portions of the data that are written non-sequentially.
  • 8. The method according to claim 1, and comprising modifying at least one of the first and second over-provisioning ratios over time.
  • 9. The method according to claim 1, wherein compacting the portions of the data comprises choosing the source memory blocks based on a selection criterion that equalizes wear of the non-volatile memory.
  • 10. The method according to claim 1, wherein storing the data comprises accepting commands to store the data in logical addresses, translating the logical addresses into respective physical storage locations in the non-volatile memory and storing the data in the physical storage locations, and comprising modifying translation of the logical addresses into the physical storage locations based on a criterion that equalizes wear of the non-volatile memory.
  • 11. Apparatus, comprising: an interface, which is configured to accept data for storage in a non-volatile memory; anda processor, which is configured to define at least first and second regions in the non-volatile memory, to define a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, to define a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region, and, individually within each of the first and second regions and independently of the other region, to compact portions of the data by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively.
  • 12. The apparatus according to claim 11, wherein the processor is configured to assign the first region for storing parts of the data that change at a first frequency, and to assign the second region for storing portions of the data that change at a second frequency, smaller than the first frequency.
  • 13. The apparatus according to claim 12, wherein the processor is configured to set the first over-provisioning ratio to be larger than the second over-provisioning ratio.
  • 14. The apparatus according to claim 12, wherein the processor is configured to assign the first region for storing frequently-changing data, and to assign the second region for storing rarely-changing data.
  • 15. The apparatus according to claim 12, wherein the first region is used for storing a computer file that is known to change frequently.
  • 16. The apparatus according to claim 15, wherein the processor is configured to detect storage locations of the non-volatile memory in which the computer file is stored.
  • 17. The apparatus according to claim 11, wherein the processor is configured to assign the first region for storing parts of the data that are written sequentially, and to assign the second region for storing portions of the data that are written non-sequentially.
  • 18. The apparatus according to claim 11, wherein the processor is configured to modify at least one of the first and second over-provisioning ratios over time.
  • 19. The apparatus according to claim 11, wherein the processor is configured to choose the source memory blocks for compaction based on a selection criterion that equalizes wear of the non-volatile memory.
  • 20. The apparatus according to claim 11, wherein the processor is configured to accept commands to store the data in logical addresses, to translate the logical addresses into respective physical storage locations in the non-volatile memory, to store the data in the physical storage locations, and to modify translation of the logical addresses into the physical storage locations based on a criterion that equalizes wear of the non-volatile memory.
CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application 61/326,858, filed Apr. 22, 2010, and U.S. Provisional Patent Application 61/286,814, filed Dec. 16, 2009, whose disclosures are incorporated herein by reference.

US Referenced Citations (572)
Number Name Date Kind
3668631 Griffith et al. Jun 1972 A
3668632 Oldham Jun 1972 A
4058851 Scheuneman Nov 1977 A
4112502 Scheuneman Sep 1978 A
4394763 Nagano et al. Jul 1983 A
4413339 Riggle et al. Nov 1983 A
4556961 Iwahashi et al. Dec 1985 A
4558431 Satoh Dec 1985 A
4608687 Dutton Aug 1986 A
4654847 Dutton Mar 1987 A
4661929 Aoki et al. Apr 1987 A
4768171 Tada Aug 1988 A
4811285 Walker et al. Mar 1989 A
4899342 Potter et al. Feb 1990 A
4910706 Hyatt Mar 1990 A
4993029 Galbraith et al. Feb 1991 A
5056089 Furuta et al. Oct 1991 A
5077722 Geist et al. Dec 1991 A
5126808 Montalvo et al. Jun 1992 A
5163021 Mehrotra et al. Nov 1992 A
5172338 Mehrotra et al. Dec 1992 A
5182558 Mayo Jan 1993 A
5182752 DeRoo et al. Jan 1993 A
5191584 Anderson Mar 1993 A
5200959 Gross et al. Apr 1993 A
5237535 Mielke et al. Aug 1993 A
5272669 Samachisa et al. Dec 1993 A
5276649 Hoshita et al. Jan 1994 A
5287469 Tsuboi Feb 1994 A
5365484 Cleveland et al. Nov 1994 A
5388064 Khan Feb 1995 A
5416646 Shirai May 1995 A
5416782 Wells et al. May 1995 A
5446854 Khalidi et al. Aug 1995 A
5450424 Okugaki et al. Sep 1995 A
5469444 Endoh et al. Nov 1995 A
5473753 Wells et al. Dec 1995 A
5479170 Cauwenberghs et al. Dec 1995 A
5508958 Fazio et al. Apr 1996 A
5519831 Holzhammer May 1996 A
5532962 Auclair et al. Jul 1996 A
5533190 Binford et al. Jul 1996 A
5541886 Hasbun Jul 1996 A
5600677 Citta et al. Feb 1997 A
5638320 Wong et al. Jun 1997 A
5657332 Auclair et al. Aug 1997 A
5675540 Roohparvar Oct 1997 A
5682352 Wong et al. Oct 1997 A
5687114 Khan Nov 1997 A
5696717 Koh Dec 1997 A
5726649 Tamaru et al. Mar 1998 A
5726934 Tran et al. Mar 1998 A
5742752 De Koning Apr 1998 A
5748533 Dunlap et al. May 1998 A
5748534 Dunlap et al. May 1998 A
5751637 Chen et al. May 1998 A
5761402 Kaneda et al. Jun 1998 A
5798966 Keeney Aug 1998 A
5799200 Brant et al. Aug 1998 A
5801985 Roohparvar et al. Sep 1998 A
5838832 Barnsley Nov 1998 A
5860106 Domen et al. Jan 1999 A
5867114 Barbir Feb 1999 A
5867428 Ishii et al. Feb 1999 A
5867429 Chen et al. Feb 1999 A
5877986 Harari et al. Mar 1999 A
5889937 Tamagawa Mar 1999 A
5901089 Korsh et al. May 1999 A
5909449 So et al. Jun 1999 A
5912906 Wu et al. Jun 1999 A
5930167 Lee et al. Jul 1999 A
5937424 Leak et al. Aug 1999 A
5942004 Cappelletti Aug 1999 A
5946716 Karp et al. Aug 1999 A
5969986 Wong et al. Oct 1999 A
5982668 Ishii et al. Nov 1999 A
5991517 Harari et al. Nov 1999 A
5995417 Chen et al. Nov 1999 A
6009014 Hollmer et al. Dec 1999 A
6009016 Ishii et al. Dec 1999 A
6023425 Ishii et al. Feb 2000 A
6034891 Norman Mar 2000 A
6040993 Chen et al. Mar 2000 A
6041430 Yamauchi Mar 2000 A
6073204 Lakhani et al. Jun 2000 A
6101614 Gonzales et al. Aug 2000 A
6128237 Shirley et al. Oct 2000 A
6134140 Tanaka et al. Oct 2000 A
6134143 Norman Oct 2000 A
6134631 Jennings Oct 2000 A
6141261 Patti Oct 2000 A
6151246 So et al. Nov 2000 A
6157573 Ishii et al. Dec 2000 A
6166962 Chen et al. Dec 2000 A
6169691 Pasotti et al. Jan 2001 B1
6178466 Gilbertson et al. Jan 2001 B1
6185134 Tanaka et al. Feb 2001 B1
6209113 Roohparvar Mar 2001 B1
6212654 Lou et al. Apr 2001 B1
6219276 Parker Apr 2001 B1
6219447 Lee et al. Apr 2001 B1
6222762 Guterman et al. Apr 2001 B1
6230233 Lofgren et al. May 2001 B1
6240458 Gilbertson May 2001 B1
6259627 Wong Jul 2001 B1
6275419 Guterman et al. Aug 2001 B1
6278632 Chevallier Aug 2001 B1
6279069 Robinson et al. Aug 2001 B1
6288944 Kawamura Sep 2001 B1
6292394 Cohen et al. Sep 2001 B1
6301151 Engh et al. Oct 2001 B1
6304486 Yano Oct 2001 B1
6307776 So et al. Oct 2001 B1
6314044 Sasaki et al. Nov 2001 B1
6317363 Guterman et al. Nov 2001 B1
6317364 Guterman et al. Nov 2001 B1
6345004 Omura et al. Feb 2002 B1
6360346 Miyauchi et al. Mar 2002 B1
6363008 Wong Mar 2002 B1
6363454 Lakhani et al. Mar 2002 B1
6366496 Torelli et al. Apr 2002 B1
6385092 Ishii et al. May 2002 B1
6392932 Ishii et al. May 2002 B1
6396742 Korsh et al. May 2002 B1
6397364 Barkan May 2002 B1
6405323 Lin et al. Jun 2002 B1
6405342 Lee Jun 2002 B1
6418060 Yong et al. Jul 2002 B1
6442585 Dean et al. Aug 2002 B1
6445602 Kokudo et al. Sep 2002 B1
6452838 Ishii et al. Sep 2002 B1
6456528 Chen Sep 2002 B1
6466476 Wong et al. Oct 2002 B1
6467062 Barkan Oct 2002 B1
6469931 Ban et al. Oct 2002 B1
6480948 Virajpet et al. Nov 2002 B1
6490236 Fukuda et al. Dec 2002 B1
6522580 Chen et al. Feb 2003 B2
6525952 Araki et al. Feb 2003 B2
6532556 Wong et al. Mar 2003 B1
6538922 Khalid et al. Mar 2003 B1
6549464 Tanaka et al. Apr 2003 B2
6553510 Pekny Apr 2003 B1
6558967 Wong May 2003 B1
6560152 Cernea May 2003 B1
6567311 Ishii et al. May 2003 B2
6577539 Iwahashi Jun 2003 B2
6584012 Banks Jun 2003 B2
6615307 Roohparvar Sep 2003 B1
6621739 Gonzalez et al. Sep 2003 B2
6640326 Buckingham et al. Oct 2003 B1
6643169 Rudelic et al. Nov 2003 B2
6646913 Micheloni et al. Nov 2003 B2
6678192 Gongwer et al. Jan 2004 B2
6683811 Ishii et al. Jan 2004 B2
6687155 Nagasue Feb 2004 B2
6707748 Lin et al. Mar 2004 B2
6708257 Bao Mar 2004 B2
6714449 Khalid Mar 2004 B2
6717847 Chen Apr 2004 B2
6731557 Beretta May 2004 B2
6732250 Durrant May 2004 B2
6738293 Iwahashi May 2004 B1
6751766 Guterman et al. Jun 2004 B2
6757193 Chen et al. Jun 2004 B2
6774808 Hibbs et al. Aug 2004 B1
6781877 Cernea et al. Aug 2004 B2
6804805 Rub Oct 2004 B2
6807095 Chen et al. Oct 2004 B2
6807101 Ooishi et al. Oct 2004 B2
6809964 Moschopoulos et al. Oct 2004 B2
6819592 Noguchi et al. Nov 2004 B2
6829167 Tu et al. Dec 2004 B2
6845052 Ho et al. Jan 2005 B1
6851018 Wyatt et al. Feb 2005 B2
6851081 Yamamoto Feb 2005 B2
6856546 Guterman et al. Feb 2005 B2
6862218 Guterman et al. Mar 2005 B2
6870767 Rudelic et al. Mar 2005 B2
6870773 Noguchi et al. Mar 2005 B2
6873552 Ishii et al. Mar 2005 B2
6879520 Hosono et al. Apr 2005 B2
6882567 Wong Apr 2005 B1
6894926 Guterman et al. May 2005 B2
6907497 Hosono et al. Jun 2005 B2
6925009 Noguchi et al. Aug 2005 B2
6930925 Guo et al. Aug 2005 B2
6934188 Roohparvar Aug 2005 B2
6937511 Hsu et al. Aug 2005 B2
6958938 Noguchi et al. Oct 2005 B2
6963505 Cohen Nov 2005 B2
6972993 Conley et al. Dec 2005 B2
6973531 Chang et al. Dec 2005 B1
6988175 Lasser Jan 2006 B2
6992932 Cohen Jan 2006 B2
6999344 Hosono et al. Feb 2006 B2
7002843 Guterman et al. Feb 2006 B2
7006379 Noguchi et al. Feb 2006 B2
7012835 Gonzalez et al. Mar 2006 B2
7020017 Chen et al. Mar 2006 B2
7023735 Ban et al. Apr 2006 B2
7031210 Park et al. Apr 2006 B2
7031214 Tran Apr 2006 B2
7031216 You Apr 2006 B2
7039846 Hewitt et al. May 2006 B2
7042766 Wang et al. May 2006 B1
7054193 Wong May 2006 B1
7054199 Lee et al. May 2006 B2
7057958 So et al. Jun 2006 B2
7065147 Ophir et al. Jun 2006 B2
7068539 Guterman et al. Jun 2006 B2
7071849 Zhang Jul 2006 B2
7072222 Ishii et al. Jul 2006 B2
7079555 Baydar et al. Jul 2006 B2
7088615 Guterman et al. Aug 2006 B2
7099194 Tu et al. Aug 2006 B2
7102924 Chen et al. Sep 2006 B2
7113432 Mokhlesi Sep 2006 B2
7130210 Bathul et al. Oct 2006 B2
7139192 Wong Nov 2006 B1
7139198 Guterman et al. Nov 2006 B2
7145805 Ishii et al. Dec 2006 B2
7151692 Wu et al. Dec 2006 B2
7158058 Yu Jan 2007 B1
7170781 So et al. Jan 2007 B2
7170802 Cernea et al. Jan 2007 B2
7173859 Hemink Feb 2007 B2
7177184 Chen Feb 2007 B2
7177195 Gonzalez et al. Feb 2007 B2
7177199 Chen et al. Feb 2007 B2
7177200 Ronen et al. Feb 2007 B2
7184338 Nakagawa et al. Feb 2007 B2
7187195 Kim Mar 2007 B2
7187592 Guterman et al. Mar 2007 B2
7190614 Wu Mar 2007 B2
7193898 Cernea Mar 2007 B2
7193921 Choi et al. Mar 2007 B2
7196644 Anderson et al. Mar 2007 B1
7196928 Chen Mar 2007 B2
7196933 Shibata Mar 2007 B2
7197594 Raz et al. Mar 2007 B2
7200062 Kinsely et al. Apr 2007 B2
7210077 Brandenberger et al. Apr 2007 B2
7221592 Nazarian May 2007 B2
7224613 Chen et al. May 2007 B2
7231474 Helms et al. Jun 2007 B1
7231562 Ohlhoff et al. Jun 2007 B2
7243275 Gongwer et al. Jul 2007 B2
7254690 Rao Aug 2007 B2
7254763 Aadsen et al. Aug 2007 B2
7257027 Park Aug 2007 B2
7259987 Chen et al. Aug 2007 B2
7266026 Gongwer et al. Sep 2007 B2
7266069 Chu Sep 2007 B2
7269066 Nguyen et al. Sep 2007 B2
7272757 Stocken Sep 2007 B2
7274611 Roohparvar Sep 2007 B2
7277355 Tanzawa Oct 2007 B2
7280398 Lee et al. Oct 2007 B1
7280409 Misumi et al. Oct 2007 B2
7280415 Hwang et al. Oct 2007 B2
7283399 Ishii et al. Oct 2007 B2
7289344 Chen Oct 2007 B2
7301807 Khalid et al. Nov 2007 B2
7301817 Li et al. Nov 2007 B2
7308525 Lasser et al. Dec 2007 B2
7310255 Chan Dec 2007 B2
7310269 Shibata Dec 2007 B2
7310271 Lee Dec 2007 B2
7310272 Mokhlesi et al. Dec 2007 B1
7310347 Lasser Dec 2007 B2
7312727 Feng et al. Dec 2007 B1
7321509 Chen et al. Jan 2008 B2
7328384 Kulkarni et al. Feb 2008 B1
7342831 Mokhlesi et al. Mar 2008 B2
7343330 Boesjes et al. Mar 2008 B1
7345924 Nguyen et al. Mar 2008 B2
7345928 Li Mar 2008 B2
7349263 Kim et al. Mar 2008 B2
7356755 Fackenthal Apr 2008 B2
7363420 Lin et al. Apr 2008 B2
7365671 Anderson Apr 2008 B1
7388781 Litsyn et al. Jun 2008 B2
7397697 So et al. Jul 2008 B2
7405974 Yaoi et al. Jul 2008 B2
7405979 Ishii et al. Jul 2008 B2
7408804 Hemink et al. Aug 2008 B2
7408810 Aritome et al. Aug 2008 B2
7409473 Conley et al. Aug 2008 B2
7409623 Baker et al. Aug 2008 B2
7420847 Li Sep 2008 B2
7433231 Aritome Oct 2008 B2
7433697 Karaoguz et al. Oct 2008 B2
7434111 Sugiura et al. Oct 2008 B2
7437498 Ronen Oct 2008 B2
7440324 Mokhlesi Oct 2008 B2
7440331 Hemink Oct 2008 B2
7441067 Gorobets et al. Oct 2008 B2
7447970 Wu et al. Nov 2008 B2
7450421 Mokhesi et al. Nov 2008 B2
7453737 Ha Nov 2008 B2
7457163 Hemink Nov 2008 B2
7457897 Lee et al. Nov 2008 B1
7460410 Nagai et al. Dec 2008 B2
7460412 Lee et al. Dec 2008 B2
7466592 Mitani et al. Dec 2008 B2
7468907 Kang et al. Dec 2008 B2
7468911 Lutze et al. Dec 2008 B2
7469049 Feng Dec 2008 B1
7471581 Tran et al. Dec 2008 B2
7483319 Brown Jan 2009 B2
7487329 Hepkin et al. Feb 2009 B2
7487394 Forhan et al. Feb 2009 B2
7492641 Hosono et al. Feb 2009 B2
7508710 Mokhlesi Mar 2009 B2
7526711 Orio Apr 2009 B2
7539061 Lee May 2009 B2
7539062 Doyle May 2009 B2
7551492 Kim Jun 2009 B2
7558109 Brandman et al. Jul 2009 B2
7558839 McGovern Jul 2009 B1
7568135 Cornwell et al. Jul 2009 B2
7570520 Kamei et al. Aug 2009 B2
7574555 Porat et al. Aug 2009 B2
7590002 Mokhlesi et al. Sep 2009 B2
7593259 Kim Sep 2009 B2
7594093 Kancherla Sep 2009 B1
7596707 Vemula Sep 2009 B1
7609787 Jahan et al. Oct 2009 B2
7613043 Cornwell et al. Nov 2009 B2
7616498 Mokhlesi et al. Nov 2009 B2
7619918 Aritome Nov 2009 B2
7631245 Lasser Dec 2009 B2
7633798 Sarin et al. Dec 2009 B2
7633802 Mokhlesi Dec 2009 B2
7639532 Roohparvar et al. Dec 2009 B2
7644347 Alexander et al. Jan 2010 B2
7656734 Thorp et al. Feb 2010 B2
7660158 Aritome Feb 2010 B2
7660183 Ware et al. Feb 2010 B2
7661000 Ueda et al. Feb 2010 B2
7661054 Huffman et al. Feb 2010 B2
7665007 Yang et al. Feb 2010 B2
7680987 Clark et al. Mar 2010 B1
7733712 Walston et al. Jun 2010 B1
7742351 Inoue et al. Jun 2010 B2
7761624 Karamcheti et al. Jul 2010 B2
7797609 Neuman Sep 2010 B2
7810017 Radke Oct 2010 B2
7848149 Gonzalez et al. Dec 2010 B2
7869273 Lee et al. Jan 2011 B2
7885119 Li Feb 2011 B2
7904783 Brandman et al. Mar 2011 B2
7928497 Yaegashi Apr 2011 B2
7929549 Talbot Apr 2011 B1
7930515 Gupta et al. Apr 2011 B2
7945825 Cohen et al. May 2011 B2
7978516 Olbrich et al. Jul 2011 B2
8014094 Jin Sep 2011 B1
8037380 Cagno et al. Oct 2011 B2
8040744 Gorobets et al. Oct 2011 B2
8065583 Radke Nov 2011 B2
8479080 Shalvi et al. Jul 2013 B1
20010002172 Tanaka et al. May 2001 A1
20010006479 Ikehashi et al. Jul 2001 A1
20020038440 Barkan Mar 2002 A1
20020056064 Kidorf et al. May 2002 A1
20020118574 Gongwer et al. Aug 2002 A1
20020133684 Anderson Sep 2002 A1
20020166091 Kidorf et al. Nov 2002 A1
20020174295 Ulrich et al. Nov 2002 A1
20020196510 Hietala et al. Dec 2002 A1
20030002348 Chen et al. Jan 2003 A1
20030103400 Van Tran Jun 2003 A1
20030161183 Tran Aug 2003 A1
20030189856 Cho et al. Oct 2003 A1
20040057265 Mirabel et al. Mar 2004 A1
20040057285 Cernea et al. Mar 2004 A1
20040083333 Chang et al. Apr 2004 A1
20040083334 Chang et al. Apr 2004 A1
20040105311 Cernea et al. Jun 2004 A1
20040114437 Li Jun 2004 A1
20040160842 Fukiage Aug 2004 A1
20040223371 Roohparvar Nov 2004 A1
20050007802 Gerpheide Jan 2005 A1
20050013165 Ban Jan 2005 A1
20050024941 Lasser et al. Feb 2005 A1
20050024978 Ronen Feb 2005 A1
20050030788 Parkinson et al. Feb 2005 A1
20050086574 Fackenthal Apr 2005 A1
20050121436 Kamitani et al. Jun 2005 A1
20050144361 Gonzalez et al. Jun 2005 A1
20050157555 Ono et al. Jul 2005 A1
20050162913 Chen Jul 2005 A1
20050169051 Khalid et al. Aug 2005 A1
20050189649 Maruyama et al. Sep 2005 A1
20050213393 Lasser Sep 2005 A1
20050224853 Ohkawa Oct 2005 A1
20050240745 Iyer et al. Oct 2005 A1
20050243626 Ronen Nov 2005 A1
20060004952 Lasser Jan 2006 A1
20060028875 Avraham et al. Feb 2006 A1
20060028877 Meir Feb 2006 A1
20060101193 Murin May 2006 A1
20060106972 Gorobets et al. May 2006 A1
20060107136 Gongwer et al. May 2006 A1
20060129750 Lee et al. Jun 2006 A1
20060133141 Gorobets Jun 2006 A1
20060156189 Tomlin Jul 2006 A1
20060179334 Brittain et al. Aug 2006 A1
20060190699 Lee Aug 2006 A1
20060203546 Lasser Sep 2006 A1
20060218359 Sanders et al. Sep 2006 A1
20060221692 Chen Oct 2006 A1
20060221705 Hemink et al. Oct 2006 A1
20060221714 Li et al. Oct 2006 A1
20060239077 Park et al. Oct 2006 A1
20060239081 Roohparvar Oct 2006 A1
20060256620 Nguyen et al. Nov 2006 A1
20060256626 Werner et al. Nov 2006 A1
20060256891 Yuan et al. Nov 2006 A1
20060271748 Jain et al. Nov 2006 A1
20060285392 Incarnati et al. Dec 2006 A1
20060285396 Ha Dec 2006 A1
20070006013 Moshayedi et al. Jan 2007 A1
20070019481 Park Jan 2007 A1
20070033581 Tomlin et al. Feb 2007 A1
20070047314 Goda et al. Mar 2007 A1
20070047326 Nguyen et al. Mar 2007 A1
20070050536 Kolokowsky Mar 2007 A1
20070058446 Hwang et al. Mar 2007 A1
20070061502 Lasser et al. Mar 2007 A1
20070067667 Ikeuchi et al. Mar 2007 A1
20070074093 Lasser Mar 2007 A1
20070086239 Litsyn et al. Apr 2007 A1
20070086260 Sinclair Apr 2007 A1
20070089034 Litsyn et al. Apr 2007 A1
20070091677 Lasser et al. Apr 2007 A1
20070091694 Lee et al. Apr 2007 A1
20070103978 Conley et al. May 2007 A1
20070103986 Chen May 2007 A1
20070104211 Opsasnick May 2007 A1
20070109845 Chen May 2007 A1
20070109849 Chen May 2007 A1
20070115726 Cohen et al. May 2007 A1
20070118713 Guterman et al. May 2007 A1
20070143378 Gorobets Jun 2007 A1
20070143531 Atri Jun 2007 A1
20070159889 Kang et al. Jul 2007 A1
20070159892 Kang et al. Jul 2007 A1
20070159907 Kwak Jul 2007 A1
20070168837 Murin Jul 2007 A1
20070171714 Wu et al. Jul 2007 A1
20070183210 Choi et al. Aug 2007 A1
20070189073 Aritome Aug 2007 A1
20070195602 Fong et al. Aug 2007 A1
20070206426 Mokhlesi Sep 2007 A1
20070208904 Hsieh et al. Sep 2007 A1
20070226599 Motwani Sep 2007 A1
20070236990 Aritome Oct 2007 A1
20070253249 Kang et al. Nov 2007 A1
20070256620 Viggiano et al. Nov 2007 A1
20070263455 Cornwell et al. Nov 2007 A1
20070266232 Rodgers et al. Nov 2007 A1
20070271424 Lee et al. Nov 2007 A1
20070280000 Fujiu et al. Dec 2007 A1
20070291571 Balasundaram Dec 2007 A1
20070297234 Cernea et al. Dec 2007 A1
20080010395 Mylly et al. Jan 2008 A1
20080025121 Tanzawa Jan 2008 A1
20080043535 Roohparvar Feb 2008 A1
20080049504 Kasahara et al. Feb 2008 A1
20080049506 Guterman Feb 2008 A1
20080052446 Lasser et al. Feb 2008 A1
20080055993 Lee Mar 2008 A1
20080080243 Edahiro et al. Apr 2008 A1
20080082730 Kim et al. Apr 2008 A1
20080089123 Chae et al. Apr 2008 A1
20080104309 Cheon et al. May 2008 A1
20080104312 Lasser May 2008 A1
20080109590 Jung et al. May 2008 A1
20080115017 Jacobson May 2008 A1
20080123420 Brandman et al. May 2008 A1
20080123426 Lutze et al. May 2008 A1
20080126686 Sokolov et al. May 2008 A1
20080130341 Shalvi et al. Jun 2008 A1
20080148115 Sokolov et al. Jun 2008 A1
20080151618 Sharon et al. Jun 2008 A1
20080151667 Miu et al. Jun 2008 A1
20080158958 Sokolov et al. Jul 2008 A1
20080181001 Shalvi Jul 2008 A1
20080198650 Shalvi et al. Aug 2008 A1
20080198654 Toda Aug 2008 A1
20080209116 Caulkins Aug 2008 A1
20080209304 Winarski et al. Aug 2008 A1
20080215798 Sharon et al. Sep 2008 A1
20080219050 Shalvi et al. Sep 2008 A1
20080239093 Easwar et al. Oct 2008 A1
20080239812 Abiko et al. Oct 2008 A1
20080253188 Aritome Oct 2008 A1
20080263262 Sokolov et al. Oct 2008 A1
20080263676 Mo et al. Oct 2008 A1
20080270730 Lasser et al. Oct 2008 A1
20080282106 Shalvi et al. Nov 2008 A1
20080288714 Salomon et al. Nov 2008 A1
20090013233 Radke Jan 2009 A1
20090024905 Shalvi et al. Jan 2009 A1
20090034337 Aritome Feb 2009 A1
20090043831 Antonopoulos et al. Feb 2009 A1
20090043951 Shalvi et al. Feb 2009 A1
20090049234 Oh et al. Feb 2009 A1
20090073762 Lee et al. Mar 2009 A1
20090086542 Lee et al. Apr 2009 A1
20090089484 Chu Apr 2009 A1
20090091979 Shalvi Apr 2009 A1
20090094930 Schwoerer Apr 2009 A1
20090106485 Anholt Apr 2009 A1
20090112949 Ergan et al. Apr 2009 A1
20090132755 Radke May 2009 A1
20090144600 Perlmutter et al. Jun 2009 A1
20090150894 Huang et al. Jun 2009 A1
20090157950 Selinger Jun 2009 A1
20090157964 Kasorla et al. Jun 2009 A1
20090158126 Perlmutter et al. Jun 2009 A1
20090168524 Golov et al. Jul 2009 A1
20090172257 Prins et al. Jul 2009 A1
20090172261 Prins et al. Jul 2009 A1
20090193184 Yu et al. Jul 2009 A1
20090199074 Sommer et al. Aug 2009 A1
20090204824 Lin et al. Aug 2009 A1
20090204872 Yu et al. Aug 2009 A1
20090213653 Perlmutter et al. Aug 2009 A1
20090213654 Perlmutter et al. Aug 2009 A1
20090225595 Kim Sep 2009 A1
20090228761 Perlmutter et al. Sep 2009 A1
20090240872 Perlmutter et al. Sep 2009 A1
20090265509 Klein Oct 2009 A1
20090300227 Nochimowski et al. Dec 2009 A1
20090323412 Mokhlesi et al. Dec 2009 A1
20090327608 Eschmann Dec 2009 A1
20100017650 Chin et al. Jan 2010 A1
20100034022 Dutta et al. Feb 2010 A1
20100057976 Lasser Mar 2010 A1
20100061151 Miwa et al. Mar 2010 A1
20100082883 Chen et al. Apr 2010 A1
20100083247 Kanevsky et al. Apr 2010 A1
20100110580 Takashima May 2010 A1
20100124088 Shalvi et al. May 2010 A1
20100131697 Alrod et al. May 2010 A1
20100131827 Sokolov et al. May 2010 A1
20100142268 Aritome Jun 2010 A1
20100142277 Yang et al. Jun 2010 A1
20100157675 Shalvi et al. Jun 2010 A1
20100165689 Rotbard et al. Jul 2010 A1
20100169547 Ou Jul 2010 A1
20100169743 Vogan et al. Jul 2010 A1
20100174847 Paley et al. Jul 2010 A1
20100195390 Shalvi Aug 2010 A1
20100199150 Shalvi et al. Aug 2010 A1
20100211803 Lablans Aug 2010 A1
20100220509 Sokolov et al. Sep 2010 A1
20100220510 Shalvi Sep 2010 A1
20100250836 Sokolov et al. Sep 2010 A1
20100287217 Borchers et al. Nov 2010 A1
20110010489 Yeh Jan 2011 A1
20110060969 Ramamoorthy et al. Mar 2011 A1
20110066793 Burd Mar 2011 A1
20110075482 Shepard et al. Mar 2011 A1
20110107049 Kwon et al. May 2011 A1
20110149657 Haratsch et al. Jun 2011 A1
20110199823 Bar-Or et al. Aug 2011 A1
20110302354 Miller Dec 2011 A1
Foreign Referenced Citations (43)
Number Date Country
0783754 Jul 1997 EP
1434236 Jun 2004 EP
1605509 Dec 2005 EP
9610256 Apr 1996 WO
9828745 Jul 1998 WO
2002100112 Dec 2002 WO
03100791 Dec 2003 WO
2007046084 Apr 2007 WO
2007132452 Nov 2007 WO
2007132453 Nov 2007 WO
2007132456 Nov 2007 WO
2007132457 Nov 2007 WO
2007132458 Nov 2007 WO
2007146010 Dec 2007 WO
2008026203 Mar 2008 WO
2008053472 May 2008 WO
2008053473 May 2008 WO
2008068747 Jun 2008 WO
2008077284 Jul 2008 WO
2008083131 Jul 2008 WO
2008099958 Aug 2008 WO
2008111058 Sep 2008 WO
2008124760 Oct 2008 WO
2008139441 Nov 2008 WO
2009037691 Mar 2009 WO
2009037697 Mar 2009 WO
2009038961 Mar 2009 WO
2009050703 Apr 2009 WO
2009053961 Apr 2009 WO
2009053962 Apr 2009 WO
2009053963 Apr 2009 WO
2009063450 May 2009 WO
2009072100 Jun 2009 WO
2009072101 Jun 2009 WO
2009072102 Jun 2009 WO
2009072103 Jun 2009 WO
2009072104 Jun 2009 WO
2009072105 Jun 2009 WO
2009074978 Jun 2009 WO
2009074979 Jun 2009 WO
2009078006 Jun 2009 WO
2009095902 Aug 2009 WO
2011024015 Mar 2011 WO
Non-Patent Literature Citations (156)
Entry
Ankolekar et al., “Multibit Error-Correction Methods for Latency-Constrained Flash Memory Systems”, IEEE Transactions on Device and Materials Reliability, vol. 10, No. 1, pp. 33-39, Mar. 2010.
U.S. Appl. No. 12/344,233 Official Action dated Jun. 24, 2011.
U.S. Appl. No. 11/995,813 Official Action dated Jun. 16, 2011.
Berman et al., “Mitigating Inter-Cell Coupling Effects in MLC NAND Flash via Constrained Coding”, Flash Memory Summit, Santa Clara, USA, Aug. 19, 2010.
U.S. Appl. No. 12/178,318 Official Action dated May 31, 2011.
CN Patent Application # 200780026181.3 Official Action dated Apr. 8, 2011.
US 7,161,836, 01/2007, Wan et al. (withdrawn).
Agrell et al., “Closest Point Search in Lattices”, IEEE Transactions on Information Theory, vol. 48, No. 8, pp. 2201-2214, Aug. 2002.
Bez et al., “Introduction to Flash memory”, Proceedings of the IEEE, vol. 91, No. 4, pp. 489-502, Apr. 2003.
Blahut, R.E., “Theory and Practice of Error Control Codes,” Addison-Wesley, May 1984, section 3.2, pp. 47-48.
Chang, L., “Hybrid Solid State Disks: Combining Heterogeneous NAND Flash in Large SSDs”, ASPDAC, Jan. 2008.
Cho et al., “Multi-Level NAND Flash Memory with Non-Uniform Threshold Voltage Distribution,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 5-7, 2001, pp. 28-29 and 424.
Compaq et al., “Universal Serial Bus Specification”, revision 2.0, Apr. 27, 2000.
Databahn™, “Flash memory controller IP”, Denali Software, Inc., 1994 https://www.denali.com/en/products/databahn—flash.jsp.
Datalight, Inc., “FlashFX Pro 3.1 High Performance Flash Manager for Rapid Development of Reliable Products”, Nov. 16, 2006.
Duann, N., Silicon Motion Presentation “SLC & MLC Hybrid”, Flash Memory Summit, Santa Clara, USA, Aug. 2008.
Eitan et al., “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?”, Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), pp. 522-524, Tokyo, Japan 1999.
Eitan et al., “Multilevel Flash Cells and their Trade-Offs”, Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), pp. 169-172, New York, USA 1996.
Engh et al., “A self adaptive programming method with 5 mV accuracy for multi-level storage in FLASH”, pp. 115-118, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, May 12-15, 2002.
Engineering Windows 7, “Support and Q&A for Solid-State Drives”, e7blog, May 5, 2009.
Goodman et al., “On-Chip FCC for Multi-Level Random Access Memories,” Proceedings of the IEEE/CAM Information Theory Workshop, Ithaca, USA, Jun. 25-29, 1989.
Gotou, H., “An Experimental Confirmation of Automatic Threshold Voltage Convergence in a Flash Memory Using Alternating Word-Line Voltage Pulses”, IEEE Electron Device Letters, vol. 18, No. 10, pp. 503-505, Oct. 1997.
Han et al., “An Intelligent Garbage Collection Algorithm for Flash Memory Storages”, Computational Science and Its Applications—ICCSA 2006, vol. 3980/2006, pp. 1019-1027, Springer Berlin / Heidelberg, Germany, May 11, 2006.
Han et al., “CATA: A Garbage Collection Scheme for Flash Memory File Systems”, Ubiquitous Intelligence and Computing, vol. 4159/2006, pp. 103-112, Springer Berlin / Heidelberg, Aug. 25, 2006.
Hong et al., “Nand Flash-based Disk Cache Using SLC/MLC Combined Flash Memory”, 2010 International Workshop on Storage Network Architecture and Parallel I/Os, pp. 21-30, USA, May 3, 2010.
Horstein, “On the Design of Signals for Sequential and Nonsequential Detection Systems with Feedback,” IEEE Transactions on Information Theory IT-12:4 (Oct. 1966), pp. 448-455.
How to Resolve Bad Super Block: Magic Number Wrong in BSD, Free Online Articles Director Article Base, posted Sep. 5, 2009.
Huffman, A., “Non-Volatile Memory Host Controller Interface (NVMHCI)”, Specification 1.0, Apr. 14, 2008.
Jedec Standard JESD84-C44, “Embedded MultiMediaCard (eMMC) Mechanical Standard, with Optional Reset Signal”, Jedec Solid State Technology Association, USA, Jul. 2009.
Jedec, “UFS Specification”, version 0.1, Nov. 11, 2009.
Jung et al., in “A 117 mm.sup.2 3.3V Only 128 Mb Multilevel NAND Flash Memory for Mass Storage Applications,” IEEE Journal of Solid State Circuits, (11:31), Nov. 1996, pp. 1575-1583.
Kang et al., “A Superblock-based Flash Translation Layer for NAND Flash Memory”, Proceedings of the 6th ACM & IEEE International Conference on Embedded Software, pp. 161-170, Seoul, Korea, Oct. 22-26, 2006.
Kawaguchi et al. 1995. A flash-memory based file system. In Proceedings of the USENIX 1995 Technical Conference , New Orleans, Louisiana. 155-164.
Kim et al., “Future Memory Technology including Emerging New Memories”, Proceedings of the 24th International Conference on Microelectronics (MIEL), vol. 1, pp. 377-384, Nis, Serbia and Montenegro, May 16-19, 2004.
Lee et al., “Effects of Floating Gate Interference on NAND Flash Memory Cell Operation”, IEEE Electron Device Letters, vol. 23, No. 5, pp. 264-266, May 2002.
Maayan et al., “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State circuits Conference (ISSCC 2002), pp. 100-101, San Francisco, USA, Feb. 3-7, 2002.
Mielke et al., “Recovery Effects in the Distributed Cycling of Flash Memories”, IEEE 44th Annual International Reliability Physics Symposium, pp. 29-35, San Jose, USA, Mar. 2006.
Micron Technology Inc., “Memory Management in NAND Flash Arrays”, Technical Note, year 2005.
Numonyx, “M25PE16: 16-Mbit, page-erasable serial flash memory with byte-alterability, 75 MHz SPI bus, standard pinout”, Apr. 2008.
Onfi, “Open NAND Flash Interface Specification,” revision 1.0, Dec. 28, 2006.
Panchbhai et al., “Improving Reliability of NAND Based Flash Memory Using Hybrid SLC/MLC Device”, Project Proposal for CSci 8980—Advanced Storage Systems, University of Minnesota, USA, Spring 2009.
Park et al., “Sub-Grouped Superblock Management for High-Performance Flash Storages”, IEICE Electronics Express, vol. 6, No. 6, pp. 297-303, Mar. 25, 2009.
Phison Electronics Corporation, “PS8000 Controller Specification (for SD Card)”, revision 1.2 Document No. S-07018, Mar. 28, 2007.
Shalvi, et al., “Signal Codes,” Proceedings of the 2003 IEEE Information Theory Workshop (ITW'2003), Paris, France, Mar. 31-Apr. 4, 2003.
SD Group and SD Card Association, “SD Specifications Part 1 Physical Layer Specification”, version 3.01, draft 1.00, Nov. 9, 2009.
Serial ATA International Organization, “Serial ATA Revision 3.0 Specification”, Jun. 2, 2009.
Shiozaki, A., “Adaptive Type-II Hybrid Broadcast ARQ System”, IEEE Transactions on Communications, vol. 44, Issue 4, pp. 420-422, Apr. 1996.
Suh et al., “A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE Journal of Solid-State Circuits, vol. 30, No. 11, pp. 1149-1156, Nov. 1995.
St Microelectronics, “Bad Block Management in NAND Flash Memories”, Application note AN-1819, Geneva, Switzerland, May 2004.
ST Microelectronics, “Wear Leveling in Single Level Cell NAND Flash Memories,” Application note AN-1822 Geneva, Switzerland, Feb. 2007.
Super User Forums, “SD Card Failure, can't read superblock”, posted Aug. 8, 2010.
Takeuchi et al., “A Double Level VTH Select Gate Array Architecture for Multi-Level NAND Flash Memories”, Digest of Technical Papers, 1995 Symposium on VLSI Circuits, pp. 69-70, Jun. 8-10, 1995.
Takeuchi et al., “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories”, IEEE Journal of Solid State Circuits, vol. 33, No. 8, Aug. 1998.
Ubuntu Forums, “Memory Stick Failed IO Superblock”, posted Nov. 11, 2009.
Wu et al., “eNVy: A non-Volatile, Main Memory Storage System”, Proceedings of the 6th International Conference on Architectural support for programming languages and operating systems, pp. 86-87, San Jose, USA, 1994.
International Application PCT/IL2007/000575 Patentability report dated Mar. 26, 2009.
International Application PCT/IL2007/000575 Search Report dated May 30, 2008.
International Application PCT/IL2007/000576 Patentability Report dated Mar. 19, 2009.
International Application PCT/IL2007/000576 Search Report dated Jul. 7, 2008.
International Application PCT/IL2007/000579 Patentability report dated Mar. 10, 2009.
International Application PCT/IL2007/000579 Search report dated Jul. 3, 2008.
International Application PCT/IL2007/000580 Patentability Report dated Mar. 10, 2009.
International Application PCT/IL2007/000580 Search Report dated Sep. 11, 2008.
International Application PCT/IL2007/000581 Patentability Report dated Mar. 26, 2009.
International Application PCT/IL2007/000581 Search Report dated Aug. 25, 2008.
International Application PCT/IL2007/001059 Patentability report dated Apr. 19, 2009.
International Application PCT/IL2007/001059 Search report dated Aug. 7, 2008.
International Application PCT/IL2007/001315 search report dated Aug. 7, 2008.
International Application PCT/IL2007/001315 Patentability Report dated May 5, 2009.
International Application PCT/IL2007/001316 Search report dated Jul. 22, 2008.
International Application PCT/IL2007/001316 Patentability Report dated May 5, 2009.
International Application PCT/IL2007/001488 Search report dated Jun. 20, 2008.
International Application PCT/IL2008/000329 Search report dated Nov. 25, 2008.
International Application PCT/IL2008/000519 Search report dated Nov. 20, 2008.
International Application PCT/IL2008/001188 Search Report dated Jan. 28, 2009.
International Application PCT/IL2008/001356 Search Report dated Feb. 3, 2009.
International Application PCT/IL2008/001446 Search report dated Feb. 20, 2009.
U.S. Appl. No. 11/949,135 Official Action dated Oct. 2, 2009.
U.S. Appl. No. 12/019,011 Official Action dated Nov. 20, 2009.
U.S. Appl. No. 11/957,970 Official Action dated May 20, 2010.
U.S. Appl. No. 12/171,797 Official Action dated Aug. 25, 2010.
U.S. Appl. No. 11/945,575 Official Action dated Aug. 24, 2010.
U.S. Appl. No. 12/497,707 Official Action dated Sep. 15, 2010.
U.S. Appl. No. 11/995,801 Official Action dated Oct. 15, 2010.
U.S. Appl. No. 12/045,520 Official Action dated Nov. 16, 2010.
U.S. Appl. No. 12/388,528 Official Action dated Nov. 29, 2010.
U.S. Appl. No. 11/995,814 Official Action dated Dec. 17, 2010.
U.S. Appl. No. 12/251,471 Official Action dated Jan. 3, 2011.
U.S. Appl. No. 12/171,797, filed Jul. 11, 2008.
U.S. Appl. No. 12/251,471, filed Oct. 15, 2008.
U.S. Appl. No. 12/497,707, filed Jul. 06, 2009.
U.S. Appl. No. 12/534,893, filed Aug. 4, 2009.
U.S. Appl. No. 12/534,898, filed Aug. 4, 2009.
U.S. Appl. No. 12/551,583, filed Sep 1, 2009.
U.S. Appl. No. 12/551,567, filed Sep. 1, 2009.
U.S. Appl. No. 12/558,528, filed Sep. 13, 2009.
U.S. Appl. No. 12/579,430, filed Oct. 15, 2009.
U.S. Appl. No. 12/579,432, filed Oct. 15, 2009.
U.S. Appl. No. 12/607,078, filed Oct. 28, 2009.
U.S. Appl. No. 12/607,085, filed Oct. 28, 2009.
U.S. Appl. No. 12/649,358, filed Dec. 30, 2009.
U.S. Appl. No. 12/649,360, filed Dec. 30, 2009.
U.S. Appl. No. 12/688,883, filed Jan. 17, 2010.
U.S. Appl. No. 12/728,296, filed Mar. 22, 2010.
U.S. Appl. No. 12/758,003, filed Apr. 11, 2010.
U.S. Appl. No. 12/880,101, filed Sep. 12, 2010.
U.S. Appl. No. 12/890,724, filed Sep. 27, 2010.
U.S. Appl. No. 12/822,207, filed Jun. 24, 2010.
U.S. Appl. No. 12/987,174, filed Jan. 10, 2011.
U.S. Appl. No. 12/987,175, filed Jan. 10, 2011.
U.S. Appl. No. 13/021,754, filed Feb. 6, 2011.
U.S. Appl. No. 12/534,898 Official Action dated Mar. 23, 2011.
U.S. Appl. No. 13/047,822, filed Mar. 15, 2011.
U.S. Appl. No. 13/069,406, filed Mar. 23, 2011.
U.S. Appl. No. 13/088,361, filed Apr. 17, 2011.
U.S. Appl. No. 12/323,544 Official Action dated Mar. 9, 2012.
Chinese Patent Application # 200780026181.3 Official Action dated Mar. 7, 2012.
Chinese Patent Application # 200780026094.8 Official Action dated Feb. 2, 2012.
U.S. Appl. No. 12/332,370 Official Action dated Mar. 8, 2012.
U.S. Appl. No. 12/579,432 Official Action dated Feb. 29, 2012.
U.S. Appl. No. 12/522,175 Official Action dated Mar. 27, 2012.
U.S. Appl. No. 12/607,085 Official Action dated Mar. 28, 2012.
Budilovsky et al., “Prototyping a High-Performance Low-Cost Solid-State Disk”, SYSTOR—The 4th Annual International Systems and Storage Conference, Haifa, Israel, May 30-Jun. 1, 2011.
NVM Express Protocol, “NVM Express”, Revision 1.0b, Jul. 12, 2011.
SCSI Protocol, “Information Technology—SCSI Architecture Model—5 (SAM-5)”, INCITS document T10/2104-D, revision 01, Jan. 28, 2009.
SAS Protocol, “Information Technology—Serial Attached SCSI—2 (SAS-2)”, INCITS document T10/1760-D, revision 15a, Feb. 22, 2009.
U.S. Appl. No. 12/323,544 Office Action dated Dec. 13, 2011.
U.S. Appl. No. 12/332,368 Office Action dated Nov. 10, 2011.
U.S. Appl. No. 12/063,544 Office Action dated Dec. 14, 2011.
U.S. Appl. No. 12/186,867 Office Action dated Jan. 17, 2012.
U.S. Appl. No. 12/119,069 Office Action dated Nov. 14, 2011.
U.S. Appl. No. 12/037,487 Office Action dated Jan. 3, 2012.
U.S. Appl. No. 11/995,812 Office Action dated Oct. 28, 2011.
U.S. Appl. No. 12/551,567 Office Action dated Oct. 27, 2011.
U.S. Appl. No. 12/618,732 Office Action dated Nov. 4, 2011.
U.S. Appl. No. 12/649,382 Office Action dated Jan. 6, 2012.
U.S. Appl. No. 13/284,909, filed Oct. 30, 2011.
U.S. Appl. No. 13/284,913, filed Oct. 30, 2011.
U.S. Appl. No. 13/338,335, filed Dec. 28, 2011.
U.S. Appl. No. 13/355,536, filed Jan. 22, 2012.
Kim et al., “Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding”, Proceedings of the 40th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-40), Chicago, USA, Dec. 1-5, 2007.
Wei, L., “Trellis-Coded Modulation With Multidimensional Constellations”, IEEE Transactions on Information Theory, vol. IT-33, No. 4, pp. 483-501, Jul. 1987.
U.S. Appl. No. 13/114,049 Official Action dated Sep. 12, 2011.
U.S. Appl. No. 12/405,275 Official Action dated Jul. 29, 2011.
Conway et al., “Sphere Packings, Lattices and Groups”, 3rd edition, chapter 4, pp. 94-135, Springer, New York, USA 1998.
Chinese Patent Application # 200780040493.X Official Action dated Jun. 15, 2011.
U.S. Appl. No. 12/037,487 Official Action dated Oct. 3, 2011.
U.S. Appl. No. 12/649,360 Official Action dated Aug. 9, 2011.
U.S. Appl. No. 13/192,504, filed Jul. 28, 2011.
U.S. Appl. No. 13/192,852, filed Aug. 2, 2011.
U.S. Appl. No. 13/231,963, filed Sep. 14, 2011.
U.S. Appl. No. 13/239,408, filed Sep. 22, 2011.
U.S. Appl. No. 13/239,411, filed Sep. 22, 2011.
U.S. Appl. No. 13/214,257, filed Aug. 22, 2011.
U.S. Appl. No. 13/192,501, filed Jul. 28, 2011.
U.S. Appl. No. 13/192,495, filed Jul. 28, 2011.
Provisional Applications (2)
Number Date Country
61286814 Dec 2009 US
61326858 Apr 2010 US