Patent Application
20230152977
This disclosure relates to the field of computer technologies, and in particular, to a memory management technology and a computer system.
A dynamic random-access memory (DRAM) is a semiconductor memory. A main functional principle of the DRAM is to use a quantity of electric charges stored in a capacitor to indicate whether a binary bit is 1 or 0. The DRAM is usually used as a memory (or referred to as a main storage) of a computer, and is an internal memory that directly exchange data with a central processing unit (CPU). ADRAM row management policy or a DRAM row policy is a management policy for a row buffer of the DRAM. The policy is a policy of a specific condition in which closing of a row in a memory bank of the DRAM is triggered after the row is opened. Alternatively, the DRAM row management policy is a policy of a specific condition in which closing of a row buffer of a corresponding bank is triggered after data of a row enters the row buffer of the bank.
During memory access, impact of a status of a row in a memory on the memory access may include a row hit and a row conflict. The row hit indicates that a to-be-accessed row is exactly consistent with an opened row in a to-be-accessed bank. In a case of the row hit, data can be read or written by sending only one column access command (for example, a read or write command). The row conflict indicates that a row in a to-be-accessed bank has been opened, but the currently opened row is not the same as a to-be-accessed row. In this case, the currently opened row needs to be closed first, then the to-be-accessed row needs to be opened, and then column access is performed. Usually, a latency of the row hit is about ⅓ of a latency of the row conflict. Therefore, during memory access, if a memory row is closed too early, an access latency is increased. If the memory row is closed too late, a row conflict occurs and the latency is increased. Therefore, the DRAM row management policy is one of key factors that affect a latency and bandwidth for accessing the DRAM.
This disclosure provides a memory management technology and a computer system, to reduce a memory access latency and improve memory access efficiency.
According to a first aspect, an embodiment of the present disclosure provides a memory management method. The memory management method may be applied to a computer system including a DRAM. The method may be implemented by a memory controller in the computer system. In the method, after obtaining a memory access, the memory controller may determine an access type of the memory access, and execute a row management policy corresponding to the access type of the memory access. The access type of the memory access includes a read access and a write access.
According to the memory management method provided in this embodiment of the present disclosure, a difference between localities of memory accesses of different types is fully considered, and the corresponding row management policy is executed based on the type of the memory access, so that memory row management can be more accurate, a memory access latency caused by an inappropriate row management policy can be reduced, and memory access efficiency can be improved.
With reference to the first aspect, in a possible implementation, the memory access is used for accessing a target row in a target memory bank in a memory. The executing a row management policy corresponding to an access type of the memory access includes: executing a row management policy that is of the target memory bank and that corresponds to the access type of the memory access. The memory includes one or more memory banks, and the target memory bank is any one of the one or more memory banks. In this case, different row management policies may be executed for different target memory banks, so that a management granularity is smaller and management is more precise.
In a possible implementation, the row management policy may be further adjusted based on the access type of the memory access and a row hit status of the target row. The row hit status includes at least one of the following states: a row hit, a row conflict, and row idle.
In a possible implementation, when the row management policy of the target memory bank is adjusted based on the access type of the memory access and the row hit status of the target row, and when the memory access is a read access, the memory controller may adjust a first indicator of the target memory bank based on the row hit status of the target row. The first indicator indicates a first row management policy of the target memory bank, and the first row management policy indicates whether to close the target row after the read access is performed.
In this way, the first indicator indicating the row management policy used after the read access is performed is specified, and the first indicator is adjusted based on only the read access and the row hit status of the target row, so that the adjustment is more accurate, the row management policy indicated by the first indicator is also more accurate, and a memory access latency can be reduced.
In another possible implementation, when the row management policy of the target memory bank is adjusted based on the access type of the memory access and the row hit status of the target row, and if the memory access is a write access, a second indicator of the target memory bank may be adjusted based on the row hit status of the target row. The second indicator indicates a second row management policy of the target memory bank, and the second row management policy indicates whether to close the target row after the write access is performed. In this case, the second indicator indicating the row management policy used after the write access is performed is specified, and the second indicator is adjusted based on only the write access and the row hit status of the target row. Therefore, after the read access and the write access are performed, different row management policies may be executed based on indications of different indicators, so that adjustment is more accurate, and a memory access latency can be reduced.
In another possible implementation, the adjusting the row management policy of the target memory bank based on the access type of the memory access and a row hit status of the target row may further include: if the memory access is a write access, determining that the row management policy of the target memory bank is a preset row management policy corresponding to the write access. The preset row management policy indicates whether to close the target row after the write access is performed. In this case, only the first indicator indicating the row management policy used after the read access is performed may be specified for the target memory bank, and the first indicator is adjusted based on only the read access of the target memory bank. Because a locality of the write access is poor, even if adjustment is performed, an effect is not noticeable. Therefore, the preset row management policy may be used, and no adjustment is performed during the memory access. For example, in actual application, considering that the locality of the write access is poor, the preset row management policy may indicate to close the target row after the write access is completely performed. In other words, in this case, only the row management policy used after the read access is performed may be adjusted, and the row management policy used after the write access is performed is not adjusted.
In another possible implementation, the row hit status includes a row hit or a row conflict. The adjusting a first indicator or a second indicator of the target memory bank based on the row hit status of the target row includes: if the memory access causes a row hit, adjusting the first indicator or the second indicator to a first indication; or if the memory access causes a row conflict, adjusting the first indicator or the second indicator to a second indication. The first indication indicates that the target row is not closed or the target row is kept in an open state, and the second indication indicates that the target row is closed.
In another possible implementation, the row hit status includes row idle. The adjusting a first indicator or a second indicator based on the row hit status of the target row includes: if the memory access causes row idle, determining whether the memory access may cause a row hit; and if the memory access may cause a row hit, adjusting the first indicator or the second indicator to the first indication, where the first indication indicates that the target row is not closed or the target row is kept in the open state, and that a row hit may be caused means that a row hit is caused if a last opened row in the target memory bank is not closed; or if the memory access may cause a row conflict, adjusting the first indicator or the second indicator to the second indication, where the second indication indicates that the target row is closed, and that a row conflict may be caused means that a row conflict is caused if a last opened row in the target memory bank is not closed.
In another possible implementation, the method further includes: determine an access type of previous memory access of the memory access. The adjusting a first indicator or a second indicator of the target memory bank based on the row hit status of the target row includes: adjusting the first indicator or the second indicator of the target memory bank based on the row hit status of the target row and the access type of the previous memory access of the memory access.
In another possible implementation, an initial value of the first indicator is greater than an initial value of the second indicator.
In another possible implementation, when the first indicator is adjusted, a first adjustment amplitude of adjustment to the first indication is greater than a second adjustment amplitude of adjustment to the second indication; and when the second indicator is adjusted, a third adjustment amplitude of adjustment to the first indication is less than a fourth adjustment amplitude of adjustment to the second indication.
In the foregoing several adjustment manners, a difference between localities of the read access and the write access is fully considered, and the first indicator or the second indicator of the target memory bank is adjusted based on the type of the memory access of the target memory bank, the type of the previous memory access of the current memory access, and the row hit status of the target row, so that adjustment of a value of the first indicator or a value of the second indicator of the target memory bank is more accurate. Therefore, the memory controller can more accurately determine, based on the indication of the first indicator or the second indicator of the target memory bank, when to close the row in the target memory bank. This reduces a memory access latency caused by an inappropriate row management policy, and improves memory access efficiency.
In another possible implementation, the memory access belongs to a first batch of memory accesses. When it is determined that the first batch of memory accesses are completely performed and a second batch of memory accesses are to be performed, the target row is closed if an access type of the first batch of memory accesses is different from an access type of the second batch of memory accesses; the target row is kept in the open state if both the first batch of memory accesses and the second batch of memory accesses are read accesses; or the target row is closed if both the first batch of memory accesses and the second batch of memory accesses are write accesses. In this manner of scheduling memory accesses in batches, memory accesses of a same type may be scheduled in a same batch, so that a read-write switching time is reduced, and memory access efficiency is improved.
In another possible implementation, the adjusting the row management policy of the target memory bank based on the indication of the first indicator or the second indicator may include: when the value of the first indicator or the value of the second indicator is greater than a preset threshold, keeping the target row in the open state after the read access is completely performed, and closing the target row until a time for keeping the open state reaches a time indicated by the value of the first indicator or a time indicated by the value of the second indicator.
In another possible implementation, the adjusting the row management policy of the target memory bank based on the indication of the first indicator or the second indicator may include: when the value of the first indicator or the value of the second indicator is greater than or equal to a first threshold, keeping the target row in the open state; or when the value of the first indicator or the value of the second indicator is less than the first threshold, closing the target row.
According to a second aspect, this disclosure provides a memory management apparatus. The apparatus includes at least one processor and the memory controller that is configured to implement the memory management method in the first aspect or any one of the implementations of the first aspect.
According to a third aspect, this disclosure provides a memory controller. The memory controller includes a communications interface and a logic circuit that is configured to perform the memory management method in the first aspect or any one of the implementations of the first aspect. The communications interface is configured to receive a memory access sent by a processor of a computer system.
According to a fourth aspect, this disclosure provides a computer system. The computer system includes a memory and the memory management apparatus in the second aspect.
According to a fifth aspect, this disclosure provides a memory management apparatus. The memory management apparatus includes functional modules configured to implement the memory management method in the first aspect or any one of the implementations of the first aspect.
According to a sixth aspect, this disclosure further provides a computer program product. The computer program product includes program code. Instructions included in the program code are executed by a computer, to implement the memory management method in the first aspect or any one of the implementations of the first aspect.
According to a seventh aspect, this disclosure further provides a computer-readable storage medium. The computer-readable storage medium is configured to store program code. Instructions included in the program code are executed by a computer, to implement the memory management method in the first aspect or any one of the implementations of the first aspect.
To describe technical solutions in embodiments of the present disclosure more clearly, the following briefly describes the accompanying drawings for describing the embodiments. It is clear that the accompanying drawings in the following description show merely some embodiments of the present disclosure.
To make a person skilled in the art better understand the technical solutions in the present disclosure, the following clearly describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. It is clear that the described embodiments are merely a part but not all of the embodiments of the present disclosure.
A DRAM is a semiconductor memory. A main functional principle of the DRAM is to use a quantity of electric charges stored in a capacitor to indicate whether a binary bit is 1 or 0. The DRAM is usually used as a memory (or referred to as a main storage) of a computer system, and is an internal memory that directly exchange data with a CPU.
The processor 102 is a computing core and a control core of the computer system 100. The processor 102 may include one or more processor cores 104. The processor 102 may be a hyperscale integrated circuit. An operating system and another software program are installed in the processor 102, so that the processor 102 can access the memory 108, a cache, and a magnetic disk. It may be understood that, in this embodiment of the present disclosure, the core 104 in the processor 102 may be, for example, a CPU, or may be another application-specific integrated circuit (ASIC). In actual application, the computer system 100 may alternatively include a plurality of processors.
The memory controller 106 is a bus circuit controller that controls the memory 108 in the computer system 100 and that is configured to manage and plan data transmission from the memory 108 to the core 104. Data may be exchanged between the memory 108 and the core 104 through the memory controller 106. The memory controller 106 may be a separate chip, and is connected to the core 104 through a system bus. A person skilled in the art may learn that the memory controller 106 may be integrated into the processor 102 (as shown in
The memory 108 is a main storage of the computer system 100. The memory 108 is connected to the memory controller 106 through a double data rate (DDR) bus. The memory 108 is usually configured to store various types of software that are running in an operating system, input and output data, information exchanged with the external storage device, and the like. To increase an access speed of the processor 102, the memory 108 needs to have an advantage of a high access speed. In a computer system architecture, a DRAM is usually used as the memory 108. The processor 102 can access the memory 108 at a high speed by using the memory controller 106, and perform a read operation and a write operation on any memory cell in the memory 108.
In actual application, the memory 108 may include one or more dual in-line memory modules (DIMM) 110.
A person skilled in the art may learn that data is stored in the memory 108. The data is stored in a memory cell in the memory chip 114. In embodiments of the present disclosure, the memory cell refers to a minimum memory cell used for storing data. Usually, one memory cell may store 1-bit data. Certainly, some memory cells can also implement multi-valued storage. When the DRAM is used as the memory 108, memory cells in the DRAM (which may also be referred to as DRAM cells) are arranged into a matrix, and the matrix is referred to as a memory bank or a DRAM bank. In this manner, memory cells in a memory chip 114 may be logically classified into a plurality of memory banks, and each memory bank may be considered as a memory array including a plurality of memory cells. Each memory cell in the memory bank is identified by using a row address and a column address in which the memory cell is located. The memory controller can locate any memory cell in the memory bank by using a corresponding row decoder and a corresponding column decoder. In embodiments of the present disclosure, the memory bank may also be referred to as a bank for short.
During memory access, after receiving a memory access request, the memory controller 106 generates an address signal and a control signal based on the received memory access request, and sends the generated address signal and control signal to the DIMM 110, to access the memory. The address signal may include a row address signal and a column address signal. The control signal may include a chip select (CS) signal, a write enable (WE) signal, a column address strobe (CAS), a row address strobe (RAS), and the like. These signals may be received by the control and refresh circuit 1140. The row address signal is buffered in the row address buffer 1143. The column address signal is buffered in the column address buffer 1144. The control signal is transferred to a bank corresponding to a row address specified by the address signal.
The row address buffer 1143 is configured to buffer the row address signal sent by the memory controller 106. The column address buffer 1144 is configured to buffer the column address signal sent by the memory controller 106. The row decoder 1145 is connected to the row address buffer 1143 and the plurality of banks 1142, and the column decoder 1146 is connected to the column address buffer 1144 and the plurality of banks 1142. The row decoder 1145 is configured to decode the row address signal, and the column decoder 1146 is configured to decode the column address signal, so that a corresponding memory cell in the bank 1142 can be located based on a decoded row address signal and a decoded column address signal.
When the memory controller accesses the DRAM, the memory controller 106 needs to first identify a memory row corresponding to to-be-accessed data and determine a bank to which the to-be-accessed memory row belongs, and then the memory controller 106 “opens” the bank and the memory row. In some implementations, the memory row may also be referred to as a “page”, and the “page” is a logical concept. In this case, one page includes a memory cell of one memory row in the DRAM. Usually, a size of a memory page may include data of 512, 1024 (1K), 2048 (2K), 4098 (4K), 8196 (8K), 16392 (16K), or 32,768 (32K) bits.
Usually, during memory access, the to-be-accessed memory row may be in one of the following three states: a row hit, row idle, or a row conflict. The row hit indicates that the to-be-accessed memory row has been opened. To be specific, data in the to-be-accessed memory row has been loaded into a row buffer corresponding to a bank storing the data in the row, and data can be read from a memory cell of the row or written into a memory cell of the row by directly sending a column access command. The column access command may include a read command or a write command. The row idle indicates that a bank corresponding to the to-be-accessed memory row is in an idle state, no memory row is opened, and the to-be-accessed memory row needs to be opened by using an “activate” command, and then is accessed. In other words, data in the to-be-accessed memory row needs to be loaded into a row buffer corresponding to the bank by using an “activate” command, and then a column access command can be sent for access. The row conflict indicates that a currently opened memory row is different from the to-be-accessed memory row. In a case of the row conflict, the currently opened memory row needs to be “closed” first. This includes: writing data in the opened memory row back into a memory array by using a “pre-charge” command, then loading data in the to-be-accessed row into a corresponding row buffer by using an activate command, and then sending a column access command for access. In embodiments of the present disclosure, the foregoing three states of the to-be-accessed memory row may be referred to as row hit statues of the memory row. The “memory row” may also be referred to as a “row” for short, and the to-be-accessed memory row may also be referred to as a target row.
It can be learned from the foregoing description that, during memory access, different states of the to-be-accessed row may cause different access latencies.
It can be learned from
A memory row management policy may also be referred to as a DRAM row management policy (DRAM row closing policy) or a DRAM row policy, and is a policy used for managing a row buffer of the DRAM. The policy is a policy of a specific condition in which closing of a row in a bank of the DRAM is triggered after the row is opened. Alternatively, the DRAM row management policy is a policy of a specific condition in which closing of a row buffer of a corresponding bank is triggered after data of a row enters the buffer (Row Buffer) of the bank. Therefore, the DRAM row management policy affects a latency and bandwidth for accessing the DRAM.
Embodiments of the present disclosure provide a memory management technology, so that a row management policy of each bank in a DRAM can be dynamically adjusted, to reduce a memory access latency and improve memory access efficiency. For ease of description, in embodiments of the present disclosure, the memory row management policy may also be referred to as a row management policy. The memory management technology provided in embodiments of the present disclosure may be applied to the computer system shown in
Step 401: Obtain a memory access of a target memory bank. In this embodiment of the present disclosure, a memory 110 includes one or more memory banks, and the target memory bank may be any bank in any memory chip 114 in the memory 110. The memory access may be used for accessing a target row in the target memory bank. It may be understood that the obtained memory access may include information such as a read/write identifier, an address, and a request ID. In addition, if the memory access is a write access, the write access may further carry data to be written into the memory. The read/write identifier indicates an access type of the memory access. The address indicates a to-be-accessed address, and an identifier of a to-be-accessed bank of the memory access may be obtained based on the address. The request ID is used for identifying the memory access.
Step 403: The memory controller determines the access type of the memory access. The memory access includes a read access or a write access. In this step, the access type of the memory access may be determined based on the read/write identifier in the memory access.
Step 405: Execute a row management policy corresponding to the access type of the memory access. In this embodiment of the present disclosure, considering a difference between locality characteristics of the read access and the write access, a locality of the read access is usually better than a locality of the write access. Therefore, in this embodiment of the present disclosure, different row management policies are used for the read access and the write access. It should be noted that a good locality means that a plurality of consecutive commands are used for repeatedly accessing a same row. A poor locality means that a plurality of consecutive commands are not used for repeatedly accessing a same row. The poor locality may also be referred to as high randomness. In this step, the row management policy corresponding to the access type of the memory access may be executed. In actual application, management may alternatively be performed at a granularity of a memory bank. In this case, different row management policies may be set for different types of access of each memory bank. Therefore, in this step, a row management policy that is of the target memory bank and that corresponds to the access type of the memory access may be executed.
When the memory access is a read access, the row management policy of the target memory bank may be executed based on an indication of a specified first indicator. When the memory access is a write access, the row management policy of the target memory bank may be executed based on an indication of a specified second indicator. The first indicator indicates a row management policy used after the read access is performed, and the second indicator indicates a row management policy used after the write access is performed. In other words, the first indicator indicates whether to close the target row after the read access is performed, and the second indicator indicates whether to close the target row after the write access is performed. It should be noted that, in this embodiment of the present disclosure, the first indicator is adjusted based on only the read access, and the second indicator is adjusted based on only the write access.
When the row management policy of the target memory bank is executed based on the indication of the first indicator or the indication of the second indicator, the following several implementations may be included. In one case, the target row may be closed or kept in an open state based on the indication of the first indicator or the indication of the second indicator. For example, if a value of the first indicator or a value of the second indicator is “1”, it indicates to open the target row; or if a value of the first indicator or a value of the second indicator is “0”, it indicates to close the target row.
In another case, whether to close the target row may be determined based on the value of the first indicator or the value of the second indicator and a preset threshold. For example, when the value of the first indicator is greater than or equal to a first threshold, the target row is kept in the open state after the read access is completely performed; or when the value of the first indicator is less than a first threshold, the target row is closed after the read access is completely performed. When the value of the second indicator is greater than or equal to a second threshold, the target row is kept in the open state after the write access is completely performed; or when the value of the second indicator is less than a second threshold, the target row is closed after the write access is completely performed. In actual application, the first threshold and the second threshold may be the same or may be different. In actual application, alternatively, when the value of the first indicator is less than the first threshold, the target row may be kept in the open state after the read access is completely performed; or when the value of the first indicator is greater than the first threshold, the target row may be closed after the read access is completely performed. Similarly, when the value of the second indicator is less than the second threshold, the target row is kept in the open state after the write access is completely performed; or when the value of the second indicator is greater than the second threshold, the target row is closed after the write access is completely performed.
In still another case, the row management policy of the target row may alternatively be executed based on a time indicated by the value of the first indicator or the value of the second indicator. For example, if the memory access is a read access and the value of the first indicator is greater than or equal to a third threshold, the target row is kept in the open state after the read access is completely performed, and the target row is closed until a time for keeping the open state reaches a time indicated by the value of the first indicator. If the memory access is a write access and the value of the second indicator is greater than or equal to a fourth threshold, the target row may be kept in the open state after the write access is completely performed, and the target row is closed until a time for keeping the open state reaches a time indicated by the value of the second indicator. The third threshold and the fourth threshold may be the same or may be different, and both the third threshold and the fourth threshold may be integers greater than or equal to 0.
In yet another case, the method may further include step 407: The memory controller may adjust the corresponding row management policy based on the access type of the memory access and a row hit status of the target row. The row hit status of the target row may include a row hit, a row conflict, or row idle. The memory controller may determine the row hit status of the target row based on the address of the memory access. When the address of the memory access is consistent with an address of an opened row in the target bank, it is considered that the memory access causes a row hit. When it is determined, based on the address of the memory access, that there is no opened row in the target bank, it is considered that the memory access causes row idle. When the address of the memory access is inconsistent with an address of an opened row in the target bank, it is considered that the memory access causes a row conflict.
In actual application, the row management policy of the target bank may be adjusted by adjusting a policy indicator corresponding to the row management policy. In this embodiment of the present disclosure, considering a difference between localities of the read access and the write access, corresponding policy indicators may be adjusted based on different access types, to adjust a corresponding row management policy. For example, in one case, the policy indicator that may be specified for the target bank may include the first indicator and the second indicator. The first indicator indicates whether to close the target row after the read access is performed, and the second indicator indicates whether to close the target row after the write access is performed. In other words, the first indicator indicates a row management policy corresponding to the read access, and the second indicator indicates a row management policy corresponding to the write access. When it is determined that the memory access is a read access in step 403, the first indicator of the target memory bank may be adjusted based on the row hit status of the target row in this step. When it is determined that the memory access is a write access in step 403, the second indicator of the target memory bank may be adjusted based on the row hit status of the target row in this step. During specific adjustment, for example, if the memory access causes a row hit, the first indicator or the second indicator is adjusted to a first indication, where the first indication indicates that the target row is not closed or the target row is kept in the open state. If the memory access causes a row conflict, the first indicator or the second indicator is adjusted to a second indication, where the second indication indicates that the target row is closed. For a specific adjustment method, refer to the following descriptions in
It should be noted that, in actual application, a sequence of performing step 405 and step 407 is not limited. The row management policy of the target bank may be adjusted based on the hit status of the target row first, and then an adjusted row management policy corresponding to the type of the memory access is executed. Alternatively, the row management policy corresponding to the type of the memory access may be executed first, and then the row management policy is adjusted based on the row hit status of the target row to be accessed during the memory access.
In this embodiment of the present disclosure, when the row management policy of the memory row in the DRAM is executed, a difference between localities of different access types is fully considered, and the corresponding row management policy is executed based on the access type, so that memory row management can be more accurate, a memory access latency caused by an inappropriate row management policy can be reduced, and memory access efficiency can be improved.
As shown in
Step 402: Monitor a plurality of memory accesses of a target memory bank. The plurality of memory accesses may include read accesses or write accesses. In this embodiment of the present disclosure, the monitoring a plurality of memory accesses of a target bank includes: obtaining the plurality of memory accesses of the target bank, and determining an access type and a row hit status of each memory access of the target bank, where the row hit status includes whether a row hit, row idle, or a row conflict is caused. The access type of the memory access may be determined based on a read/write identifier in the memory access. A status of a to-be-accessed row may be determined based on an address of each memory access. When an address of a memory access is consistent with an address of an opened row in the target bank, it is considered that the memory access causes a row hit. When it is determined, based on an address of a memory access, that there is no opened row in the target bank, it is considered that the memory access causes row idle. When an address of a memory access is inconsistent with an address of an opened row in the target bank, it is considered that the memory access causes a row conflict.
Step 404: Separately adjust a row management policy of the target bank based on the plurality of memory accesses. For example, a first indicator may be adjusted based on the read access in the plurality of memory accesses, and a second indicator may be adjusted based on the write access in the plurality of memory accesses. The first indicator indicates a row management policy used after the read access is performed, and the second indicator indicates a row management policy used after the write access is performed. In this embodiment of the present disclosure, considering a difference between locality characteristics of the read access and the write access, a second indicator and a first indicator of a same bank are separately specified. For ease of description, a bank in a memory chip 114 is used as an example for description in this embodiment of the present disclosure.
In this embodiment of the present disclosure, the second indicator and the first indicator each may exist in a form of a counter or a register. The following describes the second indicator by using a counter as an example. During initialization, different initial values may be assigned to the first indicator and the second indicator. Considering that a locality of the read access is better than a locality of the write access, an initial value of the first indicator may be greater than an initial value of the second indicator.
After the initialization is completed, the value of the first indicator may be adjusted based on the read access to the bank, and the value of the second indicator may be adjusted based on the write access to the bank. It should be noted that, in this embodiment of the present disclosure, for any bank, a first indicator of the bank is adjusted based on only a read access to the bank, and a second indicator of the bank is adjusted based on only a write access to the bank. For details about how to adjust the value of the first indicator or the value of the second indicator of the target bank based on the memory access of the target bank, refer to embodiments shown in
Step 406: Execute the row management policy of the target bank. For details about how to execute the row management policy of the target bank based on an indication of the first indicator or an indication of the second indicator, refer to the description of step 405 in
Step 502: A memory controller receives a memory access. As described above, the received memory access may include information such as a read/write identifier, an address, and a request ID. Step 504: The memory controller determines whether the memory access is a read access or a write access. If the memory access is a read access, the method proceeds to step 506. If the memory access is a write access, the method proceeds to step 520. It may be understood that step 502 and step 504 are similar to step 401 and step 403 in
When the memory access is a read access, in step 506, it is further determined whether a previous memory access of the target memory bank (memory bank or bank for short) is a read access or a write access. If the previous memory access is a read access, the method proceeds to step 508. If the previous memory access of the memory access is a write access, to reduce inappropriate closing of a row in the target bank due to read-write switching caused by a random operation, the method proceeds to step 519. Step 508: The memory controller determines whether the target bank is in an open state or an idle state. If the target bank is in the open state, the method proceeds to step 510. If the target bank is in the idle state, the method proceeds to step 516.
When the target bank is opened, in step 510, the memory controller determines whether the memory access causes a row hit. The memory controller may determine, based on a row address of the memory access, whether an opened row in the target bank is hit. If the row address of the memory access is the same as an address of the opened row in the target bank, it is considered that the memory access causes a row hit. Otherwise, it is considered that the memory access causes a row conflict. If the memory access causes a row hit, it indicates that a decision to keep the row in the open state is correct, and the method proceeds to step 514. Step 514: The memory controller may adjust the first indicator to a first indication, where the first indication indicates that a target row is not closed or a target row is kept in the open state. For example, the memory controller may increase a value of the first indicator by a first preset value or not adjust the first indicator of the target bank, to keep the target row in the open state. The first preset value may be 1 or another value.
If the memory access causes a row conflict, it indicates that the currently opened row in the target bank should be closed as early as possible, and the method proceeds to step 512. Step 512: The memory controller adjusts the first indicator of the target bank to a second indication, where the second indication indicates that the target row is closed. For example, in step 512, the memory controller may decrease a value of the first indicator of the target bank by a second preset value. For example, the second preset value may be 1 or another value. The first preset value may also be referred to as a first adjustment amplitude, and the second preset value may also be referred to as a second adjustment amplitude.
If the target bank is idle, in step 516, the memory controller further determines whether the memory access may cause a row hit. That a row hit may be caused means that a row hit is caused if a last opened row in the target bank is not closed. As described above, when the target bank is idle, it indicates that no row in the target bank is in the open state. The idle state of the target bank may be caused because the row in the target bank is closed after the previous memory access of the target bank is completely performed. In this step, the memory controller may compare the row address of the memory access with a row address of the previous memory access, to determine whether the memory access may cause a row hit.
If the row address of the memory access is the same as the row address of the previous memory access, it is determined that the memory access may cause a row hit. In this case, it indicates that the last opened row in the target bank should be opened for a longer period of time, but is closed in advance. Therefore, the method proceeds to step 518. Step 518: The memory controller adjusts the first indicator of the target bank to the first indication, for example, increases the value of the first indicator by the first preset value. For example, the first preset value may be 1 or another value. If it is determined that the memory access may not cause a row hit, that is, the memory access may cause a row conflict, it indicates that a policy of closing the last opened row in the target bank is correct, and the method proceeds to step 519. Step 519: The memory controller does not adjust the first indicator of the target bank. The last opened row in the target bank may also be referred to as a row accessed by using the previous memory access of the memory access.
The method goes back to step 504. If it is determined in step 504 that the memory access is a write access, in step 520, the memory controller further determines whether the previous memory access of the memory access is a read access or a write access. If the previous memory access of the memory access is a read access, the method proceeds to step 531: The memory controller does not adjust a write counter of the target bank. If the previous memory access of the memory access is a write access, the method proceeds to step 522. Step 522: The memory controller determines whether the target bank is in an open state or an idle state. If the target bank is in the open state, the method proceeds to step 524. If the target bank is in the idle state, the method proceeds to step 526. It should be noted that, in embodiments of the present disclosure, that the target bank is in the open state means that a row in the target bank is opened.
When the target bank is in the open state, in step 524, the memory controller further determines whether the memory access causes a row hit. The memory controller may determine, based on the row address of the memory access, whether a row hit is caused. If the memory access causes a row hit, it indicates that a policy of keeping the current row in the target bank in the open state is correct, and the method proceeds to step 530. Step 530: The memory controller may adjust the second indicator to a first indication, where the first indication indicates that the target row is not closed or the target row is kept in the open state. For example, as shown in
When the target bank is idle, in step 526, the memory controller further determines whether the memory access may cause a row hit. As described above, that a row hit may be caused means that a row hit is caused if a last opened row in the target bank is not closed. In this step, the memory controller may compare the row address of the memory access with a row address of the last opened row, to determine whether the memory access may cause a row hit. If the row address of the memory access is the same as the row address of the last opened row, it is determined that a row hit may be caused. Otherwise, it is considered that a row conflict may be caused. If it is determined that the memory access may cause a row hit, it indicates that the last opened row in the target bank is closed in advance, and should be opened for a longer period of time. It may be understood that the last opened row in the target bank is a row accessed by using the previous memory access of the memory access. In this case, the method proceeds to step 532. Step 532: The memory controller adjusts the second indicator corresponding to the target bank to the first indication. For example, the memory controller may increase the value of the second indicator of the target bank by the fourth preset value. The fourth preset value may be 1 or another value. If it is determined that the memory access may cause a row conflict, it indicates that a policy of closing of the last opened row in the target bank is correct, and the method proceeds to step 531. Step 531: The memory controller does not adjust the second indicator of the target bank.
It should be noted that the first preset value, the second preset value, the third preset value, and the fourth preset value in this embodiment of the present disclosure may be the same or may be different. This is not limited herein. When the first preset value, the second preset value, the third preset value, and the fourth preset value are different, considering a difference between localities of the read access and the write access, continuity of the read access is better, to further reduce a latency, a row accessed by using the read access may be kept open for a longer time. Randomness of the write access is higher, to reduce a latency, a row accessed by using the write access needs to be kept open for a shorter time, so as to avoid more row conflicts. Therefore, in this embodiment of the present disclosure, the first preset value may be greater than the second preset value, and the third preset value may be less than the fourth preset value. In other words, when the first indicator is adjusted, the first adjustment amplitude of adjustment to the first indication may be greater than the second adjustment amplitude of adjustment to the second indication. When the second indicator is adjusted, the third adjustment amplitude of adjustment to the first indication may be less than the fourth adjustment amplitude of adjustment to the second indication.
In the embodiment shown in
It may be understood that, in another case, when the row management policy is adjusted based on an access type of the memory access and a row hit status, because no row is opened in a row idle state, it may be considered that impact of the row idle state on the access latency is small. Therefore, in this implementation, the impact of the row idle state on the access latency may not be considered, and the row management policy is adjusted based on only two cases: the row hit and the row conflict. In this way, the adjustment method is simpler. In other words, in this case, it may be considered that the row hit status of the memory access includes only two types: the row hit and the row conflict, and a row idle case is not considered. As shown in
In another case, when a policy counter is adjusted, a type of a previous memory access request may alternatively not be considered. In the adjustment method shown in
In another adjustment method, neither a type of a previous memory access request nor whether a target bank is idle may be considered, but a first indicator or a second indicator is adjusted based on only a type of a received memory access and a hit status (including a row hit and a row conflict) of the memory access. For example, in the adjustment method shown in
It can be learned based on the foregoing description that, in actual application, steps 506, 508, and 516 in
With reference to
Step 602: The memory controller monitors a memory access command sent to a target bank. After the memory controller receives a memory access request, the memory controller accesses a target bank 1142 in a memory 114 based on an address of the memory access request. The memory controller may send the memory access command to the target bank based on a status of a row in the target bank. For example, when the target bank is in a row idle state, the memory controller sends an activate command, to activate a row to be accessed by using the memory access. In a case of a row hit, the memory controller may directly send a read command or a write command based on the received memory access. In a case of a row conflict, the memory controller sends a pre-charge command to the target bank to close an opened row in the target bank, then sends an activate command to open a to-be-accessed row, and finally sends a read command or a write command for access. It can be learned that the commands sent by the memory controller to the target bank may include at least several types: the activate command, the pre-charge command, the read command, or the write command.
Step 604: The memory controller determines whether the memory access command is a read command or a write command. As described above, the commands sent by the memory controller to the target bank may include at least several types: the activate command, the pre-charge command, the read command, or the write command. Therefore, in step 604, if the memory controller determines that the command is a read command or a write command, the method proceeds to step 606. If the command is not a read command or a write command, the method proceeds to step 620.
Step 606: The memory controller determines whether a memory access request to which the memory access command belongs is a last memory access request for accessing the target bank in a scheduling queue. As described above, the read command or the write command sent by the memory controller to the target bank is obtained based on the currently processed memory access request. In actual application, the memory controller places a plurality of received memory access requests in a buffer queue, schedules a memory access request in the buffer queue to the scheduling queue according to a specific scheduling policy, and then separately processes the memory access request in the scheduling queue. Usually, space of the buffer queue is larger than space of the scheduling queue, and there are more memory access requests buffered in the buffer queue than memory access requests in the scheduling queue.
In this step, the memory controller may determine, based on addresses of a plurality of memory access requests in the scheduling queue, whether the memory access request (that is, the currently processed access request) to which the memory access command belongs is the last memory access request for accessing the target bank in the scheduling queue. In other words, the memory controller may determine, based on an address of each memory access request, whether there is another memory access request for accessing the target bank in the scheduling queue. If the memory access request to which the command belongs (that is, the currently processed access request) is the last memory access request for accessing the target bank in the scheduling queue, in other words, there is no other memory access request for accessing the target bank in the scheduling queue, the method proceeds to step 608. If the memory access request to which the command belongs (that is, the currently processed memory access request) is not the last memory access request for accessing the target bank in the scheduling queue, in other words, there is another memory access request for accessing the target bank in the scheduling queue, the method proceeds to step 620.
Step 608: The memory controller further determines whether the memory access command is a read command or a write command. If the command is a read command, the method proceeds to step 610. If the memory access command is a write command, the method proceeds to step 612. Step 610: The memory controller reads the value of the first indicator of the target bank, and the method proceeds to step 614. Step 612: The memory controller reads the value of the second indicator of the target bank, and then the method proceeds to step 614. It may be understood that the value of the first indicator and the value of the second indicator of the target bank may be values obtained after adjustment based on the methods shown in
Step 614: The memory controller determines whether the value of the indicator read in step 610 or step 612 is less than a specified threshold. If the read value of the first indicator or the read value of the second indicator is not less than the threshold, the method proceeds to step 616. If the read value of the first indicator or the read value of the second indicator is less than the threshold, the method proceeds to step 620. In actual application, the threshold may be set to 0 or another value. This is not limited herein.
Step 616: The memory controller controls a timer corresponding to the target bank to start timing based on the read value of the first indicator or the read value of the second indicator, and then the method proceeds to step 618. Step 618: The memory controller closes the opened row in the target bank when the timer reaches a timing time. The memory controller may send a pre-charge command to the target bank, to close the opened row in the target bank. It may be understood that, the timer may start timing based on the value of the first indicator or the value of the second indicator in an incremental or decremental manner. For example, the timer may start timing from 0 until the time of the timer increases to the value of the first indicator or the value of the second indicator; or the timer may start timing in a decremental manner after the time of the timer is set to the value of the first indicator or the value of the second indicator. A timing manner is not limited herein.
The method for executing a row management policy shown in
The foregoing embodiment provides an adjustment manner for a case in which the first indicator and the second indicator are separately specified for each bank. In actual application, because a locality of a write access is poor, a fixed page policy may be used for the write access. For example, in one manner, a fixed row closing policy may be used, that is, a row accessed by using the write access is closed immediately after the write access is completely performed. In another case, a short row closing time may be set, and the row accessed by using the write access is closed when the time is reached. When the fixed row management policy is used for the write access, the second indicator may not be set. In this manner, only one first indicator may be specified for each bank.
Step 702: Obtain a memory access of a target memory bank. Similar to step 401, the memory access may include a read access or a write access. The obtained memory access may include information such as a read/write identifier, an address, and a request ID. In addition, if the memory access is a write access, the write access may further carry data to be written into a memory. Step 704: The memory controller may determine an access type of the memory access. The memory access includes a read access or a write access. In this step, the access type of the memory access may be determined based on the read/write identifier in the memory access. If the memory access is a read access, the method proceeds to step 706. If the memory access is a write access, the method proceeds to step 710.
Step 706: The memory controller adjusts a first indicator of the target bank based on a row hit status of a target row of the memory access. As described above, the row hit status may include a row hit, a row conflict, or row idle. In this embodiment of the present disclosure, the first indicator may be set to indicate a row management policy used after the read access is performed. In other words, whether to close the target row after the read access is performed may be determined based on an indication of the first indicator. In this step, the first indicator of the target bank may be adjusted based on the row hit status of the memory access, so that the row management policy of the target bank can be dynamically adjusted. For a specific adjustment method, refer to adjustment methods for the first indicator in
Step 708: The memory controller executes the corresponding row management policy based on the indication of the first indicator. After the memory access is completely performed, the corresponding row management policy may be executed based on the indication of the first indicator. For example, the target row may be closed or kept in an open state based on the indication of the first indicator after the read access is performed, or the target row may be closed based on a time indicated by the first indicator. For this step, refer to the description of step 405. Details are not described herein again. It may be understood that, for execution of the corresponding row management policy based on the first indicator, refer to the description of how to execute the corresponding row management policy based on the indication of the first indicator in
Step 710: The memory controller executes a preset row management policy. In this embodiment of the present disclosure, considering that randomness of processing a write access by the memory controller is high, a fixed row management policy may be used. For example, a row accessed by using a write access may be closed after the write access is performed. In this step, the preset row management policy may not be adjusted when the write access is received, but when to close the target row is determined according to the preset row management policy after the write access is completely performed.
In the embodiment shown in
A person skilled in the art learns that, because switching between different memory accesses of the target bank causes an access latency, in the method provided in this embodiment of the present disclosure, the memory controller may continually schedule, in a scheduling queue, a plurality of memory accesses for accessing a same bank. In addition, considering that switching between a plurality of consecutive read accesses and write accesses of a same row in a same bank also causes a latency, and there are different requirements for row management policies due to a difference between localities of the read access and the write access, in the following embodiment, the read accesses and the write accesses are further scheduled in batches.
In this scheduling mode, a row management policy of a bank may be further adjusted when different batches of accesses are performed, to reduce an access latency and reduce a waste of bus bandwidth caused by switching between different types of accesses. For a method for adjusting a row management policy during switching between different batches of accesses, refer to
Step 902: A memory controller performs an ith batch of accesses. An initial value of i may be set to 1, and i is a natural number greater than or equal to 1. As described above, after receiving memory access requests, the memory controller places a plurality of received memory access requests in a buffer queue, and then schedules a memory access request in the buffer queue to a scheduling queue for separate execution. In this embodiment of the present disclosure, the memory controller may schedule the plurality of memory access requests to the scheduling queue in batches based on types of the memory access requests. For example, the memory controller may schedule the plurality of memory access requests to the scheduling queue in the manner of scheduling in batches shown in
Step 904: The memory controller determines whether the ith batch of accesses are completely performed. The memory controller may determine whether a performed access is a last access of the ith batch, to determine whether the ith batch of accesses are completely performed. Alternatively, the memory controller may determine, based on whether there is another access in the scheduling queue, whether the ith batch of accesses are completely performed. In addition, the memory controller may alternatively determine, in a counting manner, whether the ith batch of accesses are completely performed. A method for the memory controller to determine whether the ith batch of accesses are completely performed is not limited herein. If the ith batch of accesses are not completely performed, the method goes back to step 902, and the ith batch of accesses are continued to be performed. If the memory controller determines that the ith batch of accesses are completely performed, the method proceeds to step 904, and the memory controller further determines whether to perform an (i+1)th batch of accesses. The memory controller may determine, based on whether there is another access in the scheduling queue or the buffer queue, whether the (i+1)th batch of accesses need to be performed. If the (i+1)th batch of accesses need to be performed, the method proceeds to step 908. If it is determined that the (i+1)th batch of accesses do not need to be performed, it indicates that no other memory access needs to be performed, and the method proceeds to step 914.
Step 908: The memory controller determines whether the ith batch of accesses and the (i+1)th batch of accesses are memory accesses of a same type. In the embodiment shown in
Step 910: The memory controller further determines whether both the ith batch of accesses and the (i+1)th batch of accesses are read accesses. If both the ith batch of accesses and the (i+1)th batch of accesses are read accesses, the method proceeds to step 912. If the ith batch of accesses or the (i+1)th batch of accesses are write accesses, the method proceeds to step 914. Step 912: The memory controller keeps a currently opened row in an open state. In this embodiment of the present disclosure, because both the ith batch of accesses and the (i+1)th batch of accesses are read accesses, considering that the memory controller has a good locality in processing read accesses, in other words, there is a high probability that a plurality of commands for continually accessing a same row, if a row opened in a process of performing a previous batch of read accesses remains in the open state during switching, the row may be kept in the open state. For example, during switching between the first batch of accesses 802 and the second batch of accesses 804, if a row opened in a process of performing the first batch of accesses 802 remains in the open state, the row may be kept in the open state. Then, the method proceeds to step 916.
If it is determined in step 908 that the ith batch of accesses and the (i+1)th batch of accesses are memory accesses of different types, for example, the ith batch of accesses are write accesses, or the (i+1)th batch of accesses are write accesses. In this case, the memory controller needs to switch between the read access and the write access. In this embodiment of the present disclosure, considering a difference between localities of the read access and the write access, randomness of the write access is higher. To reduce a latency, during switching, the method may proceed to step 914, to close all rows opened in a process of performing the ith batch of accesses. For example, as shown in
If it is determined in step 910 that both the ith batch of accesses and the (i+1)th batch of accesses are write accesses, because the write access has high randomness and a poor locality, in this case, the method may alternatively proceed to step 914 to close all rows opened in a process of performing the ith batch of accesses. Then, the method proceeds to step 916 to switch to perform the (i+1)th batch of accesses. Step 916: Make i=i+1. The method goes back to step 902 to perform the next batch of memory accesses. This process is repeated until the plurality of batches of accesses that need to be performed are completely performed. It may be understood that a value of i cannot be greater than a total quantity of batches of to-be-performed accesses.
According to the memory management method provided in
It should be noted that, in actual application, an independent policy counter is not necessarily specified for each bank in some designs. Alternatively, a plurality of address segments may be obtained through division, and a policy counter is specified for each address segment. Alternatively, several banks may share a same group of policy counters. Each address segment may include addresses of a plurality of banks, or may include a part of addresses in one bank. In a design in which several banks share a group of policy counters, when a row management policy is adjusted, reference may be made to the foregoing embodiment to perform an operation on a policy counter corresponding to a bank to be accessed by using a memory access. According to these manners, in actual application, a same row management policy may be used for a plurality of banks, or a same row management policy may be used for a plurality of target row accesses corresponding to at least one address segment.
According to the memory management method provided in this embodiment of the present disclosure, a difference between localities of a read access and a write access in memory accesses is considered in a process of executing a memory row management policy, so that memory row management better complies with a characteristic of the memory access, a memory access latency is reduced, a waste of bandwidth is reduced, and memory access efficiency is improved.
In addition, a case in which data is written into a memory in a direct memory access (DMA) manner exists in actual application. An embodiment of the present disclosure further provides how to manage a memory row in a DMA read/write scenario. DMA read/write is usually read/write of a large data block, and a DMA is usually unidirectionally performed once. To ensure data consistency, a data block that is being accessed by using the DMA is usually not accessed by another source. DMA read and write operations have a good locality and are irrelevant to another request. Therefore, a memory access policy in a DMA scenario may be considered separately. For example, in actual application, a DMA memory access and a non-DMA memory access may be scheduled in batches. In addition, DMA memory accesses may be further classified into a DMA read access and a DMA write access for scheduling in batches.
For switching between non-DMA accesses, refer to the foregoing embodiment. For switching between a non-DMA access and a DMA access, after a current batch of memory accesses are completely performed, a row in a bank involved in the batch of memory accesses may be directly closed. For switching between DMA accesses, if switching is performed between different batches of memory accesses that belong to a same DMA operation, no matter whether types of two adjacent batches of DMA accesses are the same, a row in a bank involved in a currently completed DMA access may be kept in an open state during switching. If two adjacent batches of DMA accesses are not DMA accesses caused by a same DMA operation, no matter whether types of the two adjacent batches of DMA accesses are the same or whether an involved DMA access is a read access or a write access, a row in a bank involved in a currently completed DMA access may be closed during switching.
According to the memory management method provided in this embodiment of the present disclosure, a characteristic of a good locality of the DMA access and non-correlation between the DMA access and another memory access are considered, and the DMA access and the non-DMA memory access are distinguished and scheduled in batches. This avoids mutual interference between the DMA access and a common memory access, ensures a performance requirement of the DMA access, and reduces a memory access latency.
An embodiment of the present disclosure further provides a memory management apparatus. The memory management apparatus provided in this embodiment of the present disclosure may include at least a part of components in the computer system shown in
In addition, an embodiment of the present disclosure further provides a memory controller. The memory controller includes a communications interface and a logic circuit that is configured to perform the memory management method in the foregoing embodiment. The communications interface is configured to receive a memory access sent by a processor of a computer system. The memory controller provided in this embodiment of the present disclosure may be shown as the memory controller 106 in
In a possible case, the memory management apparatus may further include an adjustment module 1005. The adjustment module 1005 is configured to adjust the row management policy based on the access type of the memory access and a row hit status of the target row. The row hit status includes at least one of the following states: a row hit, a row conflict, and row idle.
In a possible case, the memory management apparatus may further include a first indicator 1008. When the memory access is a read access, the adjustment module 1005 is configured to adjust the first indicator 1008 of the target memory bank based on the row hit status of the target row, where the first indicator indicates whether to close the target row after the read access is performed. In other words, the first indicator indicates a row management policy that is of the target memory bank and that is used after the read access is performed. Therefore, the execution module 1006 may execute the row management policy of the target memory bank based on the first indicator 1008. Adjusting the first indicator 1008 may be understood as adjusting the row management policy used after the read access is performed.
In a possible case, the memory management apparatus may further include a second indicator 1010. When the memory access is a write access, the adjustment module 1005 may adjust the second indicator 1010 of the target memory bank based on the row hit status of the target row, where the second indicator indicates whether to close the target row after the write access is performed. The execution module 1006 may execute the row management policy of the target memory bank based on an indication of the second indicator 1010. Adjusting the second indicator 1010 may be understood as adjusting a row management policy used after the write access is performed.
In another possible case, only the first indicator 1008 may be set, but the second indicator 1010 is not set. The execution module 1006 may directly execute a preset row management policy for a received write access. In this case, the preset row management policy corresponding to the write access may not be adjusted. In another possible case, the second indicator 1010 may alternatively be set, but the second indicator 1010 indicates the preset row management policy corresponding to the write access, and the preset row management policy does not need to be adjusted based on a row hit status of the received write access.
In a possible case, when the adjustment module 1005 adjusts the first indicator 1008 or the second indicator 1010 based on the row hit status of the target row, if the memory access causes a row hit, the adjustment module 1005 adjusts the first indicator or the second indicator to a first indication, where the first indication indicates that the target row is not closed or the target row is kept in an open state. If the memory access causes a row conflict, the adjustment module 1005 adjusts the first indicator or the second indicator to a second indication, where the second indication indicates that the target row is closed.
In another possible case, when the adjustment module 1005 adjusts the first indicator 1008 or the second indicator 1010 based on the row hit status of the target row, if the memory access causes row idle, the adjustment module 1005 determines whether the memory access may cause a row hit. If the memory access may cause a row hit, the adjustment module 1005 adjusts the first indicator or the second indicator to the first indication, where the first indication indicates that the target row is not closed or the target row is kept in the open state, and that a row hit may be caused means that a row hit is caused if a last opened row in the target memory bank is not closed. If the memory access may cause a row conflict, the adjustment module 1005 adjusts the first indicator or the second indicator to the second indication, where the second indication indicates that the target row is closed, and that a row conflict may be caused means that a row conflict is caused if a last opened row in the target memory bank is not closed.
In another case, when the adjustment module 1005 adjusts the first indicator 1008 or the second indicator 1010 based on the row hit status of the target row, the adjustment module 1005 may adjust the first indicator or the second indicator based on the row hit status of the target row and an access type of a previous memory access of the memory access.
For details about how the adjustment module 1005 adjusts the first indicator 1008 or the second indicator 1010, refer to the description in the foregoing method embodiment. Details are not described herein again.
In another case, if the memory access belongs to a first batch of memory accesses, the execution module 1006 is further configured to determine that the first batch of memory accesses are completely performed and a second batch of memory accesses are to be performed; and close the target row if an access type of the first batch of memory accesses is different from an access type of the second batch of memory accesses; keep the target row in the open state if both the first batch of memory accesses and the second batch of memory accesses are read accesses; or close the target row if both the first batch of memory accesses and the second batch of memory accesses are write accesses.
It may be understood that the memory management apparatus provided in this embodiment of the present disclosure may be the memory controller shown in
According to the memory management apparatus provided in this embodiment of the present disclosure, when a row management policy of a memory row in a DRAM is executed, a difference between localities of different access types is fully considered, a corresponding row management policy is executed based on an access type, and the corresponding row management policy may be adjusted based on a row hit status of a memory access, so that a characteristic of the memory access can be fully considered in memory row management, management can be more accurate, a memory access latency caused by an inappropriate row management policy can be reduced, and memory access efficiency can be improved.
An embodiment of the present disclosure further provides a computer program product for performing a memory management method. The computer program product includes a computer-readable storage medium storing program code. Instructions included in the program code are used for performing the method process described in any one of the foregoing method embodiments. A person of ordinary skill in the art may understand that the foregoing storage medium may include any non-transitory machine-readable medium capable of storing program code, such as a Universal Serial Bus (USB) flash drive, a removable hard disk, a magnetic disk, an optical disc, a random-access memory (RAM), a solid-state drive (SSD), or a non-volatile memory.
It should be noted that the embodiments provided in this disclosure are merely examples. A person skilled in the art may clearly know that, for convenience and conciseness of description, in the foregoing embodiments, the embodiments emphasize different aspects, and for a part not described in detail in one embodiment, refer to related descriptions in another embodiment. Features disclosed in embodiments, claims, and accompanying drawings of the present disclosure may exist independently or exist in a combination. Features described in a hardware form in embodiments of the present disclosure may be executed by software, and vice versa. This is not limited herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202010693280.4 | Jul 2020 | CN | national |
| 202011176594.3 | Oct 2020 | CN | national |
This is a continuation of International Patent Application No. PCT/CN2021/093982 filed on May 15, 2021, which claims priority to Chinese Patent Application No. 202011176594.3 filed on Oct. 28, 2020 and Chinese Patent Application No. 202010693280.4 filed on Jul. 17, 2020. All of the aforementioned patent applications are hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2021/093982 | May 2021 | US |
| Child | 18154532 | US |
