Patent Application
20060288132
Increasing memory density in a processing system can improve the system's performance. For example, stacking memory units on top of each other might let a system process more information (or process the information more efficiently) as compared to a similarly sized system that does not stack memory units. Moreover, increasing the rate at which information is stored into and/or retrieved from the memory units can improve the system's performance. At relatively high data rates, however, the integrity of electrical signals sent to and from a dense area of memory units may be degraded.
The first set of memory units 112 form a first “stack” 110. As used herein, memory units may be physically stacked by being placed substantially on top of each other, such as in a Single In-line Memory Module (SIMM), a Dual In-line Memory Module (DIMM), or a Small Outline DIMM (SODIMM). This approach may help increase the density of memory on a circuit board.
The apparatus 100 also includes a second set of memory units 122 (that form a second stack 120) and a host 150 that facilitates storing information into, and retrieving information from, the memory units 112, 122. The host 150 might comprise, for example, a Memory Controller Hub (MCH) that facilitates data exchanges between a processor and the memory units 112, 122.
The host 150 may exchange information with each of the memory units 112, 122 directly. That is, there is a direct “multi-drop” path between the host 150 and each memory unit 112, 122.
The bottom memory unit 212 in the first stack 210 may be mounted on a memory board 214 which in turn is attached to a substrate 230 via contacts 216. The contacts 216 might comprise, for example, Integrated Circuit (IC) pins and/or ball-joint contacts. The next memory unit 212 in the first stack 210 is mounted on another memory board 214, which in turn is attached the memory board 214 of the bottom memory unit 212 via contacts 216. In this way, the memory units 212 form the first stack 210.
The host 250 is also coupled to the substrate 230 via contacts 256. Traces on the substrate 230 may form conductive paths between the host 250 and the two stacks 210, 220, providing a multi-drop bus that connects with the two stacks 210, 220 in parallel.
This approach, however, may result in electrical performance problems at relatively high data rates, such as rates higher than one Gigabit-per-second (Gb/s). For example, increased noise levels, latencies, and/or reflections may degrade the integrity of the signal between the host 250 and the stacks 210, 220 to an unacceptable level. A terminal resistance (RTERM) 240 placed at the end of the signal path might improve signal integrity (e.g., by reducing an amount of signal reflection), but the improvement might still not be sufficient to enable data exchanges at high data rates.
The apparatus 300 also includes a second set of memory units 322, 324 (forming a second stack 320) and a host 350 that facilitates storing information into, and retrieving information from, the memory units 312, 314, 322, 324 (e.g., a chipset's MCH).
According to this embodiment, the host 350 exchanges information with one of the memory units 312 in the first stack 310, referred to herein as the “host” memory unit 312. That host memory unit 312 may, in turn, exchange information with the other memory units 314 in that stack 310. Similarly, the host 350 exchanges information with a host memory unit 322 in the second stack 320, which in turn may exchange information with the other memory units 324 in that stack 320. Note that the host 350 may exchange information with both host memory units 312, 322 via a single line. According to another embodiment (represented by dotted lines in
In this approach, there is a single, direct “mutli-drop” connection between the host 350 and the two stacks 310, 320 (via the host memory units 312, 322) and a “star” topology within each stack (between the host memory unit and the other memory units in that stack).
As before, the bottom memory unit 412 in the first stack 410 is mounted on a memory board 414 which, in turn, is attached to a substrate 430 via contacts 416 (e.g., ball-joint contacts). The next memory unit 412 in the first stack 410 is mounted on another memory board 414 which in turn is attached the memory board 414 of the bottom memory unit 412 via contacts 416. In this way, the memory units 412 form the first stack 410.
The host 450 is also coupled to the substrate 430 via contacts 456. Traces on the substrate 430 may form one or more conductive paths between the host 450 and the two stacks 410, 420, such as a multi-drop bus that connects to the two stacks 410, 420 in parallel.
In this case, however, the host 450 is only coupled to one memory unit in each of the two stacks 410, 420. In the example illustrated in
At 502, data is transmitted from a host to a first memory unit in a group of memory units. For example, a MCH may transmit data to a first memory unit in a stack of DRAM units in a DIMM. The data may be transmitted, for example, via a uni-directional link or a bi-directional link.
At 504, the data is “repeated” from the first memory unit to another memory unit in the group. For example, the first memory unit might buffer information received from the host. If the information is destined to be stored in another memory unit in the stack, the first memory unit would repeat the information by transmitting it to the other memory unit. If the information was instead destined to be stored within the first memory unit, of course, it would not need to be repeated to another memory unit. According to some embodiments, the first memory unit can route information received from the host to any of a number of other memory units in the stack.
The first memory unit may be configured to operate using a “repeat mode” function. For example, the host might configure the first memory unit to operate in a repeat mode during a hardware or software initialization process. In addition, memory units in the stack may be configured to activate an on-die terminal resistance.
Note that a high-speed point-to-point interface may be provided for the relatively long link between the host and a stack while a multi-drop star topology is used for communications within the stack. Such an approach may improve signaling characteristic performance problems at relatively high data rates, such as rates higher than one Gb/s.
In the example illustrated in
Although two stacks 610, 620 are illustrated in
The following illustrates various additional embodiments. These do not constitute a definition of all possible embodiments, and those skilled in the art will understand that many other embodiments are possible. Further, although the following embodiments are briefly described for clarity, those skilled in the art will understand how to make any changes, if necessary, to the above description to accommodate these and other embodiments and applications.
For example, although memory units are physically “stacked” on top each other in some of the embodiments described herein, memory units might instead be stacked or otherwise grouped by being located relatively close to each other. In addition, die stacking could be utilized instead of, or in addition to, package stacking. Moreover, each stack has been configured to have a single host memory unit in some of the embodiments described herein, but a single stack might instead have multiple host memory units (e.g., a first host memory unit could repeat data to three other memory units in the stack while a second host memory unit repeats data to three different memory units in that stack).
According to another embodiment, a host or other device can selectively configure (or re-configure) the host memory unit for a stack. For example, when a default host memory unit fails the host might re-configure the stack such that a secondary or “back-up” memory unit act as the host memory unit.
The several embodiments described herein are solely for the purpose of illustration. Persons skilled in the art will recognize from this description other embodiments may be practiced with modifications and alterations limited only by the claims.
