FIG. 1 is a bottom perspective view of the memory storage device having a poker chip design showing our new design, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design;
FIG. 2 is a bottom plan view thereof, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design;
FIG. 3 is a right side elevational view thereof, the left side elevational view being a mirror image of the right side elevational view;
FIG. 4 is a front elevational view thereof;
FIG. 5 is a rear elevational view thereof;
FIG. 6 is a top plan view thereof, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design;
FIG. 7 is a bottom perspective view thereof depicting the connector head of the memory device in an extended state, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design;
FIG. 8 is a bottom plan view thereof depicting the connector head of the memory device in an extended state, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design;
FIG. 9 is a right side elevational view thereof depicting the connector head of the memory device in an extended state, the left side elevational view with the connector head of the memory device in an extended state being a mirror image of the right side elevational view;
FIG. 10 is a front elevational view thereof depicting the connector head of the memory device in an extended state;
FIG. 11 is a rear elevational view thereof with the connector head of the memory device being in an extended state; and,
FIG. 12 is a top plan view thereof depicting the connector head of the memory device in an extended state, with the phantom lines depicting solely environmental indicia and forming no part of the claimed design.
Patent Grant
D553131