BRIEF DESCRIPTION OF THE DRAWINGS
The objectives and advantages of the present invention will become apparent upon reading the following description and upon reference to the accompanying drawings in which:
FIG. 1 shows a conventional DRAM;
FIG. 2 shows another conventional DRAM;
FIG. 3 to FIG. 16 illustrate a method for preparing a memory structure according to a first embodiment of the present invention; and
FIG. 17(
a) to FIG. 19(b) illustrate a method for preparing a memory structure according to a second embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 to FIG. 16 illustrate a method for preparing a memory structure 10 according to a first embodiment of the present invention, wherein FIG. 3(a) and FIG. 3(b) are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 3, respectively. A first etching mask such as a photoresist layer 32 is formed on a substrate 30. The substrate 30 comprises a semiconductor substrate 12 such as silicon substrate, a plurality of doped regions 13A and 13B positioned in the semiconductor substrate 12, a plurality of word lines 14 positioned on the semiconductor substrate 12, a silicon nitride spacer 16 covering the sidewalls of the word lines 14, a silicon nitride layer 18 covering the surface of the semiconductor substrate 12, and a dielectric structure 20 covering the word lines 14 and the silicon nitride layer 18. The dielectric structure 20 comprises a silicon oxide layer 22 and a silicon oxide layer 24, and the first etching mask 32 is formed on the silicon oxide layer 24. The silicon oxide layer 22 may include borophosphosilicate glass (BPSG), and the silicon oxide layer 24 may include tetraethyl silicate (TEOS).
Referring to FIG. 4(a) and FIG. 4(b), these are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 3, respectively. An anisotropic dry etching process is performed to remove a portion of the dielectric structure 20 not covered by the first etching mask 32 down to the surface of the silicon nitride layer 18 to form a plurality of dielectric pillars 36B and a plurality of first openings 38 between the dielectric pillars 36B. Subsequently, after the first etching mask 32 is removed, a deposition process is performed to form a silicon-containing layer such as a polysilicon layer 40 covering the surface of the dielectric pillars 36B, as shown in FIG. FIG. 5(a) and FIG. 5(b), these are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 3, respectively
Referring to FIG. 6, FIG. 6(a) and FIG. 6(b), wherein FIG. 6(a) and FIG. 6(b) are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 6, respectively. A first implanting mask 42 is formed to cover some of dielectric pillars 36B in a predetermined region 44 and expose the other dielectric pillars 36A outside the predetermined region 44. The dielectric pillars 36A and 36B are positioned between the word lines 14 and the active areas 46, and the first implanting mask 42 covers the dielectric pillars 36B positioned at the middle of the active areas 46. Subsequently, a first tilt implanting process is performed to implant dopants such as boron fluoride (BF2) into the silicon-containing layer 40 on the dielectric pillars 36A outside the predetermined region 44, as shown in FIG. 6(a) and FIG. 6(b).
In particular, the first tilt implanting process implants the dopants into a predetermined portion of the silicon-containing layer 40, i.e., the portion of the silicon-containing layer 40 on the left portion of the dielectric pillars 36A, to change its chemical property such as the etching resistance ability, while the other portion of the silicon-containing layer 40 on the right portion of the dielectric pillars 36A does not suffer dopants implanting and maintains its original chemical property.
Referring to FIG. 7, FIG. 7(a) and FIG. 7(b), wherein FIG. 7(a) and FIG. 7(b) are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 7, respectively. After the first implanting mask 42 is removed, a second implanting mask 48 is formed to cover the dielectric pillars 36A outside the predetermined region 44 and expose the dielectric pillars 36B inside the predetermined region 44. Subsequently, a second tilt implanting process is performed to implant dopants into the silicon-containing layer 40 on the dielectric pillars 36B inside the predetermined region 44. Preferably, the implanting direction of the first tilt implanting process is opposite to the implanting direction of the second tilt implanting process. In particular, the second tilt implanting process implants the dopants into a predetermined portion of the silicon-containing layer 40, i.e., the portion of the silicon-containing layer 40 on the right portion of the dielectric pillars 36B, to change its chemical property such as the etching resistance ability, while the other portion of the silicon-containing layer 40 on the left portion of the dielectric pillars 36B does not suffer dopants implanting and maintains its original chemical property.
Referring to FIG. 8(a) and FIG. 8(b), these are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 7, respectively. After the second implanting mask 48 is removed, a wet etching process using ammonia as etchant is performed to remove a portion of the silicon-containing layer 40 other than the predetermined portion to form the second etching mask 50 such that the left sidewall of the dielectric pillars 36B is exposed. In particular, the wet etching process removes a portion of the silicon-containing layer 40 on the left portion of the dielectric pillars 36B, i.e., the portion of silicon-containing layer 40 not suffering dopants implanting is removed by the wet etching process. Similarly, the wet etching process also remove a portion of the silicon-containing layer 40 from the right portion of the dielectric pillars 36A such that the right sidewall of the dielectric pillars 36A is exposed, as shown in FIG. 9(a) and FIG. 9(b), these are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 6, respectively.
Referring to FIG. 10(a) and FIG. 10(b), these are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 7, respectively. Another wet etching process using the buffered oxide etchant (BOE) is performed to remove a portion of the dielectric pillars 36B not covered by the second etching mask 50. The buffered oxide etchant can etch the dielectric pillars 36B via the exposed sidewall of the dielectric pillars 36B to enlarge the first openings 38 to form second openings 52. Subsequently, an anisotropic dry etching process is performed to remove the second etching mask 50 and remove a portion of silicon nitride layer 18 to expose the doped regions 13A and 13B in the semiconductor substrate 12, as shown in FIG. 11(a) and FIG. 11(b), these are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 7, respectively.
Referring to FIG. 12, FIG. 12(a) and FIG. 12(b), wherein FIG. 12(a) and FIG. 12(b) are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 12, respectively. A deposition process is performed to form a conductive layer such as a polysilicon layer, and a planarization process such as chemical mechanical polishing process or etch back process is then performed to remove a portion of the conductive layer to form a first conductive plug 54 in the second opening 52 inside the predetermined region 44 and a second conductive plug 56 in the second opening 52 outside the predetermined region 44.
The first conductive plug 54 includes a first block 54A positioned in the active area 46 and a second block 54B positioned at a first side of the active area 46. The second conductive plug 56 includes a third block 56A positioned in the active area 46 and a fourth block 56B positioned at a second side of the active area 46. Preferably, the width of the first block 54A is substantially twice as large as the width of second block 54B, the width of the third block 56A is substantially twice as large as the width of fourth block 56B, and the first side and the second side of the active area 46 are opposite sides of the active area 46.
Referring to FIG. 13, FIG. 13(a) and FIG. 13(b), wherein FIG. 13(a) and FIG. 13(b) are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 13, respectively. A dielectric layer 58 is formed to cover the first conductive plug 54 and the second conductive plug 56, and a bit line contact plug 60 connecting the first conductive plug 54 is then formed in the dielectric layer 58. Subsequently, a conductive layer such as a tungsten layer is formed by deposition process on the dielectric layer 58 and a silicon nitride mask 64 is then formed on the conductive layer. A dry etching process is performed to remove a portion of the conductive layer not covered by the silicon nitride mask 64 to form a bit line 62 connecting the bit line contact plug 60.
To achieve the electrical connection between the bit line 62 and the doped region 13A, the bit line contact plug 60 can optionally connect either the first block 54A or the second block 54B of the first conductive plug 54. Therefore the lithographic process for patterning the size and the position of the bit line contact plug 60 possesses a wider process window. Preferably, the bit line contact plug 60 connects the second block 54B of the first conductive plug 54.
Referring to FIG. 14, FIG. 14(a) and FIG. 14(b), wherein FIG. 14(a) and FIG. 14(b) are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 14, respectively. A silicon nitride spacer 66 is formed to electrically isolate the bit line 62, and a high density chemical vapor phase deposition process is then performed to form a silicon oxide layer 68 filling the gap between the bit lines 62. Subsequently, a planarization process is performed to remove a portion of silicon oxide layer 68 from the silicon nitride mask 64.
Referring to FIG. 15, FIG. 15(a) and FIG. 15(b), wherein FIG. 15(a) and FIG. 15(b) are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 15, respectively. A photoresist layer 70 having a plurality of line-shaped openings 72 is formed on the planarized surface, and the line-shaped opening 72 exposes a portion of the silicon oxide layer 68. Subsequently, using the photoresist layer 70 and the silicon nitride spacer 66 as the etching mask, a self-aligned dry etching process is performed to remove a portion of the silicon oxide layer 68 under the line-shaped openings 72 to form a plurality of contact holes 74 exposing the fourth block 56B of the second conductive plug 56.
Referring to FIG. 16, FIG. 16(a) and FIG. 16(b), wherein FIG. 16(a) and FIG. 16(b) are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 16, respectively. A silicon nitride deposition process and a dry etching process are performed after the photoresist layer 70 is removed to increase the thickness of the silicon nitride spacer 66, and a deposition process is then performed to form a conductive layer filling the contact holes 74. Subsequently, a planarization process is performed to remove a portion of the conductive layer to form a capacitor contact plug 76 connecting the fourth block 56B of the second conductive plug 56 outside the predetermined region 44, and a plurality of capacitors 78 is then formed on the dielectric layer 64 to complete the memory structure 10. The capacitors 78 are positioned above the bit line 62, and electrically connect the fourth block 56B of the second conductive plug 56 via the capacitor contact plug 46. In particular, the two capacitors 78 connects to the capacitor contact plugs 76 in the same active area 46 are positioned at the side of the active area 46.
FIG. 17(
a) to FIG. 19(b) illustrate a method for preparing a memory structure 10 according to a second embodiment of the present invention, these are cross-sectional diagrams along cross-sectional lines 1-1 and 2-2 in FIG. 3. First, the fabrication processes shown in FIG. 3(a), FIG. 3(b) and FIG. 4 are performed, and a liner oxide layer 82 is then formed on the silicon-containing layer 40 by deposition process. Subsequently, a spin-coating process and an etching process are performed to form a patterned photoresist layer 84 on a bottom portion of the first opening 38, as shown in FIG. 17(a) and FIG. 17(b).
Referring to FIG. 18(a) and FIG. 18(b), an etching process is performed to remove a portion of the liner oxide layer 82 not covered by the photoresist layer 84, i.e., remove a portion of the liner oxide layer 82 from a top portion of the first opening 38. The photoresist layer 84 is then stripped to form an implanting mask 82′ on the bottom portion of the first opening 38, as shown in FIG. 19(a) and FIG. 19(b). Subsequently, the fabrication processes shown in FIG. 5(a) and FIG. 5(b) to FIG. 16 are performed to complete the memory structure 10. The implanting mask 82′ covering the bottom portion of the first openings 38 can prevent the subsequent tilt implanting processes from implanting dopants into the semiconductor substrate 12 via the first opening 38, and the implantation of dopants into the semiconductor substrate 12 may influence the electrical property of as-fabricated electronic devices.
The conventional memory structure 100 needs the double exposure technique and the advanced lithographic technique to define the size and the position of the capacitor contact plug 110, i.e., the contact hole, as the integrated circuit technique proceeds into the nanometer generation (F is smaller than 100 nanometers). In comparison, the preparation of the present memory structure 10 does not need the double exposure technique, and patterning the size and the position of the contact hole 74 (the capacitor contact plug 76) does not need the advanced lithographic technique such as liquid immersion lithographic technique.
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.
Patent Application
20080044970
