Patent Application
20140115234
This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0120307 filed Nov. 17, 2011, the subject matter of which is hereby incorporated by reference.
The inventive concept relates generally to electronic memory technologies. More particularly, the inventive concept relates to a nonvolatile memory device, a memory system comprising the nonvolatile memory device, and related methods of operation.
Semiconductor memory devices can be roughly divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Examples of volatile memory devices include dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous DRAM (SDRAM). Examples of nonvolatile memory devices include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), a flash memory device, a phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).
In an effort to improve greater storage capacity, researchers have developed nonvolatile memory devices capable of storing more than one bit of data per memory cell. Such devices are commonly referred to as multi-bit nonvolatile memory devices or multi-level cell (MLC) memory devices. Compared with single-bit nonvolatile memory devices, multi-bit nonvolatile memory devices currently suffer from relatively slow performance and reliability. Accordingly, there is a general need for techniques and technologies that can improve both performance and reliability in multi-bit nonvolatile memory devices.
According to an embodiment of the inventive concept, a method of programming a nonvolatile memory device comprises generating write data and metadata associated with the write data, generating a seed associated with the write data and scrambling the generated seed, randomizing the write data and the metadata using the scrambled seed, and programming the randomized write data, the randomized metadata, and the scrambled seed in the nonvolatile memory device.
According to another embodiment of the inventive concept, a memory system comprises a nonvolatile memory device and a controller. The nonvolatile memory device comprises a single-level cell area and a multi-level cell area. The controller is configured to generate metadata associated with write data, generate a seed associated with the write data, scramble the generated seed, randomize the write data and the metadata using the scrambled seed, and program the randomized data, the randomized metadata, and the scrambled seed in the nonvolatile memory device.
These and other embodiments of the inventive concept can potentially improve the reliability of program operations in multi-bit nonvolatile memory devices.
The drawings illustrate selected embodiments of the inventive concept. In the drawings, like reference numbers indicate like features.
Embodiments of the inventive concept are described below with reference to the accompanying drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept.
In the description that follows, the terms first, second, third, etc., may be used to describe various features, but these features are not to be limited by these terms. Rather, these terms are only used to distinguish between different features. Thus, a first feature could be alternatively referred to as a second feature, and vice versa, without changing the meaning of the relevant description.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms “a”, “an” and “the” are intended to encompass the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises” and/or “comprising,” when used in this specification, indicate the presence of stated features but do not preclude the presence or addition of other features. The term “and/or” indicates any and all combinations of one or more of the associated listed items.
Where a feature is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another feature, it can be directly on, connected, coupled, or adjacent to the other feature, or intervening features may be present. In contrast, where a feature is referred to as being “directly on,” “directly connected to”, “directly coupled to”, or “immediately adjacent to” another feature, there are no intervening features present.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to
Nonvolatile memory device 1100 comprises a single-level cell area 1110 and a multi-level cell area 1120. Single-level cell area 1110 comprises a plurality of memory cells each configured to store 1-bit data. Multi-level cell area 1120 comprises a plurality of memory cells each configured to store two or more bits of data. Single-level cell area 1110 and multi-level cell area 1120 are divided into memory blocks.
Controller 1200 controls program, read, erase, and background operations of nonvolatile memory device 1100. Controller 1200 typically communicates with nonvolatile memory device 1100 using information such as an address ADDR, data, metadata, a seed, and a control signal CTRL.
Address ADDR typically comprises an address associated with memory cells of nonvolatile memory device 1100 in which data is to be programmed, an address associated with memory cells of nonvolatile memory device 1100 from which data is to be read, or an address associated with memory cells of nonvolatile memory device 1100 to be erased.
The data comprises data to be programmed in nonvolatile memory device 1100 or data read out from nonvolatile memory device 1100. The data can include data randomized by controller 1200.
The metadata comprises metadata to be programmed in nonvolatile memory device 1100 or metadata read out from nonvolatile memory device 1100. The metadata typically comprises information required to control nonvolatile memory device 1100, such as information on data characteristics, information on statuses of nonvolatile memory device 1100, and information for error correction. The metadata can include metadata randomized by controller 1200.
The seed may be a pattern used by controller 1200 to randomize the data and the metadata. The seed may be a pattern scrambled by controller 1200.
Control signal CTRL comprises various signals that are generated by controller 1200 to control nonvolatile memory device 1100
Controller 1200 comprises a seed generator 1210, a seed scrambler 1220, and a randomizer and de-randomizer 1230.
Seed generator 1210 generates a seed. For example, seed generator 1210 may output a predetermined pattern of data as a seed. In some embodiments, seed generator 1210 stores a plurality of seeds using a table and selects a specific seed among the plurality of seeds based on input data. In some embodiments, seed generator 1210 selects the specific seed based on an address transferred from a host. In some embodiments, seed generator 1210 selects the specific seed based on a program and erase number of nonvolatile memory device 1100. In some embodiments, seed generator 1210 outputs a generated pattern as a seed without requiring input data.
Seed scrambler 1220 receives a seed from seed generator 1210 and scrambles the input seed. For example, seed scrambler 1220 may scramble the seed using an operation between adjacent bits, such as an AND operation or an exclusive-OR. Alternatively, seed scrambler 1220 may scramble the seed using an operation such as bit-swapping between adjacent bits. Randomizer and de-randomizer 1230 is configured to randomize or de-randomize data and metadata using a scrambled seed. Randomizer and de-randomizer 1230 may be configured to randomize data and metadata to be programmed in nonvolatile memory device 1100 in a program operation and to de-randomize data and metadata read out from nonvolatile memory device 1100 in a read operation.
Referring to
Next, seed generator 1210 generates a seed, and seed scrambler 1220 scrambles the generated seed (S 120). Thereafter, randomizer and de-randomizer 1230 randomizes the write data and the metadata using the scrambled seed (S130).
Next, the randomized data, the randomized metadata, and the scrambled seed are programmed in nonvolatile memory device 1100 (S140). Controller 1200 typically sends the randomized data, the randomized metadata, and the scrambled seed to nonvolatile memory device 1100, and nonvolatile memory device 1100 programs the randomized data, the randomized metadata, and the scrambled seed in memory cells connected to a wordline in single-level cell area 1110 or multi-level cell area 1120.
Memory cells of multi-level cell area 1120 store LSB data, CSB data, and MSB data. Programming of the LSB, CSB, and MSB data is performed by a 3-step approach. Where programming is performed using the 3-step approach, memory cells of single-level cell area 1110 are used as a buffer memory.
Referring to
Next, an LSB seed and a CSB seed are generated, and the LSB and CSB seeds are scrambled (S220). Seed generator 1210 typically generates the LSB seed corresponding to LSB data and the CSB seed corresponding to CSB data. Seed scrambler 1220 scrambles the LSB seed and the CSB seed.
Thereafter, the LSB data and LSB metadata are randomized using the scrambled LSB seed, and CSB data and CSB metadata are randomized using the scrambled CSB seed (S230). Randomizer and de-randomizer 1230 randomizes the LSB data and the LSB metadata using the LSB seed. Randomizer and de-randomizer 1230 also randomizes the CSB data and the CSB metadata using the CSB seed.
The randomized LSB data, the randomized LSB metadata, the scrambled LSB seed, the randomized CSB data, the randomized CSB metadata, and the scrambled CSB seed are programmed in a multi-level cell area 1120 (S240). The randomized LSB data, the randomized LSB metadata, the scrambled LSB seed, the randomized CSB data, the randomized CSB metadata, and the scrambled CSB seed are programmed in memory cells in a wordline of multi-level cell area 1120.
The randomized LSB data, the randomized LSB metadata, the scrambled LSB seed, the randomized CSB data, the randomized CSB metadata, and the scrambled CSB seed are then programmed in single-level cell area 1110 (S250). The randomized LSB data, the randomized LSB metadata, and the scrambled LSB seed are programmed in memory cells connected to a first wordline of single-level cell area 1110. The randomized CSB data, the randomized CSB metadata, and the scrambled CSB seed may be programmed in memory cells in a second wordline of single-level cell area 1110.
Referring to
1-bit data is programmed in memory cells connected to the first wordline of single-level cell area 1110. This 1-bit data comprises randomized LSB data, randomized LSB metadata, and a scrambled LSB seed. The memory cells can be programmed to erased state E or a program state P, respectively. 1-bit data is also programmed in memory cells connected to the second wordline of single-level cell area 1110. This 1-bit data comprises randomized CSB data, randomized CSB metadata, and a scrambled CSB seed. Memory cells connected to the third wordline single-level cell area 1110 retain erase state E.
Referring to
Next, an MSB seed is generated, and the generated MSB seed is scrambled (S320). Seed generator 1210 typically generates the MSB seed, and seed scrambler 1220 scrambles the generated MSB seed.
Thereafter, the MSB data and the MSB metadata are randomized using the scrambled MSB seed (S330). Randomizer and de-randomizer 1230 typically randomizes the MSB data and the MSB metadata using the scrambled MSB seed.
Then, randomized LSB data, randomized LSB metadata, a scrambled LSB seed, randomized CSB data, randomized CSB metadata, and a scrambled CSB seed are read out from single-level cell area 1110 (S340).
Next, the randomized MSB data, the randomized MSB metadata, and the scrambled MSB seed are programmed in multi-level cell area 1120 (S350). This programming may be referred to as coarse programming.
Finally, the randomized MSB data, the randomized MSB metadata, and the scrambled MSB seed are programmed in memory cells connected to a third wordline of single-level cell area 1110 (S360).
Referring to
Referring to
Next, programming is performed on multi-level cell area 1120 based on the randomized LSB data, randomized LSB metadata, scrambled LSB seed, randomized CSB data, randomized CSB metadata, scrambled CSB seed, randomized MSB data, randomized MSB metadata, and scrambled MSB seed (S420). This programming comprises fine programming.
Compared with threshold voltage distributions in
After programming (e.g., 1-step programming, coarse programming, or fine programming) is performed on the first wordline of multi-level cell area 1120, programming (e.g., 1-step programming, coarse programming, or fine programming) is performed on the second wordline, which is adjacent to the first wordline. After the programming is performed on the second wordline, memory cells of the first wordline may experience the coupling. Consequently, a threshold voltage distribution of memory cells connected to the first wordline may widen.
Where memory cells of the first and second wordlines are programmed using the 1-step approach, a threshold voltage distribution of memory cells connected to the first wordline may widen. Where coarse programming is carried out on memory cells connected to the first wordline, a threshold voltage distribution of the memory cells connected to the first wordline may become narrow (refer to
Where the coarse programming is performed on memory cells connected to the second wordline, a threshold voltage distribution of the memory cells connected to the first wordline may widen. If the fine programming is executed on the memory cell connected to the first wordline, a threshold voltage distribution of the memory cells connected to the first wordline may become narrow (refer to
If the fine programming is performed on memory cells connected to the second wordline, a threshold voltage distribution of the memory cells connected to the first wordline may widen. However, referring to
As described above, where the 3-step programming approach is used, it is possible to minimize coupling effect experienced by programmed memory cells in multi-level cell area 1120 (i.e., fine-programmed memory cells). Programming performed by the 3-step programming approach using single-level cell area 1110 as a buffer may be referred to as On-chip Buffered Programming (OBP).
Where data being programmed in nonvolatile memory device 1100 has a specific pattern, the reliability of the programmed data may decrease. For example, where data with the same pattern is programmed in a plurality of pages, an electric field among memory cells may be reinforced such that charges accumulated or trapped at memory cells are discharged. It is possible to prevent a specific pattern from being programmed in nonvolatile memory device 1100 by randomizing data (including write data, metadata, and a seed) and programming the randomized data. Thus, the reliability of data programmed in nonvolatile memory device 1100 may be improved.
Referring to
Controller 3200 comprises a seed generator 3210, a seed scrambler 3220, and a randomizer and de-randomizer 3230. As described in relation to
Referring to
Nonvolatile memory device 4100 comprises a single-level cell area and a multi-level cell area.
Controller 4200 comprises a seed generator 4210, a seed scrambler 4220, and a randomizer and de-randomizer 4230. Similar to embodiments described in relation to
Memory card 4000 can take various alternative forms, such as a PC (PCMCIA) card, a CF card, an SM (or, SMC) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), a security card (SD, miniSD, microSD, SDHC), or a universal flash storage (UFS) device, for example.
Referring to
Each of nonvolatile memory devices 5100 comprises a single-level cell area and a multi-level cell area. Some of nonvolatile memory devices 5100 may be single-level cell devices, and the others may be multi-level cell devices.
Controller 5200 comprises a seed generator 5210, a seed scrambler 5220, and a randomizer and de-randomizer 5230. Similar to embodiments described in relation to
Referring to
Memory system 3000 is connected electrically with elements 6100 through 6400 via a system bus 6500. Data provided via user interface 6300 or processed by central processing unit 6100 is stored in memory system 3000.
Although
As indicated by the foregoing, in certain embodiments of the inventive concept, user data, metadata, and a seed are randomized, and the randomized user data, metadata, and seed are programmed in a nonvolatile memory device. Thus, a programming method and a memory system with improved reliability may be provided.
The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.
