Patent Application
20140075100
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-200638, filed Sep. 12, 2012; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate to memory systems, computer systems and memory management methods.
The SSD (Solid State Drive) loaded with memory chips equipped with NAND type memory cells has been attractive for computer systems like personal computers (PC), etc. The SSD has the advantages of high speed, light weight, and the like as compared with the magnetic disk apparatus.
Embodiments provide a memory system, computer system and memory management method which are capable of effectively reducing the generation of faults such as those preventing starting of the computer system.
In general, according to one embodiment, cells (memory cell transistor, memory cell), which are used in SSDs, have an upper limit in the number of rewrites of data that can be performed on the cell. Therefore, the life of an SSD is shortened if rewriting is concentrated in one place. To prevent this, wear leveling is performed. Wear leveling is a technique of transferring data from a cell having many rewrites to a cell having few rewrites to make the number of rewrites in all cells uniform.
According to one embodiment of the present disclosure, a memory system includes non-volatile storage having a physical memory region and a controller for conducting data transmission between the non-volatile memory and a host. The controller includes a section management module and a wear leveling module. The section management module divides the physical memory region into multiple sections, including a first section and one or more second sections. The wear leveling module performs wear leveling for each section in the second sections and does not perform wear leveling for the first section. The section management module performs expansion of the second sections according to a region expansion request from the host.
If a cell storing system data or other data that affect the effective management of a computer system (e.g., operation system (OS) data), experiences failure, a fatal situation preventing start-up of the computer system generally occurs. Namely, data cannot be read out from the SSD. Wear leveling is performed without distinguishing system data vs. user data (application program vs. data prepared by user). The probability of causing loss of system data is then generally equal to the probability of causing loss of user data. A fatal situation occurs if the system data are lost at startup of the SSD.
The rewrite frequency of system data is generally less than that of user data. According to embodiments of the disclosure, the rewrite frequency of a memory region is made smaller than other memory regions by specifying a memory region for storing system data and omitting wear leveling in this memory region. In this way, the rewrite frequency of the memory region for system data can be made lower than that for other memory regions, so that a failure such as prevention of start-up of the computer system can be reduced in likelihood. According to embodiments of the present disclosure, a host can expand memory regions specified for storing system data by transmitting the prescribed requirement to the SSD.
Hereinafter, the memory system, computer system and memory management method according to the embodiments are explained in detail with reference to the attached drawings. To that end, an explanation is given in the instance of applying the memory system of the embodiments to an SSD, however the applicability of the memory system of the embodiments is not limited to SSDs. Furthermore, the present disclosure is not limited to the disclosed embodiments.
Here, an address described by an LBA is called a logical address.
SSD 100 is provided with NAND memory 1 and controller 2, which performs data transmission between host 200 and NAND memory 1. The NAND memory 1 includes one or more memory chips 3, each of which is provided with a memory cell array 30. Memory cell array 30 includes multiple blocks that function as a single unit.
Each memory cell transistor MT includes a MOSFET (metal oxide semiconductor field effect transistor) having a laminated gate structure formed on a semiconductor substrate. The laminated gate structure includes a charge accumulating layer (floating gate electrode) formed on the semiconductor substrate via a gate insulating film and a control gate electrode formed on the charge accumulating layer via an insulating layer between the gates. Memory cell transistor MT changes threshold voltage value according to the number of electrons stored in the floating gate electrode, and stores data complying with the difference of the threshold value voltage. The memory cell transistor MT may be configured in a mode for storing 1 bit or for storing multiple values (data of 2 or more of bits).
In each NAND string, (n+1) memory cell transistors MT are arranged between the source of selection transistor ST1 and the drain of selection transistor ST2 so as to serially connect the current passage, respectively. The control gate electrode is connected to the word line WL0-WLq successively from memory cell transistor MT positioned at the most-drain side. Thus, the drain of memory cell transistor MT connected to word line WL0 is connected to the source of selection transistor ST1, and the source of memory cell transistor MT connected to word line WLq is connected to the drain of selection transistor ST2.
Word lines WL0-WLq are connected in common to the control electrode of memory cell transistor MT between NAND strings in a block. Then, the control gate electrodes of memory cell transistors MT in the same direction in the block are connected to the same word lines WL. (m+1) units of memory cell transistors MT to be connected to same word lines WL are handled as one page, and data writing in and data reading out are carried out in a pagewise fashion.
Bit lines BL0-BLp are connected in common to the drain of selection transistor ST1 between blocks. Then, NAND strings in the same line in multiple blocks are connected to same bit line BL.
Furthermore, the memory cell array 30 that forms the memory region of NAND memory 1 may be multi-level memory (MLC: Multi Level Cell) storing two bits or more in one memory cell, or single-level memory (SLC: Single Level Cell) storing one bit in one memory cell.
Memory cell array 30 provided in memory chip 3 constitutes the physical memory region of NAND memory 1. According to the first embodiment, the physical memory region provided in NAND memory 1 is managed by controller by division into a memory region assigned to store system data and another memory region.
First section 31a is the region wherein host 200 writes in system data. Second section 31b is the region wherein host 200 writes in data having relatively low rewrite frequency among user's data (for example, application program, validation code data for an application program, etc.). Third section 31c is the region wherein host 200 writes in data having relatively high rewrite frequency among user's data (for example, data prepared by user, animation film, imaged, etc.). Division of the memory region of NAND memory 1 can be appropriately established at the time of configuration by host 200. Hereinafter, when first section 31a, second section 31b, and third section 31c are expressed as one general entity, the term “section 31” may be used.
Each region is provided with an LBA-allocated region and an extended region. Namely, the first section 31a is provided with logical memory region 32a and extended region 33a. Likewise, the second section 31b is provided with logical memory region 32b and extended region 33b and the third section 31c is provided with logical memory region 32c and extended region 33c.
Logical memory region 32a has a size of, for example, Cs, and logical addresses with a range of 0−Cs−1 are allocated thereto. Logical memory region 32b has a size of, for example, Cu1, and logical addresses with a range of Cs to Cs+Cu1−1 are allocated thereto. Logical memory region 32c has a size of, for example, Cu2, and logical addresses with a range of Cs+Cu1−Cs+Cu1+Cu2−1 are allocated thereto. Host 200 can access the logical memory region 32a to 32c by using a logical address.
Each of extended regions 33a to 33c include one or more free blocks (blocks not allocated with LBA). Each of extended regions 33a to 33c is used for garbage collection in the same section, recovery of pad block, etc. Garbage collection means the operation of collecting valid data from multiple blocks, copying the collected valid data on other blocks, and eliminating the contents of the old blocks. In the course of garbage collection, for instance, valid data are collected from logical memory region 32a and copied on a free block that is maintained in extended region 33a. The copied block is then rewritten in logical memory region 32a, and original copy block is also included in extended region 33a after eliminating the contents of the copied block. In this way, for a cell belonging to one of the sections of section 31, logical addresses for data is allocated by garbage collection so that allocated logical addresses remain valid. Furthermore, in a cell belonging to one of the sections of section 31, a logical address varies within the range allocated to the cell-belonging section 31 as a result of garbage collection. In other words, over time, various logical block addresses are associated with a particular memory cell.
Furthermore, in cells belonging respectively to second section 31b and third section 31c, a logical address may also fluctuate within the range allocated to respective sections as a result of wear leveling.
Each of extended regions 33a to 33c has a corresponding logical memory region sized to comply with the rewriting frequency (i.e., the write amplitude) of the corresponding logical memory region (i.e., logical memory region 32a, 32b, and 32c), respectively. Here, it is written that extended region 33a has a size of FBs; extended region 33b has a size of FBu1; and extended region 33c has a size of FBu2. Furthermore, the write amplitude of section 31 may be selected as desired prior to manufacturing, or may be determined by a command from host 200.
Each of the various sections of section 31 can be expanded by request from host 200.
Furthermore, hereinafter, the appropriate one of logical memory regions 32a to 32c is sometimes written as logical memory region 32. Further, the appropriate one of extended regions 33a to 33c is sometimes written as extended region 33.
Memory unit 22 includes logical-physical conversion table 26, wherein equivalence between a logical address described in LBA and a physical address of NAND memory 1 is recorded and section management information 27, describing the information specifying each section. Here, as an example, it is assumed that the range of addresses (logical address and physical address) for each section is described in section management information 27.
Arithmetic unit 21 functions as read/write module 23, wear leveling module 24, and section management module by executing a prescribed firmware program. The storage location of firmware is not specifically limited. When memory unit 22 includes non-volatile memory, firmware may be housed in memory unit 22 prior to operation. When memory unit 22 includes volatile memory, it may be housed in a prescribed place of NAND memory 1 prior to operation.
Furthermore, some or all of the elements of arithmetic unit 21 may include hardware circuits.
Section management module 25 forms (divides) sections in the physical memory region of NAND memory 1 based upon region preparation requests from host 200. Particularly, section management module 25 divides the physical memory region of NAND memory 1 into multiple sections including a section of no wear leveling (i.e., first section 31a) and one or more sections of wear leveling (i.e., second sections 31b and 31c). A region preparation request includes 1) assignment of the range described in terms of logical address and 2) assignment of degree of priority. Section management module 25 creates a correspondence between the assigned address range and the assigned degree of priority and subsequently registers the correspondence in section management information 27.
Section management module 25 conducts expansion of sections in compliance with region expansion requests from host 200.
The degree of priority is used as information for specifying sections. When host 200 issues a request to expand any of section 31 (region expansion request), for instance, the section subject to expansion is assigned using a degree of priority. Here the section to which the highest degree of priority is assigned is denoted as first section 31a; the section to which next second highest degree of priority is assigned is denoted as second section 31b; and the section to which the third highest degree of priority is assigned is denoted as third section 31c.
Read/write section 23 writes data into NAND memory 1 as requested by host 200. Furthermore, read/write section 23 reads out data from NAND memory 1 and transfers the read-out data to host 200 as requested by host 200. Read/write section 23 can specify the physical address of an accessed object by referring to logical-physical conversion table 26 when data are accessed from NAND memory 1.
Read/write section 23 can execute garbage collection in each section when invalid data increases in logical memory region 32 and extended region 33 belonging to same section is full. Read/write module 23 can recognize the boundary of each section by referring to section management information 27. When a change occurs in the correspondence relation between logical address and physical address due to garbage collection, read/write section 23 records the change to logical-physical conversion table 26.
Wear leveling module 24 separately executes wear leveling of second section 31b and third section 31c. Namely, wear leveling module 24 executes wear leveling to data housed in second section 31b and executes wear leveling to data housed in third section 31c. When wear leveling is executed, the physical address of the data transferred by wear leveling is changed. Wear leveling module 24 reflects the modified correspondence in logical-physical conversion table 26 when the correspondence between logical address and physical address is changed due to the execution of wear leveling. Wear leveling module 24 can recognize the boundary of each section by referring to section management information 27.
Next, the operation of SSD 100 is explained.
Next, section management module 25 attaches the range of physical memory regions obtained by adding assignment size and extended region size to the assigned degree of priority and registers it in section management information 27 (step S3). Furthermore, how the physical memory region obtained by adding assignment size and extended region size is stored or recorded is not specifically limited. Section management module 25 reports the completion of region preparation to host 200 (step S4). The operation of preparing the section is completed.
Host 200 can prepare multiple sections by repeating the operation shown in
During a region change requirement, the range subject to change is assigned using a logical address. In other words, the range subject to change is assigned from logical memory region 32 (i.e., one of logical memory regions 32a, 32b, or 32c). In changing a section in the region of the assigned range, a portion of corresponding extended region 33 (i.e., one of extended regions 33a, 33b, or 33c) is also changed to the section corresponding to the degree of priority assigned from the section to which the assigned range belongs. Section management module 25 changes an available portion of extended region belonging to the section being expanded into, the available portion having an appropriate range available, i.e., the same range as the assignment size. Section management module 25 also changes extended region 33 belonging to the section subject to expansion (step S12). Section management module 25 requests the size of the region to be changed in the appropriate extended region 33 based on the same order (i.e., assigned degree of priority) as in step S2. Furthermore, the change of the section is implemented by editing section management information 27.
Then, the section management module 25 reports the completion of section expansion to host 200 (step S13), and the expansion operation of the section is completed.
As described above, according to the first embodiment of the present disclosure, the section management module 25 divides the physical memory region of NAND memory 1 into multiple sections including a section in which wear leveling is not executed, and one or more sections in which wear leveling is executed, and subsequently conducts the expansion of sections by complying with a region expansion request from host 200. Thus, it is possible to provide a section, in which the increase in rate of write frequency is lower than other sections, in host 200. Host 200 places system data in the section in which the rate of write frequency is lower than other sections, and places user data in other sections so that the reliability of system data is higher than user data. Furthermore, host 200 can expand a system data storage section which has become insufficient, by updating system data, etc. since the host can expand sections by issuing region expansion requests. Thus, effective management can be carried out for reducing the occurrence of a failure such as that preventing computer system start-up.
The region expansion request includes the assignment of a degree of priority as section information for specifying the region subject to change and the section to be expanded into, and the section management module 25 changes the section of the region subject to change that is assigned in the section expansion request to the section that is specified by the assigned degree of priority. In this way, host 200 can freely expand a section that has insufficient storage capacity for system data.
According to the first embodiment, it is necessary that a host provides the SSD 100 with an assigned range that is subject to change and perform a region expansion request. According to a second embodiment, a host can send a request for region expansion without assigning the range to the SSD.
The components of a computer system according to the second embodiment are the same as those of the first embodiment except for the section management module. Therefore, the section management module according to the second embodiment is denoted with 28 to, be distinguished from that of the first embodiment, and the components that are the same as those of the first embodiment are given common reference numbers to avoid repeated explanation.
According to the second embodiment, host 200 can issue to SSD 100 the degree of priority that specifies the section to be expanded and the address range that is subject to expansion. When the region expansion request is received, section management module 28 obtains the region having the assignment size from a blank region of a section having a priority at least a degree lower than the assigned priority of the section being expanded, and the obtained region can be added to the section being expanded.
Then, section management module 28 determines whether a blank region having the necessary assignment size exists in section 31 with a degree of priority lower than the section 31 that is the subject of expansion (i.e., is there a logical memory region 32 of section 31 with a degree of priority lower than section 31 of the section that is being expanded?) (step S22). Here, section management module 28 searches the section 31 having a degree of priority that is lower than the section 31 that is the subject of expansion. The searching is performed in order of descending priority, starting with those sections having the higher degree of priority. If there is a blank region that can accommodate the assignment size in a section with a degree of priority lower than the section subject to expansion (step S22, yes), section management module 28 changes a part of said blank region and associated extended region 33 to the section subject to expansion (step S23).
By treatment of step S23, sections are generated where the size of a blank region that can accommodate the assignment size is reduced as part of the region change request. Section management module 28 then determines whether a blank region of appropriate size exists in a section (called section B) with a degree of priority lower than the section that is reduced in size in step S23 (called section A) (step S24). To that end, in step S24, section management module 28 searches section 31 in descending order of degree of priority. When there is a blank region of appropriate size in section B (step 24, Yes), section management module 28 changes a part of the blank region and extended region from section B (the section with the higher degree of priority) to section A (the section with the lower degree of priority) (step S25). Section management module 28 continues to perform step S24 after completing treatment of step S25 until no blank regions of the appropriate size are available in sections of lower priority.
When there is no blank region that can accommodate the assignment size in section B (step 24, No), after changing the range, section management module 28 reports the section-changed region and section to host 200 (step S26) and completes the operation of section expansion. When there is no blank region of that can accommodate the assignment size in the section with a degree of priority lower than the section subject to expansion (step S22, No), section management module 28 reports the insufficiency of blank region (step S27) to host 200 to complete the operation of section expansion.
According to the second embodiment, priority degree is pre-set by host 200 in each of multiple sections; a region expansion request includes assignment of priority specifying expansion size and section that is to be the subject of expansion; section management module 28 searches for a blank region within sections having lower degrees of priority than the section specified by the assigned degree of priority, and changes the section that includes the appropriately-sized blank region to the section that is the subject of expansion. In this way, host 200 can conduct expansion of a section without assigning the specific section to be used for accommodating the section expansion operation.
When host 200 places system data into first section 31a, user data having relatively low write amplitude into second section 31b, and user data having relatively high write amplitude into third section 31c, the increase in rate of rewrite frequency increases in order of first section 31a, second section 31b and third section 31c. Namely, the reliability of each section decreases in order of first section 31a, second section 31b and third section 31c. Since section management module 28 searches blank regions from sections having high degrees of priority first, as mentioned above, regions having high reliability can be changed to sections that can be the subject expansion.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2012-200638 | Sep 2012 | JP | national |
