Number | Name | Date | Kind |
---|---|---|---|
4493026 | Olnowich | Jan 1985 | A |
4797814 | Brenza | Jan 1989 | A |
5781926 | Gaskins et al. | Jul 1998 | A |
5784590 | Cohen et al. | Jul 1998 | A |
5802572 | Patel et al. | Sep 1998 | A |
5835929 | Gaskins et al. | Nov 1998 | A |
5897655 | Mallick | Apr 1999 | A |
6065091 | Green | May 2000 | A |
6115794 | Arimilli et al. | Sep 2000 | A |
6119205 | Wicki et al. | Sep 2000 | A |
Entry |
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“Processor Cache Sector Invalidate Signal on a Processor Bus”, IBM Technical Disclosure Bulletin, May 1994, Volume No.: 37, Issue No.: 5, Page No.: 553-554, May, 1994.* |
Jim Handy,, “The Cache Memory Handbook”, Academic Press, TK7895.M4H35, 1993, pp. 47-91. |