BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a prior art memory system with motherboard termination.
FIG. 2 illustrates a prior art memory system with on-die termination (ODT).
FIG. 3 illustrates a prior art ODT circuit.
FIG. 4 illustrates a prior art control scheme for ODT.
FIG. 5 illustrates the operation of a prior art memory system having ODT.
FIG. 6 illustrates an embodiment of a memory system according to some of the inventive principles of this patent disclosure.
FIG. 7 illustrates an embodiment of a memory agent according to some of the inventive principles of this patent disclosure.
FIG. 8 illustrates the operation of another embodiment of a memory system according to some of the inventive principles of this patent disclosure.
DETAILED DESCRIPTION
FIG. 6 illustrates an embodiment of a memory system according to some of the inventive principles of this patent disclosure. First and second memory agents 100,102 are coupled to a third memory agent 104 by a transmission line 106. The transmission line may be simultaneously terminated with a first impedance 108 at the first memory agent and a second, substantially different impedance 110 at the second memory agent. For example, during a write operation, the third memory agent may need to transmit data to the first memory agent. During this operation, the first memory is active and the second memory agent is inactive. The third memory agent transmits a signal which propagates to both memory agents over the transmission line. The termination impedances may be chosen so that more signal power is received at the first memory agent than the second memory agent. Preferably, the value of the first impedance Z1 matches the transmission line so that power transfer to the first agent is maximized, and the value of the second impedance Z2 is set to an appropriate low value so the signal is reflected and power transfer to the second agent is minimized.
In one embodiment, the transmission impedances Z1 and Z2 may be selected dynamically between changes in the active/inactive state of the memory agents, the type of command (read/write), etc. For example, if the write operation to the first memory agent 100 as described above is followed by a write to the second memory agent, the values of Z1 and Z2 may be switched between the back-to-back write operations so that the signal is reflected by Z1 at the first agent (which is now inactive), and absorbed by Z2 at the second agent (which is now active). In an embodiment having multiple ranks of memory devices, the transmission impedances for different ranks may also be selected dynamically.
FIG. 7 illustrates an embodiment of a memory agent according to some of the inventive principles of this patent disclosure. The memory agent 112 includes a memory core 114, a terminator 116 having at least two finite termination values, and logic 118 to dynamically select the termination values that may be presented to a transmission line 120. In one embodiment, the memory agent may be a memory device having the core, the terminator and the logic fabricated on a single semiconductor die. In another embodiment, the memory agent may be a memory module where the memory core is located on a memory device mounted on the module.
The selected termination value may be changed dynamically depending on the active/inactive state of the memory agent, the type of command (read/write), etc. In an embodiment having multiple ranks of memory devices, the transmission impedances for different ranks may also be selected dynamically.
FIG. 8 illustrates the operation of another embodiment of a memory system according to some of the inventive principles of this patent disclosure. In this example, one memory agent is a memory controller, and two agents are modules, specifically, dual in-line memory modules (DIMMs). The DIMMs have a 2R/1R configuration, that is, the first module has two ranks of memory devices, and the second module has one rank. The memory controller and modules are connected by a memory channel having a bus structure and signaling similar to DDR2, but with dynamic termination according to some of the inventive principles of this patent disclosure. For this example, the terminators are assumed to be on-die in the memory devices, and the termination impedances may be resistances of 20Ω and 120Ω for a system operating at 1333 Mts.
The top row of FIG. 8 illustrates the selected termination impedances for a write command to Rank 1 of DIMM 1. Shaded cells in FIG. 8 indicate the active DIMM/rank. The controller, which transmits write data to the modules, is unterminated as indicated by the ∞ symbol (essentially infinite impedance or “off” state). A termination impedance of 120Ω is selected for the active device which is the Rank 1 memory device on DIMM 1. The Rank 2 memory device on DIMM 1 is inactive and unterminated. A termination impedance of 20Ω is selected for the inactive Rank 1 memory device on DIMM 2. DIMM 2 has no second rank memory device (N/A). This selection of termination impedances may cause more signal power to be transmitted to the active device than any of the inactive devices. Depending on the implementation details of the memory channel transmission lines, on-die termination circuits, module connectors, operating speed, etc., the termination impedance for an active device (120Ω ) may be matched to the transmission line to maximize power transfer to the active device, while the termination impedance for an inactive device (20Ω) may be chosen to reflect most of the power and minimize signal transfer to the inactive device.
The next two rows of FIG. 8 illustrate the selection of termination impedances for write commands to Rank 2 of DIMM 1, and Rank 1 of DIMM 2. The bottom three rows illustrate the selection of termination impedances for read commands for all three combinations of active DIMMs and ranks of memory devices.
As compared to the prior art system illustrated in FIG. 5, the embodiment of FIG. 8 may enable a transmission line to be simultaneously terminated with two different impedances at different memory agents. Moreover, some of the inventive principles of this patent disclosure may enable termination impedances to be varied dynamically between read/write, active/inactive states, whereas prior art systems could only enable or disable termination, not change the termination value except, e.g., during the process of changing an extended mode register.
FIG. 9 illustrates the operation of another embodiment of a memory system according to some of the inventive principles of this patent disclosure. In the example of FIG. 9, the system is similar to the embodiment of FIG. 8, but with a 1R/2R configuration; that is, the first module has one rank of memory devices, and the second module has two ranks. FIGS. 10 and 11 illustrate the operation of two more embodiments of memory system according to some of the inventive principles of this patent disclosure, this time with 2R/2R and 1R/1R configurations, respectively.
The embodiments described herein may be modified in arrangement and detail without departing from some of the inventive principles. For example, embodiments have been described having specific numbers of modules, memory devices, ranks, operating speeds, termination impedances and resistances, etc., but the inventive principles are not limited to these details. Terminators are described as having different termination values, but they need not necessarily be switched between discrete values. Logic may be implemented in hardware, software, or a combination of both. As a further example, memory modules and memory controllers may be implemented as separate components, or they may be fabricated on a common printed circuit board. As yet another example, some of the embodiments describe memory write operations from a memory controller to a memory module, but some of the inventive principles may also be applied to module-to-module transfers, controller-to-memory device transfers, and other configurations. Accordingly, such variations are considered to fall within the scope of the following claims.
Patent Application
20070247185
