Memory system

Abstract

A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:

FIG. 1 is a block diagram showing a first embodiment;

FIG. 2 is a block diagram showing the details of the optical interface unit of FIG. 1;

FIG. 3 is a flowchart showing an operation of the memory system according to the first embodiment;

FIG. 4 is a timing diagram showing an overview of the steps S10-S14, S30-34 of FIG. 3;

FIG. 5 is an explanatory diagram showing an operation of the memory system according to the first embodiment;

FIG. 6 is a timing diagram showing an overview of the read operations according to the first embodiment;

FIG. 7 is a block diagram showing a second embodiment;

FIG. 8 is a block diagram showing the details of the optical interface unit of FIG. 7;

FIG. 9 is a block diagram showing a third embodiment;

FIG. 10 is a block diagram showing the details of the optical interface unit of FIG. 9;

FIG. 11 is a block diagram showing a fourth embodiment;

FIG. 12 is an explanatory diagram showing an operation of the memory system according to the fourth embodiment;

FIG. 13 is an explanatory diagram showing an operation of the memory system according to the fifth embodiment;

FIG. 14 is a block diagram showing a sixth embodiment;

FIG. 15 is a block diagram showing a seventh embodiment;

FIG. 16 is a block diagram showing a eighth embodiment; and

FIG. 17 is a block diagram showing a ninth embodiment.

Claims

1. A memory system comprising: a memory device which includes a memory unit storing data; a controller which accesses said memory unit; and an optical transmission line which is provided between said memory unit and said controller, wherein said controller comprises:a first serial converting unit which converts a parallel command signal, address signal, and write signal into a first serial signal in order to read/write data from/to said memory unit;a first optical converting unit which outputs to said memory device said first serial signal as a first optical signal with a single wavelength via said optical transmission line; anda first parallel converting unit which converts a second optical signal supplied from said memory device into a parallel read data signal, andsaid memory device comprises:a second parallel converting unit which converts said first optical signal into the original parallel command signal, address signal, and write data signal and outputs the converted parallel signals to said memory unit;a second serial converting unit which converts a parallel read data signal from said memory unit into a second serial signal; anda second optical converting unit which outputs to said controller said second serial signal as said second optical signal with a single wavelength via said optical transmission line.

2. The memory system according to claim 1, wherein: before starting reading/writing data from/to said memory unit, said controller outputs, as said first optical signal, to said memory device, a first synchronous clock to synchronize an operation of said memory device with an operation of said controller;said memory device generates a second synchronous clock synchronized with said first synchronous clock and outputs the generated second synchronous clock as said second optical signal; andsaid controller starts reading/writing data from/to said memory unit in response to reception of said second synchronous clock.

3. The memory system according to claim 2, wherein: said memory unit has plural operation modes; andin response to the reception of said second synchronous clock, said controller further outputs as said first optical signal a command signal to set an operation mode of said memory unit to any one of said operation modes, outputs as said first optical signal a command signal to read the operation mode set in said memory unit, and starts reading/writing data from/to said memory unit when said second optical signal outputted from said memory device indicates a correct operation mode.

4. The memory system according to claim 3, wherein when said second optical signal outputted from said memory device indicates an incorrect operation mode, said controller outputs again said first synchronous clock as said first optical signal to synchronize the operation of said memory device without starting reading/writing data from/to said memory unit.

5. The memory system according to claim 2, wherein: said controller outputs said first synchronous clock to said memory device at predetermined intervals even after starting reading/writing data from/to said memory unit; andsaid memory device outputs said read data signal as said second optical signal to said controller during a period which does not overlap with a period in which said first synchronous clock is output.

6. The memory system according to claim 1, wherein said optical transmission line is composed of a single optical transmission line through which said command signal, said address signal, said write data signal, and said read data signal are transmitted as said first and second optical signals.

7. The memory system according to claim 1, wherein said optical transmission line is composed of a first optical transmission line through which said command signal and said address signal are transmitted as said first optical signal and of a second optical transmission line through which said write data signal and said read data signal are transmitted as said first and second optical signals.

8. The memory system according to claim 1, wherein said optical transmission line is composed of a first optical transmission line through which said command signal, said address signal, said write data signal, and part of said read data signal are transmitted as said first and second optical signals and of a second optical transmission line through which remainder of said read data signal is transmitted as said second optical signal.

9. The memory system according to claim 1, wherein: said memory device comprises plural kinds of memory units;said controller outputs a device signal to said memory device as said first optical signal together with said parallel command signal, address signal and write data signal, the device signal indicating a memory unit to be accessed; andsaid memory device outputs a device signal to said controller as said second optical signal together with said read data signal, the device signal indicating an accessed memory unit.

10. The memory system according to claim 9, wherein said controller outputs an order signal to said memory device as said first optical signal together with said parallel command signal, address signal and write data signal, the order signal indicating an order in which memory units are accessed; andsaid memory device outputs said order signal to said controller as said second optical signal together with said read data signal.

11. The memory system according to claim 9, wherein said optical transmission line is composed of a single optical transmission line through which said command signal, said address signal, said write data signal, and said read data signal are transmitted as said first and second optical signals.

12. The memory system according to claim 9, wherein said optical transmission line is composed of a first optical transmission line through which said command signal and said address signal are transmitted as said first optical signal and of a second optical transmission line through which said write data signal and said read data signal are transmitted as said first and second optical signals.

13. The memory system according to claim 9, wherein said optical transmission line is composed of a first optical transmission line through which said command signal, said address signal, said write data signal, and part of said read data signal are transmitted as said first and second optical signals and of a second optical transmission line through which remainder of said read data signal is transmitted as said second optical signal.

14. The memory system according to claim 9, wherein said optical transmission line includes an optical transmission line dedicated for each of said memory units.