Patent Application
20050055495
This invention generally relates to a memory wear leveling and more specifically to reducing wearing of hotspots (memory blocks used more frequently) by rotating the memory blocks on the physical level based on predetermined criteria using at least one spare memory block.
Conventional memories (e.g. flash memories) deteriorate somewhat on each write operation (destructive write). This may cause problems if certain memory areas are written more often than other areas. This problem can be solved by maintaining registers that count the number of write operations performed for each memory block. The least used block is then selected as the next block to be used when data is written (so called “wear leveling”). Solutions for wear levelling are used, for example, in flash memories. These implementations typically use tables to store usage of given sectors. Typically, there are some spare blocks, which can be taken into use, and old blocks (memory blocks that have been written too many times) can be removed from use (i.e. marked as “not in use”) as they wear out. An example of such wear management approach for the write operation during memory usage can be found in U.S. Pat. No. 6,405,323, “Defect Management for Interface to Electrically-Erasable Programmable Read-Only Memory”, by F. F-L. Lin et al.; U.S. Pat. No. 5,568,423, “Flash Memory Wear Leveling System Providing Immediate Direct Access to Microprocessor”, by E. Jou, et al.; and U.S. Pat. No. 6,230,233, “Wear Leveling Techniques for Flash EEPROM Systems”, by K. M. J. Lufgren et al. Cache routines can also be used to solve this problem as described in US Patent Application No. 20010002475 “Memory Device” by L. I. Bothwell et al. Although technologies with destructive writes can be handled relatively easily with existing wear leveling algorithms, the same methods cannot be used for technologies with destructive reads discussed below.
Ferro-electric memories (FeRAM) are based on various ferroelectric compounds, e.g. a Perovskite compound Pb(Zr,Ti)O3 (PZT). The ability of a ferroelectric crystal to switch between its polarization states and to make a small area of reversed domains with fast switching has made ferroelectrics attractive for high capacity nonvolatile memories and data storage. The information can be written and read very fast requiring very little power; however, it has a limited life and suffers from a destructive read because of a fatigue factor, which is a degradation of the polarization hysteresis characteristic with increasing number of cycles. This is the most serious problem of ferroelectric memory devices in non-volatile memory applications. From a practical point of view, a lifetime (that is, the time until the polarization degradation is observed) of well over 1015 cycles is required which cannot be met by the current state-of-the-art ferroelectric memory technologies. The wear-leveling problem is thus expanded to read operations as well. The destructive read characteristic is a problem especially in hotspots. A hotspot is a memory block that is accessed significantly more often than memory blocks that are accessed on average. These hotspots are a problem when the memory read and/or write endurance is limited, which is the case with most solid-state nonvolatile memories.
There are several approaches to solving this problem for the read operation during memory usage. US Patent Application No. 20030058681, “Mechanism for Efficient Wearout Counters in Destructive Readout Memory”, by R. L. Coulson, published Mar. 27, 2003, presents a method utilizing wearout counters somewhat similar to those used in conventional memories for the write operation. US Patent Application No. 20010054165, “Memory Device Having Redundant Cells”, by C. Ono, published Dec. 20, 2001, describes a method utilizing redundant memory blocks as spare blocks for blocks that wear out. All of these methods require counting of access activities which increases overall complexity and overhead. EP Patent No. 0741388, “Ferro-Electric Memory Array Architecture and Method for Forming the Same”, by J-D. D. Tai, published Nov. 6, 1996, discloses an architecture that reduces the number of memory cells being accessed in a read operation.
The object of the present invention is to provide a memory wear leveling methodology for reducing wearing of hotspots, i.e., frequently used memory blocks, in all memory types.
The hotspots are “smoothed out” by rotating the memory blocks on the physical level with the help of a spare memory block. This simple principle is illustrated by the example below, wherein 1,2,3,4 . . . represent memory blocks and s represents the spare block. Then during each read operation the spare block switches places with the neighboring memory block as follows:
More generally, according to a first aspect of the present invention, a method for wear leveling of a multi-block memory containing data, usable in multi-block memory activities, comprises the steps of: detecting an at least one triggering signal; and copying or relocating the data of an at least one first memory block containing an at least one memory element of the multi-block memory to an at least one second memory block of the multi-block memory after detecting the at least one triggering signal, wherein said at least one second memory block does not contain said data before said copying or relocating. Further, each of the at least one first memory block and the at least one second memory block may contain only one memory element. Still further, there may be more than one memory element contained in the at least one first memory block and there may be more than one memory element contained in the at least one second memory block, respectively.
In further accord with the first aspect of the invention, the method may further comprise the step of updating a first memory pointer originally pointed to the at least one second memory block before said copying or relocating to point to the at least one first memory block after said copying or relocating. Still further, the method may further comprise the step updating a second memory pointer by shifting it back to a physical zero point by reducing the value of the second memory pointer by a number of relocated memory elements of the second memory block if the first memory pointer is pointing to one of the memory elements of the at least one second memory block after said updating.
Still further according to the first aspect of the invention, the data of an at least one additional block of the multi-block memory may be relocated to an at least one further additional block of the multi-block memory after detecting the at least one triggering signal, wherein said at least one further additional block does not contain the data before said relocation.
Further still according to the first aspect of the invention, said copying or relocating may be performed according to predetermined criteria. Further, said predetermined criteria may enable said copying or relocating of a regular pattern such that after a predetermined number of triggering signals copying or relocating steps are identical. Still further, said predetermined criteria may enable said copying or relocating of a random pattern such that after any number of triggering signals, copying or relocating steps are not necessarily identical.
In further accordance with the first aspect of the invention, said copying or relocating of the data may occur only after detecting a predetermined number of the at least one triggering signal.
Yet further still according to the first aspect of the invention, the at least one triggering signal may correspond to a read operation, to a write operation, to a time clock pulse or to the detection of a predetermined number of read/write operations or clock pulses.
According further to the first aspect of the invention, said copying or relocating of the data may occur a predetermined number of times between the triggering signals According still further to the first aspect of the invention, the method may further comprise the step of counting the usage of the individual memory blocks of the multi-block memory, wherein said copying or relocating is performed according to predetermined criteria, said predetermined criteria includes considerations for said counting.
According further still to the first aspect of the invention, all the data contained in the multi-block memory may be copied or relocated at the same time.
Yet still further according to the first aspect of the invention, the method may further comprise the step of updating a variable logical address X after said copying or relocating in the multi-block memory containing C memory elements, said variable logical address X for said C memory elements identified by pointers X0, X1 . . . Xk, Xk+1 . . . XC−1 is updated to an updated variable logical address Xu for C-S memory elements identified by the pointers X0, X1 . . . Xk−1, Xk+S . . . XC−1, wherein C is a total number of the memory elements of the multi-element memory, S is a number of the memory elements identified by the pointers Xk, Xk+1, Xk+S−1 in a spare memory block after said copying or relocating, wherein a first element of said first memory block after said copying or relocating corresponds to a first element identified by the pointer Xk of the spare memory spare block after said copying or relocating.
According to a second aspect of the invention, an electronic device, comprises: a multi-block memory containing data, usable in multi-block memory activities; a memory wear controller, responsive to a triggering signal or to a further triggering signal, for providing a data-relocation signal to the multi-block memory to relocate the data from an at least one first memory block containing an at least one memory element of the multi-block memory to an at least one second memory block of the multi-block memory wherein said at least one second memory block does not contain said data before said copying or relocating, and for providing an update signal after performing said copying or relocating; and a memory pointer controller, responsive to the update signal. Further, each of the at least one first memory block and the at least one second memory block may contain only one memory element. Still further, there may be more than one memory element contained in the at least one first memory block and there may be more than one memory element contained in the at least one second memory block, respectively.
According further to the second aspect of the invention, the memory pointer controller may provide a pointer signal to the memory wear controller based on predetermined criteria. Further, the memory pointer signal may contain a physical address in the multi-block memory to be accessed for enabling an at least one further data relocation of the data located at the physical address and optionally an address of a first memory pointer.
Further according to the second aspect of the invention, the memory pointer controller may provide updating of at least one memory pointer pointing to said first memory block before said copying or relocating to point to said second memory block after said copying or relocating.
Further still according to the second aspect of the invention, the memory wear controller and the memory pointer controller may be implemented as software, hardware, or a combination of software and hardware components. Further, the hardware may be implemented using a finite state machine.
In further accord with the second aspect of the invention, said copying or relocating of the data from the at least one first memory block and updating the location of the memory pointers may be performed according to predetermined criteria.
Further still according to the second aspect of the invention, the electronic device may further comprise a triggering detector, responsive to the triggering signal, for providing a further triggering signal upon detecting the triggering signal.
In further accordance with the second aspect of the invention, the electronic device may further comprise of a triggering detector, responsive to the triggering signal, for providing a further triggering signal upon detecting the triggering signal.
According to a third aspect of the invention, an electronic device comprises: means for containing data in multiple memory blocks, wherein said data is usable in activities of the means for containing data; means for providing a data-relocation signal to the means for containing the data for copying or relocating the data from an at least one first memory block containing an at least one memory element of the means for containing the data to an at least one second memory block of the means for containing the data in response to a triggering signal, wherein said at least one second memory block does not contain said data before said copying or relocating, and for providing an update signal on a status of the means for containing the data after performing said copying or relocating; and means for providing to the means for providing the data-relocation signal, in response to the update signal, a pointer signal containing a physical address pointer in means for containing data to be accessed for enabling an at least one further data relocation of the data located at the physical address and optionally an address of a first memory pointer. Further, the means for providing to the means providing the data-relocation signal may further provide updating of at least one memory pointer pointing to said first memory block before said copying or relocating to point to said second memory block after said copying or relocating.
According to a fourth aspect of the invention, a method for wear leveling of a multi-block memory containing data, usable in multi-block memory activities, comprises copying or relocating the data from an at least one first block containing an at least one memory element of the multi-block memory to an at least one second block containing an at least one memory element of the multi-block memory after detecting a triggering signal related to said data, wherein said at least one second block does not contain said data before said copying or relocating. Further, an at least one memory pointer pointing to said first memory block before said copying or relocating may be updated to point to said second memory block after said copying or relocating.
For a better understanding of the nature and objects of the present invention, reference is made to the following detailed description taken in conjunction with the following drawings, in which:
a, 1b, 1c, and 1d together illustrate the concept of a multi-block memory wear leveling, according to the present invention.
a, 2b and 2c together further illustrate the concept of a multi-block memory wear leveling comparing an actual memory space with a memory space seen by a user, according to the present invention.
a shows a flow chart for general implementation of a memory wear leveling, according to the present invention.
b shows a flow chart of simplified Y-implementation procedure for general implementation of a memory wear leveling of
To assist in clarifying the technical subject matter of this invention, a few symbols are defined in Table 1 and further described in the text.
This invention describes a memory wear leveling for reducing wearing of hotspots (memory blocks used more frequently) in all memory types by rotating the memory blocks on the physical level with the help of at least one spare memory block using predetermined criteria during or after read and/or write operations. The hotspots are smoothed out by this rotation. The present invention uses a blind approach in which no information about the actual memory usage is needed. The invention can be implemented, for example, by using constant memory pointers at a logical level and dynamic memory pointers on the physical level. The rotation can be implemented as a combination of software and hardware functionalities. For example, the physical rotation can be handled independently by a memory management hardware module, whereas logical and physical addresses are associated by a software method that calculates the physical address on the basis of the logical address and memory parameters. Another implementation alternative is using hardware for both memory rotation and address management. In this case, the hardware maintains the correct associations between the logical and physical addresses.
The advantages of the present invention are simplicity and a smaller overhead (i.e. memory reserved for memory management). Using counter registers as in conventional solutions for the write operation will result in a more complex memory management scheme than the present invention.
a through 1d together show an example illustrating the concept of a multi-block memory 10 wear leveling, according to the present invention. A linear combination of memory blocks is chosen in
a shows the initial state of a memory array 10 shown as the linear combination of the memory blocks including, for example, a block 18, wherein C is the total size (a total number of the memory elements) of the multi-block memory 10, M is a spare block address/pointer or a first memory pointer which typically points at the first element of the spare memory block 18 (or the spare block 18), S is a number of memory elements in the spare memory block 18, Z0 is a physical zero address/pointer, and Z is a logical zero address/pointer or a second memory pointer. A typical memory element has 16 bits or 2 bytes of information, but it can also be a memory cell or an array of memory cells or any other entity capable of containing at least one bit of data. Any memory block of the multi-element memory 10 (including the spare block 18) can contain one or more such memory elements. The physical zero address/pointer Z0 points to the first available element of the memory 10 in a preferred embodiment (and is therefore by definition equivalent to zero), and it does not change in time. This gives the memory 10 a convenient common reference point independently of the state of rotation.
For the example of
b shows shifting of a first memory block 17 (or block 17) indicated at its start at the first element by a variable physical address/pointer Y to the spare block 18 (or the second memory block 18). Apparently, the blocks 17 and 18 have the same number of memory elements. A variable physical address/pointer Y is determined using a variable logical address X based on the predetermined criteria. According to one embodiment of the present invention, after each data relocation, the variable logical address X is altered by the amount equal to S or a multiple of S. For the presented example, a logical-to-physical memory mapping is given by a relationship Y=Z0+(Z+X)modC. Since Z0=0 and if the first value of X=0, then Y=Z0+Z=Z, which is shown in
c illustrates updating the first and second memory pointers M and Z, respectively, after the block 17 is relocated to the spare block 18 in
The same procedure described in
a, 2b and 2c together further illustrate the concept of a multi-block memory wear leveling comparing an actual memory space with a memory space seen by a user and a virtual actual memory space, according to the present invention.
X=U if k<M, (1)
X=S+U if k≧M. (2)
The above relationship is important for establishing connection between memory spaces 10 and 10u and for the practical implementation of the present invention. This concept is further developed in
As shown in
In general, the memory wear controller 22 provides a data-relocation signal 30 to the multi-block memory 10 in response to the further triggering signal 26a, which corresponds to the triggering signal 26 or it can respond directly to the triggering signal 26 if the triggering detector 20 is not used. However, according to the present invention, there are many variations. For example, the data-relocation signal 30 can be sent only after detecting a predetermined number (e.g., more than one) of the triggering signals 26 or the further triggering signal 26a. Alternatively, the data-relocation signal 30 can be sent a predetermined number of times between the triggering signals 26 or the further triggering signal 26a. It is also possible that the triggering signal 26 is only conveyed to the triggering detector 20 and not to the multi-element memory 10.
The memory pointer controller 24, in response to the update signal 32, provides a pointer signal 34 to the memory wear controller 22. Said pointer signal 34 contains a physical addresses Y and optionally M in the multi-block memory 10 based on the predetermined criteria to be accessed for enabling at least one further data relocation of the data located at the physical address Y as described in the example of
The predetermined criteria which enables a relocation of data as disclosed in the present invention can have many variations. For example, said relocation can have a regular pattern, such that after a predetermined number of triggering signals 26, relocation steps are identical. Said relocation, according to the predetermined criteria, can also have a random pattern, such that after any number of triggering signals 26, relocation steps are not necessarily identical. Furthermore, the method of the memory wear leveling described in the present invention can be used in combination with conventional methods involving counting the usage of individual memory blocks of the multi-block memory 10 such that said predetermined criteria incorporates the counting information.
The triggering detector 20, the memory wear controller 22, and the memory pointer controller 24 of the system 11 shown in
a shows a flow chart, as one example among many others, for a general implementation example of a memory wear leveling, according to the present invention. In a method according to the present invention, in a first step 40, the initial values of parameters are set in the memory pointer controller 24. For example, the following initial parameters are set for this example: Zo=0, X=0, M=Z−S, (C-S)mod C=0. In a next step 42, the triggering signal 26 is detected by the triggering detector 42. Step 42 implies sending signals 28, 30 and 32 as shown in
In a next step 44, it is ascertained whether the current value of X is pointing at a memory element within the spare block 18. If that is the case, in a next step 46, the value of X is increased by S and the process proceeds to step 48. If, however, the current value of X is not within the spare block, the process proceeds directly to step 48, wherein the value T=X+Z is calculated. A determination of the current value of Y according to the predetermined criteria is performed using Y-determination procedure 47. There are many ways to make this estimation. One general scenario, among many other possibilities, consists of steps 50 through 50g as shown in
Steps 50a, 50d, 50e and 50g are followed by a next step 52, in which a block Y:Y+S (e.g., block 17 in
b shows a flow chart of a simplified Y-determination procedure 47a for the general implementation of the memory wear leveling of
The m′×n′ logical memory array 10a refers to an idealized logical structure and not necessarily to the actual physical implementation, which is likely to be composed of several subarrays and may not include the actual spare block at all; the spare block can be also located in a register, external to the actual memory array 10a. In the current example of the m′×n′ logical memory array 10a the spare block is naturally included. The size of the logical array equals C=m′×n′ as in
Relocation (e.g. step 52 in
The FSM 15, as mentioned earlier, essentially incorporates major functional blocks 20, 22 and 24 of
The normal function of the timing and R/W controller 17 is performed by a regular R/W controller 17a with an input signal, a normal memory signal 17b, which depends on the memory type (e.g., clock signal), and an output signal, a normal R/W command signal 17c to the R/W logic means 10c, which facilitates the normal R/W operations of the memory 10. The signal 17b (e.g. a clock signal) can also serve as the triggering signal 26 as discussed earlier in regard to
The memory pointer controller 24 effectively includes the logic and data structures needed to maintain status of the state of memory rotation and to hold the data needed for address mapping of external logic addresses to actual memory array addresses where the data requested currently resides. In particular, Y and pointer update determination means 24a, based on the updated signal form the memory wear controller 22, calculates and provides (pointer signal 34) to the timing and R/W controller 17 the physical address Y (and optionally M, if required, depending on the implementation as discussed earlier) to be accessed for enabling an at least one further data relocation of the data located at the physical address Y of the array 10a to the spare block with the address M as discussed above. After each memory relocation, means 24a updates the spare block location M in a spare block address register 24b.
The spare block address information from the spare block address register 24b is used by a m′×n′ address mapping counter 24c to map the correct location of the memory elements accessed by the user, who sends the address signal 24d as a part of the normal memory operation. This mapping procedures is described in details in
It should be noted that the HW implementation is strongly dependent on the type of memory device and can be implemented using other electronic devices operating with the same fundamental logical principle but differing in details determined by the specific memory technology. For sector addressed memories like NAND Flash, the implementation would be quite different, and a pure HW solution is probably not the preferred way. Also, if the memory cell can withstand a relatively small amount of reads or writes or erases, thousands or millions, the present invention can be used with care because of the wear overhead that every cell experiences. The HW implementation is more useful if the memory can withstand several billions or more accesses/cell, because then the “hot-spot leveling” effect is dominating over the wear overhead. This makes it appealing especially to the new NVRAM type memories like FeRAM, Ovonics Unified Memory, etc. and especially read destructive wearing memories (again FeRAM).
