Patent Application
20250063713
This application claims priority to Chinese Patent Application No. 202311022435.1, filed on Aug. 14, 2023, the entire content of which is incorporated herein in its entirety by reference.
The present disclosure relates to a field of semiconductor device, in particular to a memory with a three-dimensional vertical structure and a method of manufacturing a memory with a three-dimensional vertical structure.
A traditional DRAM (Dynamic Random Access Memory) cell is formed by one transistor and one capacitor. However, with the increase of integration, the capacitive structure continues to shrink, the charge storage capacity continues to decrease, the leakage is too fast, and DRAM is about to reach the refresh frequency limit. In recent years, a 2TOC (2 Transistor 0 Capacitor, dual-transistor capacitor-free) DRAM cell based on two oxide semiconductor IGZO thin film transistors has appeared. As shown in
On a first aspect of the present disclosure, a memory with a three-dimensional vertical structure is provided, including a semiconductor substrate, a first isolation layer, a first transistor and a second transistor stacked in sequence from bottom to top;
Furthermore, a dielectric material is same as a material of the first gate dielectric layer.
Furthermore, the memory with the three-dimensional vertical structure further includes: a first contact plug electrically interconnected to the first source layer, a second contact plug electrically interconnected to the first drain layer, a third contact plug electrically interconnected to the second source layer, and a fourth contact plug electrically interconnected to the second gate layer.
Furthermore, the first contact plug, the second contact plug, the third contact plug and the fourth contact plug are distributed in a stepped shape.
Furthermore, the first active layer and the second active layer are made of indium gallium zinc oxide.
On a second aspect of the present disclosure, a method of manufacturing a memory with a three-dimensional vertical structure is provided, including:
Furthermore, the method further includes: after forming the second gate layer,
Furthermore, the method further includes:
Furthermore, the first active layer and the second active layer are made of indium gallium zinc oxide.
Furthermore, the method further includes: before forming a sixth isolation layer and after forming the second gate layer, performing a surface planarization process.
Various other advantages and benefits will become clear to those ordinary skilled in the art by reading the following detailed description of preferred embodiments. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not considered as a limitation of the present disclosure.
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are just exemplary and not intended to limit the scope of the present disclosure. In addition, in the following explanations, descriptions of well-known structures and technologies are omitted to avoid unnecessary obscuring the concepts of the present disclosure.
Various structural diagrams according to the embodiments of the present disclosure are shown in the accompanying drawings. These diagrams are not drawn to scale, in which some details may be enlarged and some details may be omitted for clarity of presentation. Shapes of various regions and layers as well as relative sizes and positional relationships thereof shown in the diagrams are just exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations. Moreover, those skilled in the art may additionally design regions/layers with different shapes, sizes and relative positions according to actual needs.
In the context of the present disclosure, when a layer/element is referred to as being located “on” a further layer/element, the layer/element may be located directly on the further layer/element, or there may be an intermediate layer/element between them. In addition, if a layer/element is located “on” a further layer/element in an orientation, the layer/element may be located “below” the further layer/element when the orientation is reversed.
In the 2T0C DRAM cell in the related art, two TFTs with horizontal channels are connected on a same plane, which occupies a large area and is not conducive to improving the integration density.
A main purpose of the present disclosure is to provide a memory with a three-dimensional vertical structure and a method of manufacturing a memory with a three-dimensional vertical structure. In this structure, an upper transistor vertically overlaps with a lower transistor, which saves the cell area, improves the integration density and reduces the manufacturing costs.
The present disclosure provides a capacitor-free DRAM cell structure based on a thin film transistor, as shown in
A substrate 101 may be any substrate known to those skilled in the art for carrying elements of a semiconductor integrated circuit, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator. A corresponding top layer semiconductor material is silicon, germanium, silicon germanium, or gallium arsenide.
An isolation layer 102 is formed on the substrate 101. The isolation layer 102 may be made of a material with high k dielectric such as oxide, oxynitride, etc., for example, typical silicon oxide (SiO2), silicon oxynitride, silicon nitride (SiNx), and the like.
Taking the isolation layer 102 as a boundary, a first transistor is located above the isolation layer 102. The first transistor is vertically stacked and achieves a function of a reading transistor. The first transistor includes a first source layer 103, a second isolation layer 104, a first drain layer 105 and a third isolation layer 106 stacked in sequence from bottom to top and a first through hole. The first through hole penetrates the third isolation layer 106, the first drain layer 105 and the second isolation layer 104 in sequence and stops at the first source layer 103. A first active layer 107, a first gate dielectric layer 108 and a first gate layer 109 are stacked in sequence on an inner sidewall of the first through hole.
The structure of the first through hole determines that each of the first active layer 107 and the first gate dielectric layer 108 is in a ring shape, and a cavity surrounded by the first active layer 107 and the first gate dielectric layer 108 is filled with the first gate layer 109. The first gate layer 109 in the first transistor is also a drain of the second transistor above the first transistor, that is, the first transistor and the second transistor share one electrode.
The second transistor is vertically stacked and achieves a writing function. The second transistor includes a fourth isolation layer 110, a second source layer 111, and a fifth isolation layer stacked in sequence from bottom to top and a second through hole. The second through hole penetrates the fifth isolation layer, the second source layer 111 and the fourth isolation layer 110 in sequence and stops at the first gate layer 109. A second active layer 113, a second gate dielectric layer 114 and a second gate layer 115 are stacked in sequence on an inner sidewall of the second through hole. The structure of the second through hole determines that each of the second active layer 113 and the second gate dielectric layer 114 is in a ring shape, and a cavity surrounded by the second active layer 113 and the second gate dielectric layer 114 is filled with the second gate layer 115.
It may be seen that each of the first transistor and the second transistor is in a vertical stack form, and a bit line, a word line, a gate and a channel in each transistor are vertically stacked and surrounded connected. The above plurality of three-dimensional stacks greatly reduce the cell area and increase the integration density.
Compared with other vertically stacked 2T0C DRAMs, the memory structure shown in
Furthermore, in order to prevent an electrical interconnection between the active layer of the first transistor and the active layer of the second transistor as well as reduce a difficulty of the manufacturing process, the first through hole and the second through hole are designed with different sizes. Specifically, a projection of the second through hole on the first isolation layer is surrounded by a projection of the first through hole on the first isolation layer. This size differentiation design may adapt to more processes and methods. For example, a planarization process may be performed after forming the first gate layer, in this case, the planarization process may stop at the third isolation layer 106 or at the first gate dielectric layer 108. However, since a film thickness of each of the gate dielectric and the gate is small, and an etching selectivity ratio is not significantly large, it is difficult to control the etching stopping. If the structure of the present disclosure is adopted, it is not required to deliberately control an etching stopping point. In the present disclosure, “surrounded by” does not include a case where the projection of the second through hole on the first isolation layer overlap with the projection of the first through hole on the first isolation layer. In the present disclosure, an area of the projection of the first through hole on the first isolation layer is large, while an area of the projection of the second through hole on the first isolation layer is small. That is, an outer contour of the projection of the second through hole is entirely located inside an outer contour of the projection of the first through hole.
A dielectric material with a large area may be deposited above the second transistor, which plays a role of filling and isolating. At the same time, in order to lead out each electrode, the memory with the three-dimensional vertical structure further includes a first contact plug 116 electrically interconnected to the first source layer 103, a second contact plug 117 electrically interconnected to the first drain layer 105, a third contact plug 118 electrically interconnected to the second source layer 111, and a fourth contact plug 119 electrically interconnected to the second gate layer 115. These contact plugs may be distributed in a stepped shape, so as to reduce the short circuit effect and reduce the difficulty of implementing the process.
An operation circuit of the capacitor-free memory structure described in the present disclosure is shown in
During a process of writing “1”, a positive voltage (greater than a threshold voltage Vth) is applied to a writing word line WWL, so that the writing transistor is turned on. A positive voltage is applied to a source (i.e. a writing bit line WBL) of the writing transistor to inject charges into the gate capacitance (i.e. the storage node) of the reading transistor. After injecting the charges, a gate voltage and a source voltage of the writing transistor are removed, and a “1” state is saved.
During a process of reading “1”, a reading voltage is applied to a drain of the reading transistor. Since certain charges are stored in the gate capacitance, the reading transistor is in a lower resistance state, obtaining a larger current. After being amplified and recognized by a peripheral circuit, the process of reading “1” is completed.
During a process of writing “0”, a positive voltage (greater than the threshold voltage Vth) is applied to the gate (i.e. the writing word line WWL) of the reading transistor, so that the writing transistor is turned on. A negative voltage is applied to the source (i.e. the writing bit line WBL) of the writing transistor to extract charges from the gate capacitance (i.e. the storage node) of the reading transistor. After extracting the charges, the gate voltage and the source voltage of the writing transistor are removed, and a “0” state is saved.
During a process of reading “0”, a reading voltage is applied to the drain (RBL) of the reading transistor. Since there is no charge in the gate capacitance, the reading transistor is in a higher resistance state, obtaining a smaller current. After being amplified and recognized by the peripheral circuit, the process of reading “0” is completed.
In terms of selecting materials for the above memory structure, each layer may be made of any material that achieves a corresponding basic function. However, in order to further improve the electrical performance and usage effectiveness of the memory, each layer has a preferred material.
For example, the first active layer 107 and the second active layer 113 are used as channels. Each of the first active layer 107 and the second active layer 113 may be independently made of at least one of In2O3, ZnO, or IGZO (indium gallium zinc oxide). Since an off-state leakage of the IGZO thin film transistor is very low, information of the storage node may be maintained for a long time.
Each of the first gate dielectric layer 108 and the second gate dielectric layer 114 plays a role of insulating between the gate and the channel. Preferably, a material with a wide bandgap and a high dielectric constant, or a material suitable for manufacturing devices with extremely small sizes, such as at least one of SiO2, HfO2, or Al2O3, may be selected for each of the first gate dielectric layer 108 and the second gate dielectric layer 114.
The first source layer 103, the first drain layer 105, the first gate layer 109, the second source layer 111 and the second gate layer 115 are used as electrodes to be connected to the power supply. Preferably, each of the first source layer 103, the first drain layer 105, the first gate layer 109, the second source layer 111 and the second gate layer 115 may be made of a metal material or a doped semiconductor material with good conductivity, including but not limited to at least one of Mo, TiN, Ti, Al, W, indium tin oxide or indium zinc oxide. In addition, considering the fast and stable current transmission between the electrodes, the first source layer 103, the first drain layer 105, the first gate layer 109, the second source layer 111 and the second gate layer 115 are preferably made of the same material or materials with similar properties.
Each of the first isolation layer 102, the second isolation layer 104, the third isolation layer 106, the fourth isolation layer 110 and the fifth isolation layer may be made of a material with high k dielectric such as oxide, oxynitride, etc., for example, typical silicon oxide (SiO2), silicon oxynitride, silicon nitride (SiNx), and the like.
Therefore, in the present disclosure, a gate of the first transistor and a drain of the second transistor are a same electrode, that is, the first transistor and the second transistor share one electrode, achieving an integration method of dual-transistor capacitor-free. Moreover, the first transistor and the second transistor are stacked vertically, which saves a larger cell area and has a higher integration density compared with the planar stack.
In addition, the first through hole is larger than the second through hole, that is, the projection of the second through hole is surrounded by the projection of the first through hole. Therefore, with the formation of the fourth isolation layer, the second active layer on the sidewall is inevitably insulated and isolated from the first active layer, without the requirements for additional insulation material deposition or control of etching stopping position, thereby reducing the process difficulty.
The present disclosure further provides a method of manufacturing the above-mentioned memory, which has a simple process and good compatibility with related 3D semiconductor device manufacturing processes. In combination with
Firstly, a first isolation layer 102, a first source layer 103, a second isolation layer 104, a first drain layer 105 and a third isolation layer 106 are formed on a surface of a semiconductor substrate 101, as shown in
Next, a first through hole structure is formed by patterning and etching, so as to expose the first source layer 103. A sidewall of the through hole may be maintained to be vertical, as shown in
Afterwards, a first active layer 107 is deposited in the first through hole, as shown in
A first gate dielectric layer 108 and a first gate layer are deposited in sequence. Planarization is performed on the first through hole structure and stopped at the third isolation layer 106.
Next, a fourth isolation layer 110, a second source layer 111 and a fifth isolation layer are deposited, as shown in
A second through hole structure is formed by patterning and etching, so as to expose the first gate layer 109, as shown in
A second active layer 113, a second gate dielectric layer 114, and a second gate layer 115 are deposited in sequence, and planarization is performed on the second through hole, as shown in
Afterwards, a sixth isolation layer 120 is deposited, as shown in
A trench structure is formed through a patterning process, so as to isolate source/drain layers and divide the memory structure into array cells, as shown in
The isolation trench is filled with a dielectric to form an isolation structure 121, and a planarization process is performed, as shown in
Finally, contact holes connected to respective electrodes, including a first contact hole penetrating to the first source layer 103, a second contact hole penetrating to the first drain layer 105, a third contact hole penetrating to the second source layer 111 and a fourth contact hole penetrating to the second gate layer 115, are formed through an etching process. The above contact holes are distributed in a stepped shape, as shown in
Each contact hole described above is filled with a conductive material to form a first contact plug 116, a second contact plug 117, a third contact plug 118 and a fourth contact plug 119, so as to complete the interconnection process, as shown in
Therefore, in the present disclosure, by using a difference between a size of the first through hole and a size of the second through hole, the upper and lower transistors with the same size share one electrode and the interconnection between the active layers of the upper and lower transistors is avoided. The active layer of the upper transistor is isolated from the active layer of the lower transistor by the fourth isolation layer.
Compared with the related art, the present disclosure achieves the following technical effects:
In the memory structure of the present disclosure, the upper transistor vertically overlaps with the lower transistor, which saves the cell area, improves the integration density and reduces the manufacturing costs. Furthermore, the process difficulty is reduced by using the difference between the size of the through hole in the upper transistor and the size of the through hole in the lower transistor.
The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311022435.1 | Aug 2023 | CN | national |
