Patent Application
20240048478
This application claims a priority to Chinese Patent Application No. 202011321949.3 filed in China on Nov. 23, 2020, the disclosures of which are incorporated in their entirety by reference herein.
The present disclosure relates to the technical field of communications, and in particular, to a message forwarding method, a message forwarding apparatus, a communication device, and a readable storage medium.
Segment Routing (SR) is a source routing technology, forms a path-oriented network architecture based on a Software Defined Network (SDN) concept, supports multi-level programmable requirements of a future network, and can meet connection requirements in an application scenario of a 5th generation (5G) ultra-large connection and a slice. SR-Multi-Protocol Label Switching (MPLS) is an SR solution formed based on a current mainstream MPLS forwarding plane. SRv6 is an SR solution extended based on an Internet Protocol Version 6 (IPv6). IPv6 is a subject technology of a new generation of networks, long-term consideration of SRv6 based on the IPv6 is an evolution trend of future networks, and a mechanism research on SRv6 technology is an industry hotspot.
A 128-bit segment identifier (SID) of a standard SRv6 uses an SID in an IPv6 address format, and compared with an SID in an MPLS label format, the SID in the IPv6 address format has a routing attribute, simplifies inter-domain path creation, and simplifies capability of establishing an end-to-end path in an IPv6 network. Meanwhile, the SRv6 SID supports programmable capability, can meet flexible network and service function processing, combines a cooperative support of a centralized control plane and a distributed control plane, can flexibly meet requirements of various services and network functions, and adapts to requirements of network and service development.
The SR encapsulates a series of instructions through a head node to guide a packet to pass through the network, and in a SRv6 architecture, one instruction is a 128-bit IPv6 address, as shown in
It can be seen from the encapsulation format of the SRv6 extension header that an encapsulation length of the SRv6 extension header is 40 Bytes (IPv6 header)+8 Bytes (Segment Routing Header, SRH)+16×N Byte (Segment List). Therefore, as the number of SIDs specified by the SRv6 increases, an additional overhead brought by the SRv6 extension header encapsulation becomes larger. In order to solve this problem, a function of shortening the SRv6 extension header needs to be realized.
Although the standard SRv6 has the above advantages, disadvantages are also obvious. Actual deployment of the SRv6 technology in the network currently mainly faces two challenges: 1. a SRv6 message overhead is large and a bandwidth utilization rate of a network link is low, which is only about 60% under a condition that a packet length is 256 Bytes and the SID is 8-layer; 2. SRv6 message processing has high requirement on a chip, it is difficult for an existing network equipment to support an in-depth copying operation of a SRH header, and 128-bit SRH header processing can reduce a processing efficiency of an existing chip.
The requirement on the number of layers of a Segment Routing (SR) tag in an operator network is relatively high. Taking a fifth generation (5G) bearer network as an example, as the 5G core network is deployed in a centralized manner, traffic of a base station needs to pass through a metropolitan area network and an IP backbone network. In a typical scenario, in the metropolitan area network, there are 8-10 nodes in an access ring, a convergence ring has 4-8 nodes, and a core ring also has 4-8 nodes; and in the IP backbone network, the traffic also needs to pass through a plurality of router nodes. At the same time, because of a controllable requirements of a network slice and a high-reliable Service-Level Agreement (SLA), the operator network needs to specify an explicit path, and an end-to-end SR tunnel may have 10 hops or even more. Therefore, at present, most domestic and oversea operators deploy Multi-Protocol Label Switching (MPLS), whereas SR operators all require supporting more than eight layers of segment identifier (Segment ID, SID) tags.
Currently, SRv6 is a SR solution extended based on IPv6, the SRv6 solution is based on SRH, a SID length of the SRv6 is a 128-bit segment ID. In case of 8-layer SID, an overhead of 128 bytes is brought to the packet, and for an application payload with an average length of 256 bytes, the overhead brought by the SRv6 exceeds ⅓, and the bandwidth utilization rate is reduced to 67% or less. In the same scenario, the overhead of SR-MPLS is only 32 bytes, and the bandwidth utilization rate is still 89%. Comparative analysis of bearer efficiency between SRv6 and SR-MPLS in cases of the number of SIDs being from 1 to 10 is shown in
The increase of the overheads causes a reduction in network utilization, and further, provides a greater challenge for supporting in-depth packet load balancing, in-band telemetry (In-Band Telemetry), and a Network Service Header (NSH).
In addition, deployment of the SRv6 may necessarily coexist with the SR-MPLS network, and due to different network utilization rates, a problem that network boundary interfaces are not balanced, resulting in waste of investment. Referring to
In an operator's application, the SRv6 needs a network chip to insert a field having a length of more than 128 Bytes in the message, the 128 Byte field is equivalent to a 32-layer depth of a MPLS-SR tag, which exceeds a capability of a deployed network chip, and if a loop-back solution is used inside the chip, a network performance is greatly reduced and higher latency and jitter are introduced. In a redesigned network chip, it is necessary to further expand a bandwidth of an internal processing bus to support the SRv6, which is a key factor of chip cost and power consumption.
The SRv6 requires a network chip of an intermediate node to read a complete SRH, and then extracts, according to a position indicated by a pointer, a segment that needs to be processed, and forwards the segment. Comparing with the MPLS-SR which only needs to read an outermost label, introduced complexity further increases a processing delay of the network chip.
Low power consumption and a low delay are key factors of an operator's 5G solution, and an increase of the power consumption, the cost, and the delay brought to the network chip by complexity of the SRv6 brings a challenge to application of the SRv6.
According to the above analysis, an existing SRv6 message overhead, complexity of the network chip, and difficulty of smooth upgrading make it difficult to quickly deploy the SRv6 into an operator network, and need to be further evolved on basis of a SRv6 technology.
An objective of the embodiments of the present disclosure is to provide a message forwarding method, a message forwarding apparatus, a communication device, and a readable storage medium, to solve the problem of large overheads of an SRv6 message.
According to a first aspect, a message processing method performed by a first node is provided. The method includes:
Optionally, the method includes:
Optionally, copying the first SID and the second SID in the SID list to the destination address of the data packet and sending the data packet includes:
Optionally, copying the first SID and the second SID in the SID list to the destination address of the data packet, the first SID replacing the current SID, and the second SID replacing the next SID, includes:
Optionally, the method further includes:
Optionally, the destination address includes the current SID and the next SID; copying the first SID and the second SID in the SID list to the destination address of the data packet and sending the data packet includes:
According to a second aspect, a message processing apparatus is provided. The apparatus includes:
Optionally, the apparatus further includes:
Optionally, the sending module is further configured to:
Optionally, the sending module is further configured to:
Optionally, the apparatus is arranged in a first node, and the apparatus further includes:
Optionally, the destination address includes the current SID and the next SID; the sending module is further configured to
According to a third aspect, a communication device is provided. The communication device includes: a processor, a memory, and a program stored on the memory and executable on the processor, wherein when the program is executed by the processor, the processor implements steps of the method according to the first aspect.
According to a fourth aspect, a readable storage medium is provided, wherein a program is stored on the readable storage medium, wherein when the program is executed by a processor, the processor implements the steps of the method according to the first aspect.
In this embodiment of the present disclosure, the SRv6 message overhead can be effectively decreased, and complexity of a network chip is reduced.
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading detailed description of preferred embodiments hereinafter. The drawings are for a purpose of illustrating preferred embodiments only and are not to be considered as limitation of the present disclosure. Moreover, in the drawings, same reference signs are used to represent same components. In the drawings:
I. Definition of a Short SRv6 SID Format
According to a standard SRv6 SID format, it can be seen that in a typical programmable application supporting a SRv6 network, the SID format is regular, and regularity of the SID format can be fully utilized to optimize the standard SRv6 SID format.
A typical 32-bit SRv6 short G-SID format is defined herein, and the G-SID is composed of a Node ID, a Function ID and optional Arguments (Args) in a standard 128-bit SID. The standard 128-bit SID format is referred to as a complete SID, which defines a standard SRv6 SID, and the 32-bit SID is a shortened G-SID, which is a changed part of the complete SID. The format is shown in
Similarly, a G-SID of 16 bits may also be defined. The present disclosure is described temporarily with 32 bits as an example, and there are no special difference between the 16 bits and the 32 bits.
Conversion relationship between the complete SID and the short SID may be determined in following ways based on regularity of a SRv6 location identifier (Locator):
the complete SID=B (blocks, i.e., a general prefix)+N (node ID)+F (Function)+A (Args) (optional)+padding (optional);
G-SID=N+F (Function)+A (Args) (optional);
It can be seen therefrom that the G-SID plus a Common Prefix/an address block (Block) can form a complete SRv6 SID.
To support the G-SID, a short SRv6 SID format needs to be planned. For example, the Common Prefix is 96 bits, and the G-SID is 32 bits; for example, the Common Prefix is 64 bits, followed by the G-SID of 32 bits, and the remaining low 32 bits are 0.
II. Definition of a G-SID Container Format
When the short SID and the standard SID are arranged in a SRH SID list, it is required that the G-SID needs to be arranged in a 128-bit alignment manner in order to accurately locate the G-SID, that is, one row of 128 bits requires 4 32-bit shorten G-SIDs, or a plurality of the shortened G-SIDs of other lengths. If the arrangement is not full, padding is needed so that 128 bits are aligned.
For ease of understanding, this solution defines a concept of a G-SID container, which is 128 bits. One G-SID container may include:
When multiple types of SIDs are mixedly arranged, 128-bit alignment needs to be ensured. When the 128 bits cannot be completely filled by the G-SIDs, padding is needed. Taking the 32-bit G-SID as an example, a possible format of the G-SID container is shown in
Since multiple types of G-SID containers can be encoded in SRv6 SRH, this SRH is referred to as X-SRH which is implementation of a new SRv6 type which is referred to as X-SRv6. Details of a data plane of the X-SRv6 are described below.
III. Data Plane Mixture Scheme of Short Labels and Standard Labels
To support multiple types of SIDs (especially the G-SIDs and the standard SRv6 SIDs) to be mixed in one SRH, there is a need to perform certain extension on an existing SRH. There is also a need to perform certain extension on a control plane of the SRv6. Here, a data plane of X-SRv6 is first introduced, and an extension solution of a control plane of the X-SRv6 is subsequently introduced.
A basic concept of the data plane is that classical 128-bit SRv6 SIDs and G-SIDs can be mixedly encoded in one SRH.
As shown in
In order to identify the start and end of the SRv6 short label path in the SID list, that is, a boundary between the 128-bit SID and the 32-bit SID, several new types of flavors (Flavor) need to be added, and SIDs corresponding to the flavors are published, see Table 1.
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It is obvious that the described embodiments are a part, rather than all, of the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.
The terms “comprising” and any variations thereof in the specification and claims of the present disclosure are intended to cover non-exclusive inclusion, for example, processes, methods, systems, products, or devices that include a series of steps or units are not necessarily limited to those steps or units clearly listed, but may include other steps or units not expressly listed or inherent to these processes, methods, products, or devices. In addition, use of “and/or” in the specification and in the claims indicates at least one of the connected objects, such as A and/or B, indicating that there are three cases including only A exists alone, only B exists alone, and both A and B exist.
In the embodiments of the present disclosure, words such as “exemplary” or “for example” are used to represent an example, an illustration, or a description. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present disclosure should not be construed as being more preferred or more advantageous over other embodiments or design schemes. Rather, the use of “exemplary” or “for example” is intended to present related concepts in a particular manner.
The techniques described herein are not limited to fifth generation mobile communication (5G) systems and subsequent evolved communications systems, and are not limited to Long Term Evolution (LTE)/LTE-Advanced (LTE-A) systems, and may also be used in various wireless communication systems, such as Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiple Access (OFDMA), Single-Carrier Frequency-Division Multiple Access (SC-FDMA), and other systems.
The terms “system” and “network” are often used interchangeably. The CDMA system may implement radio technologies such as CDMA2000, Universal Terrestrial Radio Access (UTRA), etc. UTRA includes Wideband CDMA (Wideband Code Division Multiple Access, WCDMA), and other CDMA variants. A TDMA system may implement radio technologies such as Global System for Mobile Communication (GSM). An OFDMA system may implement radio technologies such as Ultra Mobile Broadband (UMB), Evolved UTRA (E-UTRA), IEEE 802.11(Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20, Fast Orthogonal Frequency Division Multiplexing (Flash-OFDM), etc. UTRA and E-UTRA are part of Universal Mobile Telecommunications System (UMTS). LTE and more advanced LTE (e.g., LTE-A) are new UMTS versions using E-UTRA. UTRA, E-UTRA, UMTS, LTE, LTE-A, and GSM are described in documents from the organization named “3rd Generation Partnership Project” (3GPP). CDMA2000 and UMB are described in documents from an organization named “3rd Generation Partnership Project 2” (3GPP2). The techniques described herein may be used in both the systems and radio technologies mentioned above, as well as other systems and radio technologies.
Referring to
Step 701: obtaining first information and second information of a first SID, wherein the first information indicates a location, in an SID list of a data packet, of a container where the first SID is located, and the second information indicates a location of the first SID in the container.
Step 702: obtaining a location of the first SID in the SID list according to the first information and the second information.
Step 703: copying the first SID and a second SID in the SID list to a current SID and a next SID in a destination address of the data packet, and sending the data packet, wherein the second SID is a next SID next to the first SID in the SID list, and the second information is greater than or equal to 1, or the second information is equal to 0.
In this embodiment of the present disclosure, the method further includes:
In this embodiment of the present disclosure, copying the first SID and the second SID in the SID list to the destination address of the data packet and sending the data packet includes:
In this embodiment of the present disclosure, copying the first SID and the second SID in the SID list to the destination address of the data packet, the first SID replacing the current SID, and the second SID replacing the next SID, includes:
In this embodiment of the present disclosure, the method further includes:
In this embodiment of the present disclosure, the destination address includes: the current SID and the next SID.
Copying the first SID and the second SID in the SID list to the destination address of the data packet and sending the data packet includes:
In this embodiment of the present disclosure, a SRv6 message overhead can be effectively decreased, and complexity of a network chip is reduced.
As shown in
The field may having a specified length. A minimum length of the field is related to the number of G-SIDs that can be accommodated in one container, for example, the length of the G-SID is 32, four G-SIDs can be placed in one container, and then the minimum of the SI needs 2 bits.
The SI is used to indicate the location of the G-SID in each 128-bit G-SID container, and if the G-SID uses a 32-bit compression SID, then the value of the SI is 0-3; and if the G-SID uses a 16-bit compression SID, then the value of the SI is 0-7.
In this embodiment of the present disclosure, in order to further improve the compression efficiency, compression SIDs are divided into two classes. One class is used to identify the global SID, such as an END SID, and values of the class are taken from a global SID set (GIB); and one class is used to identify the local SID, for example, END. X SID of a specified link or END.DT SID of a VPN Context, values of the class are taken from a local SID set (LIB). In this way, in some cases, only one global SID or one local SID is replaced at a certain node; in some cases, at a certain node, both the global SID and the local SID need to be replaced at the same time.
In this embodiment of the present disclosure, the efficiency is relatively low for the case that both the global SID and the local SID need to be replaced at the same time. The present application proposes a method, i.e, regardless of the class of the SID to be processed and the length of the SID, data having a length of 2×L is copied to the destination address each time, wherein L is the length of a SID having a minimum length. In this way, if a certain node only needs to use one global SID or one local SID, then a first SID having the length of L is used, and at the same time, SI−1; if a certain node needs to use both the global SID and the local SID at the same time, then 2 SIDs having the length of 2×L are used, and SI−2.
In this embodiment of the present disclosure, specific operation process is as follows:
Scenario 1:
referring to
Scenario 2:
Referring to
Referring to
Scenario 4:
Referring to
For invalid G-SID replacement that occurs in the above scenarios, following two methods may be used:
Solution 1: no pre-judgement is made before copying G-SIDs, two adjacent G-SIDs are copied as long as the SI meets the requirement. Only the first G-SID is valid when looking up the table, the NEXT G-SID is invalid, and the NEXT G-SID is changed into the current G-SID when replacing DA next time.
Solution 2: pre-judgement is made before copying G-SIDs, and only when the current G-SID belongs to the GIB and the NEXT G-SID belongs to the LIB, adjacent two G-SIDs are used to replace the DAs.
There are two cases:
Case 1: various network nodes uniformly define the range of GIB and LIB, for example, 16-bit compression SIDs, 0x0000-0xDFFF, belong to the GIB, 0xE000-0xFFFF belong to LIB: a forward plane of each node can directly make the determination.
Case 2: each network node independently defines ranges of GIBs and LIBs, and notifies by means of a control plane IGP/BGP protocol, and each node control plane can determine whether the G-SID belongs to the range of GIBs or the range of LIBs, but the forward plane does not have this information and is incapable of implementing the pre-judgement.
Referring to
In this embodiment of the present disclosure, the apparatus 1400 further includes:
In this embodiment of the present disclosure, the sending module 1403 is further configured to:
In this embodiment of the present disclosure, the sending module 1403 is further configured to:
In this embodiment of the present disclosure, the apparatus 1400 further includes:
In this embodiment of the present disclosure, the destination address includes: the current SID and the next SID. The sending module 1403 is further configured to:
The apparatus provided in the embodiments of the present disclosure may perform the method in the embodiment shown in
Embodiments of the present disclosure further provide a communication device. As shown in
The radio frequency apparatus 1502 may be located in the baseband apparatus 1503, and the method executed by the communication device in the foregoing embodiment may be implemented in the baseband apparatus 1503, and the baseband apparatus 1503 includes a processor 1504 and a memory 1505.
For example, the baseband apparatus 1503 may include at least one baseband board, the baseband board is provided with a plurality of chips, as shown in
The baseband apparatus 1503 may further include a network interface 1506 configured to interact with the radio frequency apparatus 1502, wherein the interface is, for example, a Common Public Radio Interface (CPRI).
Specifically, the communication device of the embodiments of the present disclosure further includes instructions or programs stored on the memory 1505 and executable on the processor 1504, wherein when the processor 1504 invokes the instructions or programs in the memory 1505, the processor 1504 executes the methods executed by the modules shown in
Embodiments of the present disclosure further provide a readable storage medium, wherein a program or an instruction is stored on the readable storage medium, and when the program or THE instruction is executed by a processor, each process of the method IN THE embodiment shown in
The processor is a processor in the terminal in the foregoing embodiment. The readable storage medium includes a computer readable storage medium, such as a computer Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disc.
The steps of the method or the algorithm described in conjunction with contents disclosed by the present disclosure may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes a software instruction. The software instruction may be composed of corresponding software modules, and the software modules may be stored in a RAM, a flash memory, a ROM, an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a register, a hard disk, and a mobile hard disk, read only optical disks or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor to enable the processor to read information from the storage medium and write information to the storage medium. Certainly, the storage medium may also be a component of the processor. The processor and the storage medium may be carried in an Application Specific Integrated Circuit (ASIC). In addition, the ASIC may be carried in a core network interface device. Certainly, the processor and the storage medium may also exist in the core network interface device as discrete components.
Those skilled in the art should be aware that, in the foregoing one or more examples, functions described in the present disclosure may be implemented by hardware, software, firmware, or any combination thereof. When implemented using software, these functions may be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes a computer storage medium and a communication medium, wherein the communication medium includes any medium that facilitates transfer of a computer program from one place to another. The storage medium may be any available medium accessible by a general purpose or special purpose computer.
Objectives, technical solutions, and beneficial effects of the present disclosure are further described in detail by the above detailed description, and it should be understood that the foregoing is merely specific embodiments of the present disclosure and is not intended to limit the protection scope of the present disclosure, and any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present disclosure shall fall within the protection scope of the present disclosure.
Those skilled in the art should understand that the embodiments of the present disclosure may be provided as a method, a system, or a computer program product. Therefore, the embodiments of the present disclosure may be in the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to a magnetic disk memory, a CD-ROM, an optical memory, etc.) including computer-usable program codes.
Embodiments of the present disclosure are described with reference to flowcharts and/or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each flow and/or block in the flowcharts and/or block diagrams, and combinations of flows and/or blocks in the flowcharts and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, a special purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing functions specified in one or more flows of the flowcharts and/or one or more blocks of the block diagrams.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a particular manner such that the instructions stored in the computer-readable memory produce an article that includes an instruction means. The instruction means implements the functions specified in one or more flows of the flowcharts and/or one or more blocks of the block diagrams.
These computer program instructions may also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on the computer or other programmable device to produce a computer-implemented process, such that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more flows of the flowcharts and/or one or more blocks of the block diagrams.
Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and the scope of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims and their equivalents, the present disclosure is also intended to encompass these modifications and variations.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202011321949.3 | Nov 2020 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/129000 | 11/5/2021 | WO |
