Patent Application
20060294277
The invention relates to message signaled interrupt redirection. More specifically, the invention relates to using a table of interrupt entries and interrupt redirection to preserve Message Signaled Interrupts (MSI) with new interrupt capabilities.
The PCI Local Bus Specification, Rev. 2.2 (Dec. 18, 1998) introduced the concept of a message signaled interrupt (MSI). An I/O bus-master capable device can request service using an MSI by writing a programmed value to a programmed address. MSI capabilities are present in all PCI Local Bus Specifications in and after Rev. 2.2, and additionally in the PCI Express™ Base Specification 1.0a (Apr. 15, 2003).
Many current Intel® Corporation processors and chipsets utilize MSI capabilities. The IA-32 Intel® Architecture Software Developer's Manual, Vol. 3 (2004) describes the necessary information included in the programmed value that a device must write to perform an MSI in a system with an Intel® Corporation processor or chipset. Two key pieces of information that must be included in the programmed value are the Destination ID (an 8-bit field containing the specific address for the processor or chipset) and the Vector (an 8-bit field containing the interrupt vector associated with the message).
A new extension of an Intel® Processor's integrated interrupt controller (i.e., an Advance Programmable Interrupt Controller) has been proposed to extend interrupt capabilities for Intel® processors. The two primary results of this change are an extension of the number of destinations (i.e., an increase in possible Destination IDs) and a potential increase in the number of Vectors. Unfortunately, as mentioned above, the current Intel® usage model limits the number of Destination IDs and Vectors to 256 each because of the 8-bit field limitation.
The present invention is illustrated by way of example and is not limited by the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
Embodiments of a method, device, and system for message signaled interrupt redirection are disclosed. In the following description, numerous specific details are set forth. However, it is understood that embodiments may be practiced without these specific details. In other instances, well-known elements, specifications, and protocols have not been discussed in detail in order to avoid obscuring the present invention.
In a computer system that utilizes an Intel® Corporation processor or chipset, the key limitation regarding number of MSI Destination IDs and Vectors is the 8-bit field limitation, as mentioned above, specified in the IA-32 Intel® Architecture Software Developer's Manual, Vol. 3 (2004). In order to circumvent this limitation and extend the Destination ID and the Vector fields, a level of indirection is needed.
Processor-memory interconnect 100 provides the central processor 102 access to the memory and input/output (I/O) subsystems. System memory controller 104 is coupled to processor-memory interconnect 100 for controlling access to system memory 106. In one embodiment, the system memory controller is located on the same chip as the central processor (a single chip processor and memory controller is not shown in this figure). Information, instructions, and other data may be stored in system memory 106 for use by central processor 102 as well as many other potential devices. In one embodiment, a device with a graphics processor (not shown) is also coupled to processor-memory interconnect 100. An I/O bus master device 112 is coupled to system I/O interconnect 110 and to processor-memory interconnect 100 through bridge 108. Bridge 108 is coupled to processor-memory interconnect 100 and system I/O interconnect 110 to provide an interface for a device on one interconnect to communicate with a device on the other interconnect.
In one embodiment, the I/O interconnect master device generates an MSI by writing a programmed value (referred to as the message data register) to a programmed address (referred to as the message address register).
In one embodiment, the message data register and message address register (206 of the present invention) include a new implementation of the programmed address 208 and the programmed value 210. In this embodiment, the programmed address 208 has a 16-bit Vector field (bits 17-2), which allows for a larger number of vector possibilities (216=65536 unique vectors). In one embodiment, the 16-bit vector field acts as an index value into a table of interrupt entries 212. In one embodiment, the table of interrupt entries is placed contiguously in system memory. The individual interrupt entries in the table can be any given uniform length to accommodate all necessary information. Among the information stored in each new interrupt entry 214 is an extended 64-bit Destination ID field.
Thus, when an MSI is generated it is redirected to the table of interrupt entries and the programmed address's 16-bit vector field enables a lookup of the specific interrupt entry being used. The initial redirection to the table may occur in a number of ways. In one embodiment, a bridge (such as bridge 108 in
Thus, embodiments of a method, device, and system for message signaled interrupt redirection are disclosed. These embodiments have been described with reference to specific exemplary embodiments thereof. It will, however, be evident to persons having the benefit of this disclosure that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the embodiments described herein. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
