Claims
- 1. A method for developing a circuit, comprising the steps of:
(A) generating a solution space having a dimension for each of a plurality of parameters for said circuit; (B) evaluating a plurality of instances of said circuit in said solution space through a software simulation; (C) evaluating said instances through a hardware simulation; and (D) updating said instances in response to said software simulation and said hardware simulation to approach an optimum instance of said instances for said circuit.
- 2. The method according to claim 1, further comprising the step of:
searching said solution space with a first granularity to identify a region of promise for said instances.
- 3. The method according to claim 2, further comprising the step of:
searching a region of promise with a second granularity finer than said first granularity.
- 4. The method according to claim 1, further comprising the step of:
searching said solution space using a first simulation time to identify a region of promise for said instances.
- 5. The method according to claim 4, further comprising the step of:
searching said region of promise using a second simulation time longer than said first simulation time.
- 6. The method according to claim 1, further comprising the steps of:
searching said region of promise to identify a region of interest for said instances; and reducing said region of promise using a first pruning technique.
- 7. The method according to claim 6, further comprising the step of:
reducing said region of promise using a second pruning technique more relaxed than said first pruning technique.
- 8. The method according to claim 1, wherein said hardware simulation comprises a throughput simulation.
- 9. The method according to claim 8, wherein said hardware simulation further comprises an area simulation.
- 10. The method according to claim 9, wherein said software simulation comprises a bit-error-rate simulation for a trellis decoder.
- 11. A decoder comprising:
a memory storing a plurality state metrics implementing a decoder trellis; and a plurality of pointers each configured to store a branch in said decoder trellis spanning a plurality of time steps of said decoder trellis.
- 12. The circuit according to claim 11, wherein each branch identifies one of a plurality of possible bit patterns received by said decoder.
- 13. A decoder comprising:
a memory storing a plurality state metrics implementing a decoder trellis; and a processor configured to (i) calculate a plurality of first branch metrics for a first half of a plurality of path segments in said decoder trellis in response to a signal received by said decoder, (ii) calculate a plurality of second branch metrics for a second half of said path segments based upon said first branch metrics and (iii) update said state metrics in response to said first branch metrics and said second branch metrics.
- 14. The decoder according to claim 13, wherein each particular first branch metric of said first branch metrics has a complementary second branch metric of said second branch metrics such that a sum of said particular first branch metric and said complementary second branch metric equals a constant.
- 16. A decoder comprising:
a memory storing a plurality state metrics implementing a decoder trellis; and a processor configured to (i) compute a plurality of branch metrics at each of a plurality of time steps of said decoder trellis substantially simultaneously and (ii) update said state metrics sequentially along said time steps based upon said branch metrics.
- 17. The decoder according to claim 16, further comprising:
a plurality of pointers each configured to store one of said path segments in said decoder trellis spanning a plurality of said time steps.
- 18. The decoder according to claim 16, further comprising:
a plurality of adders each configured to add one branch metric of said branch metrics to one state metric of said state metrics at a first time step of said time steps to generate a next state metric of said state metrics at a second time step of said time steps.
- 19. The decoder according to claim 18, further comprising:
a plurality of comparators each configured to (i) compare a plurality of said next state metrics and (ii) pass a lowest of said plurality of said next state metrics to said second time step.
- 20. The decoder according to claim 16, wherein said processor is further configured to recompute a subset of said branch metrics and a subset of said state metrics along a plurality of paths through said decoder trellis at a higher resolution than initially used to update said state metrics sequentially.
Parent Case Info
[0001] This application claims the benefit of U.S. Provisional Application No. 60/383,890, filed May 29, 2002 which is hereby incorporated by reference in its entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60383890 |
May 2002 |
US |