Patent Application
20250107114
The present invention relates to the field of semiconductor technology, and in particular to an improved metal oxide semiconductor (MOS) capacitor structure.
Metal oxide semiconductor (MOS) capacitors are composed of semiconductor substrate, insulating film and gate. In the existing technology, the MOS capacitor manufacturing process usually requires the use of a hard mask for forming the MOS capacitors in combination with two P-well ion implantation steps and one counter doping step. Therefore, the process cost of the prior art method is high and the time dependent dielectric breakdown (TDDB) of the MOS capacitor is not satisfactory.
It is one object of the present invention to provide an improved MOS capacitor structure to solve the deficiencies or shortcomings of the prior art.
One aspect of the invention provides a metal-oxide-semiconductor (MOS) capacitor structure including a substrate having a first conductivity type; a first trench isolation structure disposed in the substrate and surrounding an active area of the substrate; a source region disposed in the active area; a drain region disposed in the active area and spaced apart from the source region, wherein the source region and the drain region have a second conductivity type; a channel region disposed between the source region and the drain region; a counter doping region disposed in the channel region, wherein the counter doping region has the second conductivity type; a deep ion well disposed in the substrate under the channel region, wherein the deep ion well has the second conductivity type; a first semiconductor region between the deep ion well and the counter doping region and directly under the counter doping region; a gate disposed over the channel region; and a gate dielectric layer disposed between the gate and the channel region, wherein a doping concentration of the first semiconductor region is lower than a doping concentration of the deep ion well.
According to some embodiments, the first semiconductor region comprises dopants having the first conductivity type and dopants having the second conductivity type.
According to some embodiments, the MOS capacitor further includes a spacer disposed on a sidewall of the gate.
According to some embodiments, the MOS capacitor further includes a lightly doped drain (LDD) region disposed in the substrate and directly under the spacer, wherein the LDD region has the second conductivity type.
According to some embodiments, the counter doping region overlaps with the LDD region.
According to some embodiments, the counter doping region overlaps with the LDD region, the source region, and the drain region.
According to some embodiments, the MOS capacitor further includes a second trench isolation structure disposed in the substrate and surrounding the first trench isolation structure; and a first pick-up doping region disposed in the substrate between the first trench isolation structure and the second trench isolation structure, wherein the first pick-up doping region has the first conductivity type.
According to some embodiments, the MOS capacitor further includes a third trench isolation structure disposed in the substrate and around the second trench isolation structure; a second pick-up doping region disposed in the substrate between the second trench isolation structure and the third trench isolation structure, wherein the second pick-up doping region has the second conductivity type; and an ion well disposed in the substrate between the second pick-up doping region and the deep ion well, wherein the ion well has the second conductivity type.
According to some embodiments, a second semiconductor region is disposed between the deep ion well and the source region and between the deep ion well and the drain region.
According to some embodiments, the first conductivity type is P type and the second conductivity type is N type.
Another aspect of the invention provides a metal-oxide-semiconductor (MOS) capacitor including a substrate having a first conductivity type; a first trench isolation structure disposed in the substrate and surrounding an active area of the substrate; a source region disposed in the active area; a drain region disposed in the active area and spaced apart from the source region, wherein the source region and the drain region have a second conductivity type; a channel region disposed between the source region and the drain region; a counter doping region disposed in the channel region, wherein the counter doping region has the second conductivity type; a deep ion well disposed in the substrate directly under the channel region, wherein the deep ion well has the second conductivity type; a first semiconductor region between the deep ion well and the counter doping region; a second semiconductor region disposed between the source region and the deep ion well and between the drain region and the deep ion well in the substrate, and wherein the second semiconductor region surrounds the first semiconductor region, wherein a doping concentration of the second semiconductor region is greater than a doping concentration of the first semiconductor region; a gate disposed over the channel region; and a gate dielectric layer disposed between the gate and the channel region, wherein the doping concentration of the first semiconductor region is lower than a doping concentration of the deep ion well.
According to some embodiments, the first semiconductor region has dopants having the first conductivity type and dopants having the second conductivity type.
According to some embodiments, the MOS capacitor further includes a spacer disposed on a sidewall of the gate.
According to some embodiments, the MOS capacitor further includes a lightly doped drain (LDD) region disposed in the substrate directly under the spacer, wherein the LDD region has the second conductivity type.
According to some embodiments, the counter doping region overlaps with the LDD region.
According to some embodiments, the counter doping region overlaps with the LDD region, the source region, and the drain region.
According to some embodiments, the MOS capacitor further includes a second trench isolation structure disposed in the substrate and surrounding the first trench isolation structure; and a first pick-up doping region disposed in the substrate between the first trench isolation structure and the second trench isolation structure, wherein the first pick-up doping region has the first conductivity type, and wherein the second semiconductor region is disposed between the first pick-up doping region and the deep ion well.
According to some embodiments, the MOS capacitor further includes a third trench isolation structure disposed in the substrate and around the second trench isolation structure; a second pick-up doping region disposed in the substrate between the second trench isolation structure and the third trench isolation structure, wherein the second pick-up doping region has the second conductivity type; and an ion well disposed in the substrate between the second pick-up doping region and the deep ion well, wherein the ion well has the second conductivity type.
According to some embodiments, the second semiconductor region is contiguous with the ion well.
According to some embodiments, the first conductivity type is P type and the second conductivity type is N type.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.
Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.
In the semiconductor structures illustrated, there are two different conductivity types: P-type where the majority charge carriers are positively charged holes that typically migrate along the semiconductor valence band in the presence of an electric field, and N-type where the majority charge carriers are negatively charged electrons that typically migrate along the conduction band in the presence of an electric field. Dopants may be introduced into an intrinsic semiconductor to create one of the conductivity types. Heavily, medium, and lightly doped P-type materials are designated P+, P and P−, respectively, while heavily, medium, and lightly doped N-type materials are designated N+, N and N−, respectively.
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According to an embodiment of the present invention, a channel region CH is formed between the source region SR and the drain region DR. According to an embodiment of the present invention, at least a counter-doping region 103 is provided in the channel region CH, wherein the counter-doping region 103 has a second conductivity type, for example, N+ type. According to an embodiment of the present invention, a deep ion well 101 is provided in the substrate 100 below the channel region CH, where the deep ion well 101 has a second conductivity type, for example, N type.
According to an embodiment of the present invention, a first semiconductor region 102 is provided between the deep ion well 101 and the counter-doping region 103 and directly under the counter-doping region 103. According to an embodiment of the present invention, the doping concentration of the first semiconductor region 102 is lower than the doping concentration of the deep ion well 101. According to an embodiment of the present invention, the first semiconductor region 102 may have dopants of the first conductivity type and dopants of the second conductivity type.
According to an embodiment of the present invention, a gate 210 is disposed above the channel region CH, for example, a polysilicon gate or a metal gate. According to an embodiment of the present invention, a gate dielectric layer 202 is provided between the gate 210 and the channel region CH. The gate dielectric layer 202, for example, is a silicon dioxide layer, but is not limited thereto. During operation, a high voltage VG is provided to the gate 210.
According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a spacer SP, which is disposed on the sidewall of the gate 210. According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a lightly doped drain (LDD) region SRD and a lightly doped drain region DRD, which are disposed in the substrate 100 directly under the spacers SP, wherein the lightly doped drain region SRD and the lightly doped drain region DRD have the second conductivity type.
According to an embodiment of the present invention, the counter-doping region 103 overlaps the lightly doped drain region SRD and the lightly doped drain region DRD. According to an embodiment of the present invention, the counter-doping region 103 overlaps the lightly doped drain region SRD, the lightly doped drain region DRD, the source region SR, and the drain region DR
According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a second trench isolation structure ST2, which is disposed in the substrate 100 and surrounds the first trench isolation structure ST1. A first pick-up doping region PD1 is disposed in the substrate 100 between the first trench isolation structure ST1 and the second trench isolation structure ST2. According to an embodiment of the present invention, the first pick-up doping region PD1 has the first conductivity type, for example, P+ type. During operation, a voltage VB is provided to the first pick-up doping region PD1, for example, VB=0V.
According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a third trench isolation structure ST3, which is disposed in the substrate 100 and surrounds the second trench isolation structure ST2. According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a second pick-up doping region PD2 disposed in the substrate 100 between the second trench isolation structure ST2 and the third trench isolation structure ST3. According to an embodiment of the present invention, the second pick-up doping region PD2 has the second conductivity type, for example, N+ type. During operation, the voltage VDNW is provided to the deep ion well 101 via the second pick-up doping region PD2, for example, VDNW=VCC.
According to an embodiment of the present invention, the MOS capacitor structure 1 further includes an ion well 106, which is disposed in the substrate 100 between the second pick-up doping region PD2 and the deep ion well 101, wherein the ion well 106 has the second conductivity type, such as, N type. According to an embodiment of the present invention, the ion well 106 is an input/output (I/O) N-type well. According to an embodiment of the present invention, a second semiconductor region 102a is further provided between the deep ion well 101 and the source region SR and between the deep ion well 101 and the drain region DR. According to an embodiment of the present invention, the doping concentration of the second semiconductor region 102a is also lower than the doping concentration of the deep ion well 101. According to an embodiment of the present invention, the junction between the counter-doping region 103 and the first semiconductor region 102 is shallower than the junction between the source region SR and the second semiconductor region 102a. According to an embodiment of the present invention, the junction between the counter-doping region 103 and the first semiconductor region 102 is shallower than the junction between the drain region DR and the second semiconductor region 102a.
According to an embodiment of the present invention, the MOS capacitor structure 1 further includes an ion well 104, which is disposed in the substrate 100 between the second trench isolation structure ST2 and the deep ion well 101, wherein the ion well 104 has the first conductivity type, such as, P type. According to an embodiment of the present invention, the ion well 104 is an input/output (I/O) P-type well. According to an embodiment of the present invention, the ion well 104 does not extend directly below the first pickup doping region PD1.
Please refer to
According to an embodiment of the present invention, a channel region CH is provided between the source region SR and the drain region DR. According to an embodiment of the present invention, at least a counter-doping region 103 is provided in the channel region CH, wherein the counter-doping region 103 has the second conductivity type, for example, N+ type. According to an embodiment of the present invention, a deep ion well 101 is provided in the substrate 100 below the channel region CH, wherein the deep ion well 101 has the second conductivity type, for example, N type. During operation, a voltage VDNW is provided to the deep ion well 101, for example, VDNW=VCC.
According to an embodiment of the present invention, a first semiconductor region 102 is provided between the deep ion well 101 and the counter-doping region 103 and directly under the counter-doping region 103. According to an embodiment of the present invention, the doping concentration of the first semiconductor region 102 is lower than the doping concentration of the deep ion well 101. According to an embodiment of the present invention, the first semiconductor region 102 may have dopants of the first conductivity type and dopants of the second conductivity type.
According to an embodiment of the present invention, a gate 210 is disposed above the channel region CH, for example, a polysilicon gate or a metal gate. According to an embodiment of the present invention, a gate dielectric layer 202 is provided between the gate 210 and the channel region CH, for example, a silicon dioxide layer, but is not limited thereto. During operation, a high voltage VG is provided to the gate 210.
According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a spacer SP, which is disposed on the sidewall of the gate 210. According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a lightly doped drain region SRD and a lightly doped drain region DRD, which are disposed in the substrate 100 directly under the spacers SP, wherein the lightly doped drain region SRD and the lightly doped drain region DRD have the second conductivity type.
According to an embodiment of the present invention, the counter-doping region 103 overlaps the lightly doped drain region SRD and the lightly doped drain region DRD. According to an embodiment of the present invention, the counter-doping region 103 overlaps the lightly doped drain region SRD, the lightly doped drain region DRD, the source region SR, and the drain region DR.
According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a second trench isolation structure ST2, which is disposed in the substrate 100 and surrounds the first trench isolation structure ST1. A first pick-up doping region PD1 is disposed in the substrate 100 between the first trench isolation structure ST1 and the second trench isolation structure ST2. According to an embodiment of the present invention, the first pick-up doping region PD1 has the first conductivity type, for example, P+ type.
According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a third trench isolation structure ST3, which is disposed in the substrate 100 and surrounds the second trench isolation structure ST2. According to an embodiment of the present invention, the MOS capacitor structure 1 further includes a second pick-up doping region PD2, which is disposed in the substrate 100 between the second trench isolation structure ST2 and the third trench isolation structure ST3. According to an embodiment of the present invention, the second pick-up doping region PD2 has the second conductivity type, for example, N+ type.
According to an embodiment of the present invention, the MOS capacitor structure 1 further includes an ion well 106, which is disposed in the substrate 100 between the second pick-up doping region PD2 and the deep ion well 101, wherein the ion well 106 has the second conductivity type, such as, N type. According to an embodiment of the present invention, the ion well 106 is an input/output (I/O) N-type well. According to an embodiment of the present invention, a second semiconductor region 102a is further provided between the deep ion well 101 and the source region SR and between the deep ion well 101 and the drain region DR. The second semiconductor region 120a surrounds the first semiconductor region 120. The second semiconductor region 120a is also disposed between the first pick-up doping region PD1 and the deep ion well 101. According to an embodiment of the present invention, the doping concentration of the second semiconductor region 102a is greater than the doping concentration of the first semiconductor region 102.
According to an embodiment of the present invention, the MOS capacitor structure 1 further includes an ion well 104, which is disposed in the substrate 100 between the second trench isolation structure ST2 and the deep ion well 101, wherein the ion well 104 has the first conductivity type, such as, P type. According to an embodiment of the present invention, the ion well 104 is an input/output (I/O) P-type well. For example, the second semiconductor region 102a may have the first conductivity type, for example, P type. The doping concentration of the second semiconductor region 102a may be equal to the doping concentration of the ion well 104, but is not limited thereto. According to an embodiment of the present invention, the second semiconductor region 102a can be regarded as an extension of the ion well 104. The second semiconductor region 102a can avoid leakage current between the deep ion well 101 and the source region SR or between the deep ion well 101 and the drain region DR during operation.
One advantage of the present invention is that the conventional two P-type well ion implantation steps are omitted in the active region AA, so the process cost is reduced, and the doping dose of the counter doping region 103 can be reduced, which improves the time-dependent dielectric breakdown (TDDB) issue of the device.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112136045 | Sep 2023 | TW | national |
