METALLIZATION STRUCTURES FOR SOLAR CELLS

BACKGROUND

Photovoltaic (PV) cells, commonly known as solar cells, are devices for conversion of solar radiation into electrical energy. Generally, solar radiation impinging on the surface of, and entering into, the substrate of a solar cell creates electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby creating a voltage differential between the doped regions. The doped regions are connected to the conductive regions on the solar cell to direct an electrical current from the cell to an external circuit. When PV cells are combined in an array such as a PV module, the electrical energy collected from all of the PV cells can be combined in series and parallel arrangements to provide power with a certain voltage and current.

Techniques for increasing the efficiency of solar cells, or techniques for increasing the efficiency in the manufacture of solar cells, are generally desirable. Some embodiments of the present disclosure allow for increased solar cell manufacturing efficiency by providing novel processes for fabricating solar cell structures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a flow chart representation of an example method for fabricating a solar cell, according to some embodiments.

FIG. 2 illustrates a stage in solar cell fabrication following formation of a protective layer formed above a substrate of a solar cell, according to some embodiments.

FIG. 3 illustrates the structure of FIG. 2 following patterning the protective layer, according to some embodiments.

FIG. 4 illustrates the structure of FIG. 3 following forming a first metal layer over the substrate, according to some embodiments.

FIG. 5 illustrates the structure of FIG. 4 following forming a second metal layer over the first metal layer, according to some embodiments.

FIG. 6 illustrates bonding the second metal layer to the first metal layer of FIG. 5, according to some embodiments.

FIG. 7 illustrates a solar cell formed from the methods of FIG. 1-6, according to some embodiments.

FIG. 8 illustrates a top view of a portion of an example configuration for the solar cell of FIG. 7, according to some embodiments.

FIG. 9 illustrates a top view of a portion of another example configuration for the solar cell of FIG. 7, according to some embodiments.

FIG. 10 illustrates a top view of a portion of still another example configuration for the solar cell of FIG. 7, according to some embodiments.

FIG. 11 illustrates a top view of a portion of yet another example configuration for the solar cell of FIG. 7, according to some embodiments.

FIG. 12 illustrates example cell efficiency data, according to some embodiments.

DETAILED DESCRIPTION

The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter of the application or uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.

This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

Terminology. The following paragraphs provide definitions and/or context for terms found in this disclosure (including the appended claims):

“Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or steps.

“Configured To.” Various units or components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the units/components include structure that performs those task or tasks during operation. As such, the unit/component can be said to be configured to perform the task even when the specified unit/component is not currently operational (e.g., is not on/active). Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, sixth paragraph, for that unit/component.

“First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, reference to a “first” bond region does not necessarily imply that this bond region is the first bond region in a sequence, instead the term “first” is used to differentiate this bond region from another bond region (e.g., a “second” bond region). In an embodiment, a bond region can be a region which couples one layer to another layer. In an example, a bond region can couple a first metal layer to a second metal layer. In one example, a bond region can be a metal weld disposed between the first metal layer and second metal layer. In some examples, the bond region is a thermal bond region (e.g., a bond region formed from a thermal compression process).

1 “Based On.” As used herein, this term is used to describe one or more factors that affect a determination. This term does not foreclose additional factors that may affect a determination. That is, a determination may be solely based on those factors or based, at least in part, on those factors. Consider the phrase “determine A based on B.” While B may be a factor that affects the determination of A, such a phrase does not foreclose the determination of A from also being based on C. In other instances, A may be determined based solely on B.

“Coupled”—The following description refers to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically.

“Inhibit”—As used herein, inhibit is used to describe a reducing or minimizing effect. When a component or feature is described as inhibiting an action, motion, or condition it may completely prevent the result or outcome or future state completely. Additionally, “inhibit” can also refer to a reduction or lessening of the outcome, performance, and/or effect which might otherwise occur. Accordingly, when a component, element, or feature is referred to as inhibiting a result or state, it need not completely prevent or eliminate the result or state.

In addition, certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, “side”, “outboard”, and “inboard” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

In the following description, numerous specific details are set forth, such as specific operations, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known techniques are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure.

Approaches for metallization of solar cells and the resulting solar cells are described herein. In the following description, numerous specific details are set forth, such as specific solar cell structures and process flow operations, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known fabrication techniques, such as lithography and patterning techniques, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Disclosed herein are methods of fabricating solar cells. In an exemplary process flow, FIG. 1 illustrates a flowchart 100 listing operations in a method of fabricating a solar cell corresponding to FIGS. 2-8, according to some embodiments. In various embodiments, the method of FIG. 1 can include additional (or fewer) blocks than illustrated. For example, in some embodiments, a heating step can be performed after forming a metal seed layer over the substrate, at block 110.

Embodiments described herein include fabrication of a solar cell 200, according to some embodiments. Referring to FIG. 2 and corresponding operation 102 of flowchart 100, a semiconductor region 210 can be formed in or above a substrate 206. In an example, as shown in FIG. 1, the substrate 206 has disposed there above a semiconductor region 210. In an embodiment, the semiconductor region 210 is a n-type doped semiconductor region. In one embodiment, the semiconductor region 210 is a p-type doped semiconductor region. In some embodiments, the semiconductor region 210 can be an amorphous silicon region. In one embodiment, the region 210 can be a metal oxide having a high or low work function (e.g., work required to remove an electron from a material). Some examples, the semiconductor region 210 can be formed in the substrate 206. In an example, the semiconductor region 210 is an emitter region. In one embodiment, the semiconductor region 210 can be a polysilicon region. In an example, the semiconductor region 210 can be a heavily doped polysilicon region. In an embodiment, the semiconductor region 210 can be a doped n-type or a doped p-type polysilicon region. In an embodiment, a thin dielectric layer 208 can be disposed between the semiconductor region 210 and the substrate 206. In an embodiment, where the semiconductor region 210 is formed in the substrate 206, the thin dielectric layer 208 need not be formed. Although a cross-sectional view of a single semiconductor region is shown, a plurality of semiconductor regions can be used. In an example, a first semiconductor region and/or a second semiconductor region can be formed over the substrate 206. In one example, the first semiconductor region and/or a second semiconductor region can be n-type and/or p-type emitter regions. In an embodiment, the n-type and p-type emitter regions are formed in the substrate itself, in which case the dielectric layer 208 would not be included. In an embodiment, the first semiconductor region and/or a second semiconductor region can be doped n-type and/or doped p-type polysilicon regions. In some embodiments, a trench region can be formed which can separate the first and second semiconductor region. In an example, a trench region can be disposed between the first and second semiconductor regions. In an embodiment, the substrate 206 includes a light-receiving surface 216 on a front side 202 opposite a back side 204 of the solar cell 200. Although, as shown, the semiconductor region 210 is formed on a back side 204 of the solar cell 200, in some embodiments, the semiconductor region 210 can be formed on a front side 202 of the solar cell 200.

In an embodiment, the substrate 206 is a monocrystalline silicon substrate, such as a bulk single crystalline n-type doped silicon substrate. It is to be appreciated, however, that substrate 206 may be a layer, such as a multi-crystalline silicon layer, disposed on a global solar cell substrate. In an embodiment, the thin dielectric layer 208 is a tunneling silicon oxide layer having a thickness of approximately 2 nanometers or less. In one such embodiment, the term “tunneling dielectric layer” refers to a very thin dielectric layer, through which electrical conduction can be achieved. The conduction may be due to quantum tunneling and/or the presence of small regions of direct physical connection through thin spots in the dielectric layer 208. In one embodiment, the tunneling dielectric layer is or includes a thin silicon oxide layer. In an embodiment, the dielectric layer 208 includes silicon oxide (e.g., SiO₂), aluminum oxide (e.g., Al₂O₃), or an intrinsic amorphous silicon layer.

In an embodiment, the semiconductor region 210 is a polycrystalline silicon formed by, e.g., using a plasma-enhanced chemical vapor deposition (PECVD) process. In one such embodiment, the semiconductor region 210 is doped with an n-type impurity, such as phosphorus (e.g., n-type semiconductor region). In an embodiment, the semiconductor region 210 is doped with a p-type impurity, such as boron (e.g., p-type semiconductor region). As discussed above, although a cross-sectional view of a single semiconductor region is shown, a plurality of semiconductor regions can be used (e.g., n-type and p-type semiconductor regions).

In an embodiment, the light receiving surface 216, is a texturized light-receiving surface, as is depicted in FIG. 2. In one embodiment, a hydroxide-based wet etchant is employed to texturize the light receiving surface 216 of the substrate 206. In an embodiment, a texturized surface may be one which has a regular or an irregular shaped surface for scattering incoming light, decreasing the amount of light reflected off of the light receiving surfaces 216 of the solar cell 200. In some embodiments, the light receiving surface 216 need not be texturized.

Referring again to FIG. 2 and corresponding operation 104 of flowchart 100, a protective layer 104 can be formed over the substrate 206, according to some embodiments. In an embodiment, the protective layer 214 can also be referred to as an insulating layer. In one embodiment, the protective layer 214 includes a passivation layer and/or a back anti-reflective coating (BARC). In an example, the protective layer 214 includes silicon nitride, silicon dioxide and/or amorphous silicon. In an embodiment, the protective layer 214 can be a dielectric layer (e.g., include one or more dielectrics). In one embodiment, the protective layer 214 can include polyimide.

Referring to FIG. 3 and corresponding operation 106 of flowchart 100, contact holes 220 can be formed through the protective layer 214, according to some embodiments. In an embodiment, the contact holes 220 are formed to accommodate direct contact of a first metal layer to the second semiconductor region 210 (e.g., as discussed in FIG. 4 below). In an embodiment, the contact holes 220 are formed by a patterning process. In an example, a laser ablation, lithography and/or etching process can be performed to form the contact holes 220. In one embodiment, the contact holes 220 can have a diameter of approximately less than or equal to 50 microns. In an example, a contact holes having a 30 micron diameter can be formed. In one embodiment, protective layer 214 can include locations 224 without contact holes formed. In an example, these locations 224 can be referred to as contact hole free zones 224. In an embodiment, a distance, or gap 239, between contact holes 220 having a contact hole free zone 224 located between is approximately less than or equal to 0.50 millimeters.

Additional embodiments can include forming of a passivation and/or front anti-reflective coating (ARC) layer 218 on a light-receiving surface 216 at the front side 202 of the substrate 206. In an example, the front anti-reflective coating (ARC) layer 218 can include silicon nitride. It is to be appreciated that the timing of the formation of the protective layer 214 and/or ARC layer 218 may also vary. For example, subsequent to forming the protective layer 214 on the back side 204 (e.g., a BARC layer) of the substrate 206, the ARC layer 218 can be formed on the front side 202. In one embodiment, the protective layer 214 can be formed subsequently after the ARC layer 218. In some embodiments, both the protective layer 214 and the ARC layer 218 can be formed in a single process (e.g., the same process step).

Referring to FIG. 4 and corresponding operation 108 of flowchart 100, a first metal layer 226 is formed over the substrate 206 (which may be referred to as a metal seed layer and/or a M1 layer, for the solar cell 200), according to some embodiments. In an embodiment, the first metal layer 226 can be formed as an uninterrupted layer over the substrate 206. In an embodiment, portions of the first metal layer 216 can contact the semiconductor region 210 at the contact holes 220 of the protective layer 214. In one example, the first metal layer 226 can be formed using a blanket deposition process. In one example, a sputtering process can be used to deposit the first metal layer 226. In an embodiment, the first metal layer 216 can formed using a patterning process (e.g., a printing process). In an example, a screen printing process can be performed to form the first metal layer. In one example, a patterned metal seed layer can be formed. In some embodiments, the first metal layer 226 can include a metal paste (e.g., an aluminum paste). In an embodiment, the first metal layer 226 can include one or more metals and/or metal alloys. In an example, the first metal layer 226 can include aluminum, titanium tungsten, tungsten, and/or copper, among other metals. In an embodiment, the first metal layer 226 can be formed significantly thin. In an example, the first metal layer 226 can be formed having a thickness of approximately less than or equal to 400 nanometers.

Referring to FIG. 5 and corresponding operation 110 of flowchart 100, a second metal layer 228 can be formed over the first metal layer 226. In an embodiment, the second metal layer 228 is a metal foil, according to some embodiments. In an example, a metal foil 228 can be placed over the first metal layer 226. In an embodiment, the metal foil 228 is an aluminum foil. In an embodiment, the metal foil 228 can be pre-patterned and/or placed over the semiconductor region 210. In an example, a patterned metal foil can be placed over the semiconductor regions 210. In one example, the patterned metal foil can follow a pattern in alignment with the semiconductor region 210.

In an embodiment, metal foil 228 is an aluminum (Al) foil having a thickness approximately in a range of 5-100 microns and, in one example, having a thickness of approximately less than 50 microns. In one embodiment, the Al foil is an aluminum alloy foil including aluminum and second element such as, but not limited to, copper, manganese, silicon, magnesium, zinc, tin, lithium, or combinations thereof. In one embodiment, the AI foil is a temper grade foil such as, but not limited to, F-grade (as fabricated), O-grade (full soft), H-grade (strain hardened) or T-grade (heat treated).

Referring to FIG. 6 and corresponding operation 112 of flowchart 300, bond regions 234 can be formed between the first metal layer 226 and the second metal layer 228, according to some embodiments. In an embodiment, a bonding process can be used to form the bond regions 234. In an example, the bonding process can include performing a laser welding, thermal compression process or an ultrasonic bonding process. In an example, a laser welding process can be performed to form a bond region between a metal foil 228 and a metal seed layer 226. In one embodiment, the bond region 234 is formed by directing a laser 232 over the second metal layer 228. In one example, the bond region 234 is a metal weld 234 formed from a laser welding process. In an example, the metal weld can be a line weld and/or a spot weld. As used herein, metal welds can be used interchangeably with bond regions. In an embodiment, a pitch 237 between bond regions 234 (e.g., distance from the center of one bond region to another bond region) is approximately less than or equal to 5 millimeters. In an example, the pitch 237 can be 1.00 millimeters. In one embodiment, the bond region 234 can have a diameter of approximately less than or equal to 100 microns. In an example, a metal weld 234 having an 80 micron diameter can be formed. In an embodiment, the bond region 234 is a melted region of the second metal layer 228. In one example, the bond region 234 can be a melted region of a metal foil.

Forming a bond region 234 in direct overlap with contact holes can be detrimental to the operation of the solar cell 200. In an example, laser welding above a contact hole 220 can cause intermixing and/or diffusion of contaminants which can degrade the performance of a solar cell by introducing recombination sites in a semiconductor region of the solar cell. In one example, these recombination sites can be in-diffused contaminants or metal. In an example, these recombination sites can also be crystal defects arising from imperfect re-crystallization of the semiconductor upon cooling of the intermixed phase. In an example, the recombination sites can also be caused by altering (upon intermixing and/or recrystallization), for example, redistribution of dopants and/or introducing doping via metal incorporation, such as in a p-type aluminum doping of silicon. In one example, another mechanism of degrading the solar cell performance upon intermixing and/or in-diffusion of metal and/or contaminants is contamination of a tunnel oxide (e.g. dielectric layer 208). Thus, in an embodiment, the bond regions 234 are formed at locations 230 above contact hole free zones 224 of the protective layer 214 (e.g., at locations that do not directly overlap with at least one contact hole 220).

In an embodiment, a laser can be scanned at different scanning speeds over a metal layer to allow the formation of metal welds which do not overlap with contact holes of the protective layer. Thus, forming the bond regions 234 can include locally scanning a laser over metal layer as also described in U.S. patent application Ser. No. 15/201,349, the entirety of which is hereby incorporated by reference.

In an embodiment, the protective layer 214 can prevent and/or inhibit damage to the underlying substrate 206 during the bonding process. In one embodiment, the protective layer 214 prevents and/or inhibits radiative damage to the semiconductor region 210 from a laser welding process during the formation of a bond region 234. In an example, to minimize solar cell manufacturing cost and material usage, the first metal layer 226 can be formed significantly thin (e.g., approximately less than equal to 400 nanometers). In the same example where the first metal layer 226 is formed significantly thin, the protective layer 214 can prevent and/or inhibit damage to the semiconductor region 210 due to radiative and/or thermal damage from a laser welding process. In one embodiment, the protective layer 214 prevents and/or inhibits thermal damage to the semiconductor region 210 from a thermal compression process during the formation of a bond region 234. In an example, a thermal compression process can be performed to form a bond region 234 between a metal foil 228 and a metal seed layer 226. In one example, the bond region 234 is a thermal bond region.

FIG. 7 illustrates a solar cell formed from the methods of FIGS. 1-6, according to some embodiments. In an embodiment, the solar cell 200 includes a substrate 206. In an embodiment, the solar cell 200 has a front side 202 and a back side 204, opposite the front side 202. In one embodiment, the solar cell 200 includes a semiconductor region 210 disposed in (not shown) or above (as shown) the substrate 206. As discussed above, in an example, the substrate 206 can be a monocrystalline silicon substrate, such as a bulk single crystalline n-type doped silicon substrate.

In an embodiment, a protective layer 214 is disposed over the semiconductor region 210. In an embodiment, the protective layer 214 can also be referred to as an insulating layer. In one embodiment, the protective layer 214 includes a passivation layer and/or a back anti-reflective coating (BARC). In an example, the protective layer 214 includes silicon nitride, silicon oxide and/or amorphous silicon. In an embodiment, the protective layer 214 can be a dielectric layer (e.g., include one or more dielectrics). In one embodiment, the protective layer can include polyimide.

In an embodiment, the protective layer 214 includes contact holes and/or openings 220 formed through the protective layer 214. In one embodiment, the contact holes 220 can have a diameter of approximately less than or equal to 50 microns. In an example, a contact holes having a 30 micron diameter can be formed. In one embodiment, protective layer 214 can include locations 224 without contact holes formed. In an example, these locations 224 can be referred to as contact hole free zones 224.

In one embodiment, a conductive contact 236 is disposed over the protective layer 214 and are electrically connected to the semiconductor region 210 through the contact holes 220. Although only a single conductive contact 236 and/or semiconductor region 210 is shown, more than one conductive contact 236 and/or semiconductor region 210, e.g., two or more conductive contacts 236 and/or semiconductor regions 210 can be present. In an embodiment, the conductive contact 236 includes a second metal layer 228 disposed over a first metal layer 226. In an embodiment, the first metal layer 226 can be formed significantly thin. In an example, the first metal layer 226 can be formed having a thickness 213 of approximately less than or equal to 400 nanometers. In an embodiment, the second metal layer 228 can be formed significantly thick. In an example, the second metal layer 228 can be formed having a thickness 211 approximately in a range of 25-75 microns. In an example, the conductive contact 236 includes a metal foil portion 228 disposed over a metal seed layer 226. In an embodiment, the metal seed layer 226 is disposed over the substrate 206, where portions of the metal seed layer 226 are in contact with the semiconductor region 210 at the contact holes 220. In an embodiment, contact holes 220 allow for electrical conduction between the metal seed layer 226 and the semiconductor region 210. Although, as shown, the conductive contact 236 and/or semiconductor region 210 is formed on a back side 204 of the solar cell 200, in some embodiments the conductive contact 236 and/or semiconductor region 210 can be formed on a front side 202 of the solar cell 200.

In an embodiment, bond regions 234 electrically connect the metal foil 228 to the metal seed layer 226. In one embodiment, the bond regions 234 can have a diameter of approximately less than or equal to 100 microns. In an example, a bond regions 234 having an 80 micron diameter can be formed. In some embodiments, a lateral distance from an edge 217 of a bond regions 234 to an edge of a contact hole can be approximately in a range of 10-100 microns. In one embodiment, a direct distance 219 from an edge 217 of a bond region 234 to an edge of a contact hole can be approximately in a range of 50-150 microns. In an embodiment, the bond region 234 is a metal weld formed from a laser welding process. In one embodiment, the bond region 234 is a thermal bond region 234 (e.g., a bond region formed from a thermal compression process). Forming a bond region 234 in direct overlap with contact holes 220 can be detrimental to the operation of a solar cell. In an example, laser welding above a contact hole 220 can cause deep intermixing and/or diffusion of contaminants, as discussed above, from the metal seed layer 226 into the semiconductor region 210. Thus, in an embodiment, the bond regions 234 are disposed over the metal seed layer 226 at locations 230 above contact hole free zones 224 of the protective layer 214. In an embodiment, the bond regions 234 provide structural support between the metal foil 228 and metal seed layer 226.

With reference to FIG. 8, there is shown a top view of a portion of an example configuration for the solar cell of FIG. 7, according to some embodiments. In an embodiment, bond regions 234 can be formed in linear alignment with contact holes 220. In an embodiment, a pitch 239 between bond regions 234 (e.g., distance from the center of one bond region to another bond region) is approximately less than or equal to 5 millimeters. In an example, the pitch 237 can be 1.00 millimeters. In one embodiment, the bond region 234 can have a diameter of approximately less than or equal to 100 microns. In an example, a bond region 234 having an 80 micron diameter can be formed. In one embodiment, the contact holes 220 can have a diameter of less than or equal to 50 microns. In an example, a contact holes having a 30 micron diameter can be formed. In an embodiment, a distance or gap 239 (e.g., distance from the center of one contact hole to another contact hole), between contact holes 220, having a bond region 234 formed between, is approximately less than or equal to 0.50 millimeters. Varying the gap 239 and pitch 237 to provide an optimal pathway for charger carriers to travel from the semiconductor region 210 (e.g., 210 of FIG. 7) and through the conductive contact 236 can allow for improved solar cell efficiency, an example of which is shown in FIG. 12 below.

FIG. 9 illustrates a top view of a portion of another example configuration for the solar cell of FIG. 7, according to some embodiments. As shown, in an embodiment, the contact holes 220 can be aligned linearly along a center of a conductive contact 236. In an embodiment, bond regions 234 can be located adjacent to the contact holes 220 and are located along edges of the conductive contact 236 as shown.

With reference to FIG. 10, there is shown a top view of a portion of still another example configuration for the solar cell of FIG. 7, according to some embodiments. As shown, a continuous bond region 240 can be formed and aligned linearly along a center of a conductive contact 236. In an example, the continuous bond region 240 can be referred to as a line weld. As shown, in an embodiment, the contact holes 220 can be aligned linearly and/or adjacent the continuous bond region 240. In an embodiment, the contact holes 220 can have distance 242 of approximately less than or equal to 500 nanometers from an edge of a contact hole 220 to an edge of the conductive contact 236.

FIG. 11 illustrates a top view of a portion of a portion of yet another example configuration for the solar cell of FIG. 7, according to some embodiments. FIG. 11 shows a similar configuration to FIG. 10 but instead of having a continuous weld 240 or line weld, as in FIG. 10, spot welds 234 can instead be formed. As shown, a bond regions 234 can be formed and aligned linearly along a center of a conductive contact 236. As shown, in an embodiment, the contact holes 220 can be aligned linearly and/or adjacent to bond regions 234. In an embodiment, the contact holes 220 can have distance 242 of less than or equal to 500 nanometers from an edge of a contact hole to an edge of the conductive contact 236.

With reference to FIG. 12 example solar cell efficiency data is shown, according to some embodiments. Referring to FIG. 8 and the data shown in FIG. 12, G represents a gap between contact holes 239 and P represents a pitch between bond regions 237, emphasis added. The gap G is a distance from the center of one contact hole to another contact hole (e.g., as shown in 239FIG. 8). The pitch P is a distance from the center of one bond region to another bond region (e.g., as shown in 237FIG. 8). Points 302-310 illustrate representative data calculations gathered for the absolute value of the difference in solar cell efficiency from a control solar cell, 302, and solar cells 304-310 with varied gap G and pitch P. An optimal configuration can be a configuration which minimizes efficiency loss, e.g., approximately less than or equal to 0.1% in reference to the control solar cell 302. Points 304, 306 and 308 represent example configurations of G and P which show minimized efficiency loss. 310 represents an example where the absolute value of the solar cell efficiency difference varies significantly from the control 302. It can be possible that the G and P configuration for 310 provides for a longer pathway for charge carriers in comparison to points 304, 306 and 308 and thus reduced solar cell efficiency.

Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure.

The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.

METALLIZATION STRUCTURES FOR SOLAR CELLS

Information

Publication Number

Date Filed

Date Published

Inventors

Original Assignees

CPC

International Classifications

Abstract

Description

Claims