The technical field of this invention is processor technology in communicating with external devices and more specifically microcontrollers communicating with SDRAM.
Existing microprocessors access synchronous dynamic random access memories (SDRAMs) using the full set of pins. Many will connect a set of SDRAMs in parallel to get wider data widths (such as used by dual in line memory modules (DIMMs)), but none are concerned with fewer pins. The main focus of most microprocessors is maximizing performance, since the SDRAM is the memory used by the processor.
Microcontroller units (MCUs) traditionally try to have all memory in the chip and try to minimize number of pins. MCUs with external memory normally pin limit by use of narrower data widths, narrower address widths, both or multiplexing address and data. Narrow data widths require more data accesses. Narrower address widths limit the amount of memory addressable. Multiplexing of address and data has been used for older style SRAMs and Flash devices because the address versus data read/write are separate operations controlled by strobes (request pins) at the expense of speed. In other cases, multiplexing is used with an external device which maps fewer pins to the larger number of pins needed but still at the expense of speed.
SDRAMs are not amendable to the traditional multiplexing because they use a different operational model. The address versus data operation is controlled by commands and is clocked. Separate strobed pins are not used.
The invention is an apparatus and method to allow processor use of SDRAM with fewer pins. The invention favorably uses a burst mode. In this invention the address before the actual initial write address is used in the first cycle of the burst mode having a burst size of two or more. In addition, in the first cycle all data writes are suppressed via data mask (DQM) signals. During second and subsequent cycles at least some data writes are permitted by DQM signals. Bursts larger than two allow normal use of burst writes in subsequent cycles because the address is supplied only with an initiating write command.
These and other aspects of this invention are illustrated in the drawings, in which:
This invention allows an MCU to use SDRAM with fewer pins. This disclosure includes numerous specific details to provide a thorough understanding of the invention. One skilled in the art would appreciate that one may practice the invention without some or all of these specific details. This disclosure does not describe some well known items in detail in order not to obscure the invention.
The standard approach when using SDRAM memory with a microcontroller unit devotes a full set of pins to cover address, command, data and control. This large number of pins requires larger packaging for the MCU and far more power to control and drive all of the pins. This invention reduces the number of pins without specialized hardware external to the MCU. This reduction in the number of pins is achieved by multiplexing the address output of the MCU with the data input/output of the MCU.
This invention uses logic in the MCU to access the SDRAM with 14 to 16 fewer pins. The address and data pins are overlapped or wire ORed. Special operational logic ensures there are no conflicts.
This invention advantageously uses a commonly supported burst mode in SDRAMs. In a burst read, MCU 130 supplies an initial memory address. The SDRAM returns data starting at this initial address during a following clock cycle. The SRRAM returns data from the next following addresses in subsequent clock cycles up to the burst length.
SDRAM read operations naturally support the wired OR 120 illustrated in
This invention also permits write operations. SDRAM writes typically require that the initial address and the data of the write operation to be stored at the initial address be present on respective address and data pins at the same time during the same memory clock cycle. This would normally prevent using the wired OR of this invention. This invention favorably uses write masking in the burst mode. This invention presents the address one less than the initial write address to the SDRAM with a burst size of two or more. The SDRAM burst write operation would ordinarily store the data on the data bus during this initial memory cycle into the supplied memory address. With wire OR 120, this data would be the address one less than the initial write address. This invention suppresses the first write in this burst mode via DQM data masking signals. Thus this first write has no effect. DQM mask signals are normally used to allow independent writes of lower or upper byte in a by-16 SDRAM or any of 4 bytes in a by-32 SDRAM rather than writing the whole data word. This invention uses such DQM signals to prevent any write during the first cycle of the burst write access by masking all bytes. This invention thus uses these DQM signals to separate the address from the data. In this invention the first write cycle of the burst mode writes the address. The second write cycle in the burst mode writes the initial data. The DQM mask signals permit a normal write operation during the second write cycle. Burst accesses larger than two allow normal use of burst writes, where the address is supplied only with the initiating write command. Thus MCU 130 supplies the write data for sequential addresses in sequential memory clock cycles.
Block 203 notes the actions of MCU 130 during a first memory cycle in the burst access. MCU 130 supplies an address on multiplexed address/data bus 131. This address is one less than the actual initial address of the upcoming write cycle. MCU 130 supplies signals on control bus 133 to trigger a burst access write. Finally, MCU 130 supplies signals on the one or more lines of DQM bus 135 to prevent any memory write. This is noted in block 203 as “All Mask.” The result of this first cycle is to start an SDRAM burst access with the next cycle at the initial address of the desired memory write.
Block 204 notes the actions of MCU 130 during the second and any subsequent memory cycles in the burst access. MCU 130 supplies the next data on multiplexed address/data bus 131. In the case of the second cycle in the burst access, this next data is the data to be stored in the first address of the write operation. MCU 130 supplies signals on control bus 133 to continue the burst access write. MCU 130 supplies signals on the one or more lines of DQM bus 135 to permit normal memory write. This is noted in block 204 as “Normal Mask.” Depending upon the particular memory write operation the signals on DQM bus 135 may block some byte memory writes. However, at least one byte write is allowed during the second cycle of the burst access.
The method determines if the last cycle was the end of the burst access in test block 205. If the last cycle was the end of the burst (Yes at test block 205), then the method ends at end block 206.
If the last cycle was not the end of the burst (No at test block 205), then the method determines whether the previous cycle supplied the last data in the data write in test block 207. If the last cycle stored the last data (Yes at test block 207), then MCU 130 issues a burst terminate command (block 208) via command bus 133. Thereafter the method ends at end block 206.
If the last cycle did not store the last data (No at test block 207), then MCU 130 returns to block 204. MCU 130 supplies the next data on multiplexed address/data bus 131, supplies signals on control bus 133 to continue the burst access write and supplies signals on the one or more lines of DQM bus 135 to permit normal memory write.
The invention is an apparatus and method allowing an MCU to use an SDRAM with fewer MCU pins. The invention favorably uses the SDRAM burst mode. In the invention the MCU supplies the address before the actual initial write address to the SDRAM in a burst mode with a burst size of two or more. In the invention, the first burst mode write cycle writes the address and blocks the all data writes via DQM masking. For second and subsequent cycles, the MCU supplies the write data and unmasks one or more DQM pins.
This application claims priority under 35U.S.C. 119(e)(1) to U.S. Provisional Application No. 61/105,256 filed Oct. 14, 2008.
Number | Date | Country | |
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61105256 | Oct 2008 | US |