The invention relates to a method and to a device for controlling allocation of memory blocks of a memory organized to contain a plurality of memory block groups each of which containing a plurality of memory blocks. Furthermore, the invention relates to a computer program for controlling allocation of memory blocks of a memory.
In many electronic devices which comprise a memory and a processor there is a need to allocate parts of the memory for some purposes of use, and later release the allocated parts when they are no more needed for these purposes of use. Network elements such as routers, switches, and bridges are examples of electrical of devices of the kind mentioned above. A network element receives data frames, stores and processes the received data frames, and finally forwards the data frames to data transfer links which connect the network element to other network elements. Many network elements comprise one or more such memories which are organized to contain a plurality of memory block groups each of which containing a plurality of memory blocks. A single memory block can be allocated, for example, for storing a data frame, or a part of it, which is queuing up for being processed or forwarded. A process that controls the allocation of the memory blocks receives, from another process that uses the memory, a request to allocate one or more memory blocks and, in response to this request, returns one or more addresses which identify the allocated one or more memory blocks. When the allocated memory blocks are no more needed, the process using the memory returns one or more addresses which identify the memory blocks that can be released to wait for further use. The process for controlling the allocation of the memory blocks is frequently in use, and thus the process should be such that a cache memory is effectively utilized. In typical methods for controlling the memory allocation, this is however not the case because pointers which indicate the locations of free and allocated memory blocks are situated in conjunction with the memory blocks, and thus these pointers are located in a distributed way in the address space of the memory. Therefore, data items which are used in successive allocation or releasing operations can be located relatively far from each other in the address space. Thus, it is typical that the cache memory contains data which is used only once or twice and, before the next usage of this data, a lot of other data is used and loaded to the cache memory and therefore the first mentioned data may be dropped out from the cache memory before its next usage. As a corollary, the cache memory is not effectively utilized.
The following presents a simplified summary in order to provide a basic understanding of some aspects of various invention embodiments. The summary is not an extensive overview of the invention. It is neither intended to identify key or critical elements of the invention nor to delineate the scope of the invention. The following summary merely presents some concepts of the invention in a simplified form as a prelude to a more detailed description of exemplifying embodiments of the invention.
In accordance with the first aspect of the invention there is provided a new device for controlling a memory organized to contain a plurality of memory block groups each of which containing a plurality of memory blocks. The device according to the invention comprises a processor configured to:
The processor is further configured to carry out the following actions in response to receiving a request to allocate a free memory block:
In a device according to an advantageous and exemplifying embodiment of the present invention, the processor is further configured to carry out the following actions in response to receiving an address identifying a memory block to be released from allocation:
The above-mentioned first data entity that contains the first data items is used in every allocation and releasing operation. Thus, at each allocation or releasing operation, the first data entity can be found from a cache memory with a very high probability. Also the second data entities can be arranged to constitute a compact data set because each second data item can be a data element of only few bits. Hence, at each allocation or releasing operation, also the second data entity relating to the memory block group under consideration can be found from the cache memory with a good probability.
For example, in a case where there are e.g. 48 memory block groups each containing e.g. 15 memory blocks, each first data item can be four bits and also each second data item can be four bits. In this exemplifying case, the size of the first data entity is 48×4 bits which is 24 bytes, and the size of each second data entity is 15×4 bits which is less than 8 bytes. In a case where a cache line is e.g. 32 bytes, the first data entity fits in a single cache line and four second data entities fit in a single cache line. The whole data structure, i.e. the first data entity and the 48 second data entities, fits in only 13 cache lines. Thus, cache misses are very improbable in allocation and releasing operations, and therefore the cache memory can be effectively utilized.
In accordance with the second aspect of the invention there is provided a new method for controlling a memory organized to contain a plurality of memory block groups each of which containing a plurality of memory blocks. The method according to the invention comprises:
The method further comprises carrying out the following actions in response to receiving a request to allocate a free memory block:
A method according to an advantageous and exemplifying embodiment of the present invention further comprises carrying out the following actions in response to receiving an address identifying a memory block to be released from allocation:
In accordance with the third aspect of the invention there is provided a new computer program for controlling a memory organized to contain a plurality of memory block groups each of which containing a plurality of memory blocks. The computer program according to the invention comprises computer executable instructions for controlling a programmable processor to:
The computer program further comprises computer executable instructions for controlling the programmable processor to carry out the following actions in response to receiving a request to allocate a free memory block:
A computer program according to an advantageous and exemplifying embodiment of the present invention further comprises computer executable instructions for controlling the programmable processor to carry out the following actions in response to receiving an address identifying a memory block to be released from allocation:
In accordance with the fourth aspect of the invention there is provided a new computer program product. The computer program product comprises a non-volatile computer readable medium, e.g. a compact disc “CD”, encoded with a computer program according to the invention.
A number of exemplifying embodiments of the invention are described in accompanied dependent claims.
Various exemplifying embodiments of the invention both as to constructions and to methods of operation, together with additional objects and advantages thereof, will be best understood from the following description of specific exemplifying embodiments when read in connection with the accompanying drawings.
The verb “to comprise” is used in this document as an open limitation that neither excludes nor requires the existence of also un-recited features. The features recited in depending claims are mutually freely combinable unless otherwise explicitly stated.
The exemplifying embodiments of the invention and their advantages are explained in greater detail below with reference to the accompanying drawings, in which:
The data structure comprises N+1 second data entities 102, 103, . . . , 105 so that there is one second data entity for each of the N+1 memory block groups. Each of the second data entities contains second data items so that the number of the second data items in each second data entity is at least the number of the memory blocks in the memory block group related to this second data entity. For example, the memory block group related to the first data item ‘0’ and to the second data entity ‘0’ contains M(0) memory blocks and thus the second data entity ‘0’ contains at least M(0) second data items, and correspondingly, the memory block group related to the first data item ‘N’ and to the second data entity ‘N’ contains M(N) memory blocks and thus the second data entity ‘N’ contains at least M(N) second data items. However, it is usually advantageous that all the memory block groups contain a same number of memory blocks.
When one or more of the memory blocks of a given memory block group are free, one or more of the second data items of the corresponding second data entity contain indicators identifying the free memory blocks from among all the memory blocks of this memory block group. In the exemplifying case illustrated in
When a request to allocate a free memory block has been received, such a first data item that indicates that there is at least one free memory block in the corresponding the memory block group is searched from the first data entity 101. This search can be, for example, a linear search starting from the first data item ‘0’, but it should be noted that this is not the only possible choice. For another example, the first data entity 101 can be arranged to be a logical ring so that each first data item has a predecessor and a successor in the logical ring, and the data structure comprises a pointer 131 indicating, from the logical ring, such a first data item that relates to the memory block group that contains a previously-allocated memory block. The search is started from a first data item that is indicated by the pointer 131. In
In the exemplifying case illustrated in
It should be noted that arranging the second data entities in ordered lists, where the indicators of free memory blocks are placed at the ends of the ordered lists, is not the only possible choice. The indicators of free memory blocks can be handled in the second data entities according to various pre-determined principles. For example, each second data entity can be an ordered list and the indicators of free memory blocks can be placed at the beginning of the ordered list. For another example, each second data entity can be a logical ring and there can be a ring pointer that points to the first one or to the last one of those second data items which contain the indicator of free memory blocks.
An address that identifies the free memory block being allocated is formed at least partly on the basis of (i) the searched first data item ‘0’ which indicates the memory block group having at least one free memory block and (ii) the indicator ‘a’ which identifies the said free memory block from among all the memory blocks of the memory block group under consideration. The address can be, for example, the address of the first row of the memory block being allocated.
Advantageously, the memory block groups are consecutively numbered, and, within each memory block group, the memory blocks are consecutively numbered. In this case, the indicator ‘a’ which identifies the free memory block is advantageously the number of this memory block. For the sake of illustration, we consider a special case where each memory block group has a same number of memory blocks, each memory block has a same size, the memory block groups are located at regular intervals in the address space of the memory, and, within each memory block group, the memory blocks are located at regular intervals in the address space. In this case, the address Addr1 identifying the memory block being allocated can be formed according to the formula:
Addr1=kBG1x SBG+kB1×SB+C, (1)
where kBG1 is the number of the memory block group related to the searched first data entity, kB1 is the number of the free memory block being allocated, i.e. the indicator identifying this memory block, SBG is a difference of mutually corresponding addresses of two successive memory block groups, SB is a difference of mutually corresponding addresses of two successive memory blocks in the memory block group related to the searched first data entity, and C is an offset control parameter which is the value of Addr1 in the situation where SBG=SB=0. The mutually corresponding addresses of the two successive memory block groups can be the addresses of the first rows of the first memory blocks of the two successive memory block groups, and the mutually corresponding addresses of the two successive memory blocks can be the addresses of the first rows of the two successive memory blocks. SBG is the length of the address range of the memory block group when there are no gaps between successive memory block groups. Correspondingly, SB is the length of the address range of the memory block when there are no gaps between successive memory blocks. The formula (1) is straightforward to understand when the memory block groups are consecutively numbered starting from zero, and, within each memory block group, the memory blocks are consecutively numbered starting from zero. In this case, the offset control parameter C can be a base-address which is the address of the first row of the memory block ‘0’ of the memory block group ‘0’. The data structure may further comprise one or more parameters 132 which indicate the above-mentioned SBG and/or SB and/or the base address.
After the address that identifies the memory block being allocated has been formed, it can be delivered to a process from which the request to allocate a free memory block was received. This process can be, for example, a process for queuing and de-queuing data frames, e.g. Internet Protocol “IP” data packets.
When an address identifying a memory block to be released from allocation has been received, the memory block group which contains the memory block to be released is determined on the basis of the said address and information about how the memory has been organized into memory block groups. In this exemplifying case, we assume that the memory block group which contains the memory block to be released is the memory block group related to the first data item ‘N’. Next, the first data item ‘N’ is increased by one up to 5 and, as a corollary, the arrow 107 is shifted to point to the second data item ‘M(N)-5’ of the second data entity 105. An indicator identifying the memory block to be released is determined on the basis of the above-mentioned address and information about how the determined memory block group has been organized into memory blocks. This indicator identifies this memory block from among all the memory blocks of the determined memory block group. Next, an appropriate second data item of the second data entity 105 is updated to contain the indicator identifying the memory block to be released. The first data item ‘N’ was four prior to its above-described update, and thus the second data item ‘M(N)-5’ of the second data entity 105 does not contain an indicator of any other free memory block. Therefore this second data item ‘M(N)-5’ can be used for storing the indicator identifying the memory block to be released. The releasing operation is completed by setting the second data item ‘M(N)-5’ of the second data entity 105 to contain the indicator identifying the memory block to be released.
For the sake of illustration, we consider the special case where each memory block group has a same number of memory blocks, each memory block has a same size, the memory block groups are located at regular intervals in the address space of the memory, and, within each memory block group, the memory blocks are located at regular intervals in the address space. We further assume that the memory block groups are consecutively numbered starting from zero, and, within each memory block group, the memory blocks are consecutively numbered starting from zero. In this case, the number kBG2 of the memory block group, which contains the memory block to be released, can be obtained from the following formula:
where Addr2 is the address identifying the memory block to be released, and “the integer part of” is the greatest integer that is less than or equal to the value under consideration. For example, the integer part of 3.14 is 3 and the integer part of 4.999 is 4. The SBG is the difference of mutually corresponding addresses of two successive memory block groups as in conjunction with the formula (1), and C is the same offset control parameter as in conjunction with the formula (1). The number kB2 of the memory block to be released can be obtained from the following formula:
where SB is a difference of mutually corresponding addresses of two successive memory blocks as in conjunction with the formula (1).
It should be noted that embodiments of the present invention are not limited to the above-mentioned special case where each memory block group has a same number of memory blocks, each memory block has a same size, the memory block groups are located at regular intervals in the address space of the memory, and, within each memory block group, the memory blocks are located at regular intervals in the address space. For example, it is possible that the memory is organized to contain two types of memory block groups so that there is a first set of successively located memory block groups having greater memory blocks and a second set of successively located memory block groups having smaller memory blocks. In this exemplifying case, the above-mentioned formulas (1)-(3) can be applied separately to the first and second sets of memory block groups so that a required address-offset is implemented by giving, in each case, a suitable value to the offset control parameter C.
The processor 201 is configured to carry out the following actions in response to receiving a request to allocate a free memory block:
In a device according an exemplifying embodiment of the invention, the processor 201 is configured to carry out the following actions in response to receiving an address identifying a memory block to be released from allocation:
In a device according an exemplifying embodiment of the invention, the processor 201 is configured to:
In a device according an exemplifying embodiment of the invention, the processor 201 is configured to carry out the following actions in order to search, from the first data entity 101, such a first data item that indicates that there are one or more free memory blocks in the memory block group related to this first data item:
In a device according an exemplifying embodiment of the invention, the processor 201 is configured to carry out the following actions in order to search, from the first data entity 101, such a first data item that indicates that there are one or more free memory blocks in the memory block group related to this first data item:
In a device according an exemplifying embodiment of the invention, the processor 201 is configured to maintain a consecutive numbering of the memory block groups and a consecutive numbering of the memory blocks within each memory block group. The processor is configured to form the address Addr1 identifying the free memory block to be allocated according to the following formula:
Addr1=kBG1×SBG+kB1×SB+C,
where kBG1 is the number of the memory block group related to the searched first data entity, kV1 is the number of the free memory block to be allocated, SBG is a difference of mutually corresponding addresses of two successive memory block groups, SB is a difference of mutually corresponding addresses of two successive memory blocks in the memory block group related to the searched first data entity, and C is an offset control parameter which is the value of Addr1 in the situation where SBG=SB=0.
In a device according an exemplifying embodiment of the invention, the processor 201 is configured to determine the number kBG2 of the memory block group, which contains the memory block to be released, according to the following formula:
where Addr2 is the address identifying the memory block to be released. The processor 201 is configured to determine the number kB2 of the memory block to be released according to the following formula:
In a device according an exemplifying embodiment of the invention, the processor 201 is configured to:
In the above-mentioned exemplifying case, there are 48 memory block groups each containing 15 memory blocks. Each first data item 101 can be four bits because in each memory block group there can be from 0 to 15 free memory blocks and four bits are sufficient for expressing the values from 0 to 15. Each of the second data items 102, 103, 104, . . . , 105 can also be four bits. In this case, the size of the first data entity is 48×4 bits which is 24 bytes, and the size of each second data entity is 15×4 bits which is less than 8 bytes. In a case where a cache line is e.g. 32 bytes, the first data entity 101 fits in a single cache line and four second data entities fit in a single cache line. The whole data structure, i.e. the first data entity and the 48 second data entities, fits in only 13 cache lines. Thus, cache misses are very improbable in allocation and releasing operations, and therefore the cache memory 202 can be effectively utilized.
The processor 201 can be implemented with one or more processor circuits, each of which can be a programmable processor circuit provided with appropriate software, a dedicated hardware processor such as, for example, an application specific integrated circuit “ASIC”, or a configurable hardware processor such as, for example, a field programmable gate array “FPGA”. Furthermore, it is possible that a first processing circuit is configured to allocate memory blocks and a second processing circuit is configured to release the memory blocks from allocation.
The method further comprises carrying out the following actions in response to receiving a request to allocate a free memory block:
A method according to an exemplifying embodiment of the invention comprises carrying out the following actions in response to receiving an address identifying a memory block to be released from allocation:
A method according to an exemplifying embodiment of the invention comprises:
A method according to an exemplifying embodiment of the invention comprises carrying out the following actions in order to search, from the first data entity, such a first data item that indicates that there are one or more free memory blocks in the memory block group related to this first data item:
A method according to an exemplifying embodiment of the invention comprises carrying out the following actions in order to search, from the first data entity, such a first data item that indicates that there are one or more free memory blocks in the memory block group related to this first data item:
In a method according to an exemplifying embodiment of the invention, the memory block groups are consecutively numbered and, within each memory block group, memory blocks are consecutively numbered. The address Addr1 identifying the free memory block to be allocated is formed according to the following formula:
Addr1=kBG1×SBG+kB1×SB+C,
where kBG1 is the number of the memory block group related to the searched first data entity, kB1 is the number of the free memory block to be allocated, SBG is a difference of mutually corresponding addresses of two successive memory block groups, SB is a difference of mutually corresponding addresses of two successive memory blocks in the memory block group related to the searched first data entity, and C is an offset control parameter which is the value of Addr1 in the situation where SBG=SB=0.
In a method according to an exemplifying embodiment of the invention, the number kBG2 of the memory block group, which contains the memory block to be released, is determined according to the following formula:
and the number kB2 of the memory block to be released is determined according to the following formula:
where Addr2 is the second address identifying the memory block to be released.
In a method according to an exemplifying embodiment of the invention, the first data entity contains 48 first data items each of which containing four bits, and each second data entity comprises 15 second data items each of which containing four bits.
A computer program according to an embodiment of the invention comprises software modules for controlling a memory organized to contain a plurality of memory block groups each of which containing a plurality of memory blocks. The software modules comprise computer executable instructions for controlling a programmable processor to:
The software modules further comprise computer executable instructions for controlling the programmable processor to carry out the following actions in response to receiving a request to allocate a free memory block:
In a computer program according to an exemplifying embodiment of the invention, the software modules further comprise computer executable instructions for controlling the programmable processor to carry out the following actions in response to receiving an address identifying a memory block to be released from allocation:
The software modules can be e.g. subroutines or functions implemented with a suitable programming language and with a compiler suitable for the programming language and the programmable processor.
A computer program product according to an embodiment of the invention comprises a computer readable medium, e.g. a compact disc (“CD”), encoded with a computer program according to an embodiment of invention.
A signal according to an embodiment of the invention is encoded to carry information defining a computer program according to an embodiment of invention.
The specific examples provided in the description given above should not be construed as limiting the scope and/or the applicability of the appended claims.
Number | Date | Country | Kind |
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20125118 | Feb 2012 | FI | national |