BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a block diagram illustrating an embodiment of a memory device including a multi-level Content Addressable Memory (CAM) having search abort circuitry.
FIG. 2 is a block diagram partially illustrating an embodiment of a multi-level CAM.
FIG. 3 is a logic flow diagram illustrating an embodiment of program logic for aborting a CAM search operation.
FIG. 4 is a block diagram partially illustrating another embodiment of a multi-level CAM.
FIG. 5 is a circuit diagram illustrating an embodiment of a zero-catcher monotonic storage device.
FIG. 6 is a block diagram illustrating an embodiment of a microprocessor including a multi-level CAM.
DETAILED DESCRIPTION
FIG. 1 illustrates an embodiment of a memory device 10 such as a cache including a multi-level Content Addressable Memory (CAM) 12, a holding register 14 and a Random Access Memory (RAM) 16 such as a Dynamic RAM (DRAM), Static RAM (SRAM) or embedded-DRAM (e-DRAM). The multi-level CAM 12 has multiple memory cells (not shown) such as binary or ternary CAM cells for storing data. The CAM cells are arranged in groups 18, e.g., rows, where each group 18 is coupled to a Global Match Line (GML0-GMLn). Each GML indicates whether its corresponding group 18 of CAM cells contains a data sequence that matches a search field provided to the CAM 12. That is, the GMLs indicate whether a data sequence stored by the CAM 12 matches a search field input (hit) or mismatches (miss). In one embodiment, each GML coupled to a group 18 of CAM cells containing a matching data sequence is activated. In another embodiment, each GML coupled to a group 18 of CAM cells containing a non-matching data sequence is activated. In the present context, ‘activate’ corresponds to setting the state of the GMLs to indicate CAM search results, e.g., by discharging pre-charged GMLs or charging pre-discharged GMLs. Regardless, precharge and evaluation circuitry 20 coupled to each group of CAM cells 18 has search abort circuitry 22 included in or associated therewith for preventing activation of the GMLs in response to a search abort signal (ABORT). As such, a CAM search operation may be aborted before the GMLs are activated, thus enabling the holding register 14 to retain prior CAM search results.
In more detail, the multi-level CAM 12 is provided a search field such as an address during a search portion of a memory access. The CAM 12 searches each group 18 of memory cells for a stored data sequence that matches the search field. Each GML associated with a group 18 of CAM cells that contains a matching data sequence is activated by the precharge and evaluation circuitry 20 in one embodiment while each GML associated with a group 18 of CAM cells that contains a non-matching data sequence is activated in another embodiment. The state of each GML is captured by the holding register 14 (hit/miss). The holding register 14 comprises high-performance monotonic storage devices (not shown) such as zero-catcher latches, one-catcher latches, or jam latches. As such, the holding register 14 is capable of capturing the activation state of GMLs without regard to a clock signal input. That is, the monotonic storage devices sense GML activation regardless of clock signal transitions, thus enabling the holding register 14 to capture GML activation states near instantaneously. During a read portion of the memory access, each entry 24 in the RAM 16 associated with a ‘hit’ result stored in the holding register 14 is accessed and the corresponding data read.
In response to a search abort signal, the search abort circuitry 22 prevents the GMLs from activating during a CAM search operation. Aborting a CAM search operation before the GMLs are activated prevents the contents of the holding register 14 from being altered by the monotonic storage devices that form the storage elements of the holding register 14. As such, monotonic storage devices may be incorporated in the holding register 14 to improve performance while the search abort circuitry 22 preserves hit/miss search results presently stored in the holding register 14 in response to a search abort signal. Absent the search abort circuitry 22, the holding register 14 overwrites prior hit/miss search results each time a GML is activated.
FIG. 2 is a partial illustration of one embodiment of the multi-level CAM 12. Individual CAM cells 26 are arranged into N groups 18, e.g., rows, where each group 18 is coupled to a Local Match Line (LML). The LMLs indicate whether their corresponding group 18 of CAM cells yields a match (hit) or mismatch (miss) in response to a search field or a portion of a search field provided to the CAM 12. Each LML is coupled to an instantiation of the precharge and evaluation circuitry 20. The output of each instantiation of the precharge and evaluation circuitry 20 are coupled together to form one of the GMLs (GML0) of the CAM 12. Although not illustrated, numerous other GMLs may be formed in a like manner. For example, a 64-entry CAM may have 64 GMLs (one for each CAM entry). The search abort circuitry 22 associated with each LML prevents GML0 from activating in response to a search abort signal (ABORT), thus preserving the current state of GML0 as stored in the holding register 14.
In one embodiment, the precharge and evaluation circuitry 20 includes a LML precharge circuit (p-FET T1), an inverter (p-FET T2 and n-FET T3), a GML precharge circuit (p-FET T4), and a GML discharge circuit (n-FETs T5 and T6). For ease of explanation only, reference is made hereinafter to pre-charging of match lines and activating the pre-charged match lines by discharging them. However, those skilled in the art will readily recognize that a match line may be pre-discharged and subsequently activated by being charged. With this understanding, a CAM search operation begins with the LML pre-charge circuit pre-charging each LML associated with GML0 to Vdd, as illustrated by Step 100 of FIG. 3. In addition, the GML pre-charge circuit pre-charges GML0. The LMLs and GML0 may be pre-charged in response to the same precharge signal (PRECHARGE) as illustrated in FIG. 2, or alternatively, may be pre-charged in response to separate signals. Once pre-charged, each LML is ready for activation by its corresponding group 18 of CAM cells. A search field is provided to the CAM 12, as illustrated by Step 102 of FIG. 3. Each group 18 of CAM cells storing a data sequence not matching the search field activates its corresponding LML by discharging it, as illustrated by Step 104 of FIG. 3. Otherwise, the LMLs remain in their pre-charged state in response to a search hit.
Regardless of the underlying organization of the multi-level CAM 12, each LML coupled to an instantiation of the precharge and evaluation circuitry 20 remains in its pre-charged high state unless one of the LMLs is activated in response to a search mismatch. If one or more of the LMLs is activated and thus discharged, the input to the inverter of the precharge and evaluation circuitry 20 is driven to a logic-low level. Otherwise, the inverter input remains at the pre-charged state. The search abort circuitry 22 determines whether the present CAM search operation should be aborted in response to a search abort signal, as illustrated by Step 106 of FIG. 3. In one embodiment, the search abort circuitry 22 comprises logic AND gate circuitry 27 that uses the abort signal, e.g., an activated late select signal, to gate a clock signal input (CLK) to the GML discharge circuit. Those skilled in the art will readily recognize that the search abort circuitry 22 may comprise other circuitry for gating the clock signal input to the GML discharge circuit such as logic NAND gate circuitry (not shown).
Regardless, if the abort signal is active, e.g., at a logic high value, the search abort circuitry 22 blocks the clock signal from enabling the GML discharge circuit, thus preventing GML0 from being activated in the event of a CAM search mismatch. That is, when the second transistor T6 of the GML discharge circuit is disabled by the search abort circuitry 22, GML0 cannot be discharged to Vss since its discharge path is blocked. As a result GML0 remains in its pre-charged state, as illustrated by Step 108 of FIG. 3. Conversely, if the abort signal is not active, the search abort circuitry 22 passes the clock signal to the GML discharge circuit, thus enabling it, as illustrated by Step 110 of FIG. 3. When enabled, the GML discharge circuit activates GML0 in the event of a CAM search mismatch by discharging GML0 to Vss, as illustrated by Step 112 of FIG. 3. The CAM search operation then ends, as illustrated by Step 114 of FIG. 3. The program logic illustrated in FIG. 3 enables the multi-level CAM 12 to activate LMLs in response to a search field input without activating a corresponding GML unless the discharge circuit associated with the GML is enabled. Until then, the GML remains in its pre-charged state, unaffected by the search results produced by the corresponding LMLs. In turn, the monotonic storage devices included in the holding register 14 do not alter previously stored data.
FIG. 4 is a partial illustration of one embodiment of the multi-level CAM 12 wherein the CAM 12 has two hierarchical match line levels 28-30 coupled to a GML (GML0). Although not illustrated, numerous other GMLs may be formed in a like manner. With this in mind, the first hierarchical level 28 receives various LML inputs (LML0-LML15), the LMLs being coupled to respective groups of CAM cells (not shown). The search abort circuitry 22 controls whether corresponding intermediary match lines (IML0-IML1) are activated or not in response to the activation state of the LMLs, a clock signal input (CLK) and a search abort signal (ABORT) as previously described. The intermediary match lines are then input to a second hierarchal level 30, where they are gated by the search abort circuitry 22. The search abort circuitry 22 included in or associated with the second hierarchal level 30 controls whether GML0 is activated or not in response to the activation state of IML0 and IML1. Thus, activation of GML0 may be prevented by blocking activation of the intermediary level 28 of match lines or the global match line level 30. Regardless of the number of intermediary match line levels, the monotonic storage devices included in the holding register 14 do not alter previously stored data if the search abort circuitry 22 prevents the GMLs of the multi-level CAM 12 from activating.
FIG. 5 illustrates an embodiment of a zero-catcher latch 40 included in the holding register 14 for capturing GML activation states (hit/miss results). The zero-catcher latch 40 captures a logic one input during an active portion of a clock signal input (MCLK) and captures a logic zero without regard to the clock signal. The zero-catcher latch 40 comprises an input inverter (p-FET T7 and n-FET T8), latch circuitry (p-FETs T9-T11 and n-FETs T12-T14) and an output inverter (p-FET T15 and n-FET T16). When MCLK is inactive, the latch circuitry stores the data value currently captured by the zero-catcher latch. Transistor T12 coupled between Vss and the input inverter prevents the input inverter from inverting a logic one unless MCLK is active. However, the inverter inverts a logic zero regardless of the state of MCLK, hence the name ‘zero-catcher’. However, the search abort circuitry 22 prevents activation of the GML input (GML0) to a logic zero state when the search abort signal is active, thus preventing the zero-catcher latch 40 from capturing a logic zero GML state. The output inverter inverts the data stored by the latch circuitry, thus yielding the opposite signal level (GML0_HOLD) as the data originally provided to the zero-catcher input inverter (GML0). Those skilled in the art will readily recognize that one-catcher latches (not shown) could be used in place of zero-catcher latches if the multi-level CAM 12 yields activated GMLs by charging pre-discharged GMLs instead of discharging pre-charged GMLs. A one-catcher latch functions much the same way as the zero-catcher latch 40 except that a one-catcher latch captures logic one input signals notwithstanding the state of a clock signal input instead of logic zero input signals. Regardless of the particular monotonic storage device used, data stored in the holding register 14 will not be overwritten by the multi-level CAM 12 when the abort signal is activated during a CAM search operation, thus preserving data previously stored by the holding register 14.
FIG. 6 illustrates an embodiment of a processor 50 that includes an instruction unit 52, one or more execution units 54 and a bus interface unit 56. The instruction unit 52 provides centralized control of instruction flow to the execution units 54. The execution units 54 execute instructions dispatched by the instruction unit 52 and the bus interface unit 56 provides a mechanism for transferring data, instructions, addresses, and control signals to and from the processor 50. The processor 50 also includes an instruction cache 58, a data cache 60 and a higher-level cache (L2 cache) 62. The instruction and data caches 58, 60 store instructions and data, respectively. The L2 cache 62 provides a high-speed memory buffer between the data and instruction caches 58, 60 and memory (not shown) external to the processor 50.
The caches 58, 60 and 62 included in the processor 50 have a CAM portion 12, a RAM portion 16 and a holding register 14. Each CAM 12 returns a list of one or more matching addresses corresponding to a search field supplied to it. A matching memory address, represented as a hit/miss entry or an encoded memory address stored in the respective holding registers 14, is provided to a corresponding RAM 16. Each RAM 16 returns data stored at the memory address supplied to it. In the event of a cache miss, a higher-level memory transaction occurs to retrieve the desired data.
Search abort circuitry 22 included in or associated with the CAMs 12 prevents activated LML results from propagating to corresponding GMLs. As such, data previously stored in the holding registers 14 is preserved in response to a search abort signal as previously described. The search abort signal may be generated by the processor 50, received by the processor 50 as part of an instruction stream, or received by the processor 50 as an external signal input. Regardless, monotonic storage devices (not shown) included in the holding registers 14 improve processor performance while the search abort circuitry 22, in response to a search abort signal, prevents the monotonic storage devices from overwriting hit/miss search results presently stored by the corresponding holding registers 14.
With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
Patent Application
20080031040
