Claims
- 1. An adaptive receiver that receives an optical signal, said receiver comprising:
at least one optical device for compensating distortion in a channel of the optical signal that has been transmitted through a fiber; at least one photodetector circuit for converting said optical signal into an electrical signal; at least one electronic device for further compensating the distortion in the electronic signal; a clock and data recovery circuit for generating a recovered data signal and a clock signal from said electronic signal; and a post-processing circuit for error-correction in said recovered data signal.
- 2. An adaptive transceiver comprising:
an adaptive receiver that receives an optical signal, said receiver comprising:
at least one optical device for compensating distortion in a channel of the optical signal that has been transmitted through a fiber, at least one photodetector circuit for converting said optical signal into an electrical signal, at least one electronic device for further compensating the distortion in the electronic signal, a clock and data recovery circuit for generating a recovered data signal and a clock signal from said electronic signal, and a post-processing circuit for error-correction in said recovered data signal; and an adaptive transmitter for converting said error-corrected recovered data signal into a second optical signal, said transmitter comprising a controllable polarization scrambler.
- 3. The transceiver of claim 2 wherein said at least photodetector circuit comprises:
at least one photodetector, wherein said photodetector generates at least one electrical signal; and at least one front-end amplifier for amplifying said electrical signal.
- 4. The transceiver of claim 3 wherein said front-end amplifier comprises an amplifier selected from a group consisting of a trans-impedance amplifier, a series of linear amplifier stages, and a combination thereof.
- 5. An adaptive transceiver comprising:
at least one adaptive optical distortion compensator having an optical compensator input and an optical compensator output; a photodetector circuit having a circuit input and a circuit output, said circuit comprising:
a photodetector, and a trans-impedance amplifier coupled in series to the photodetector, wherein said circuit input is coupled to said optical compensator output; at least one adaptive electronic equalizer having an equalizer input and an equalizer output, wherein said equalizer input is coupled to said circuit output; an eye opening measurement circuit for measuring an eye opening along at least one dimension to generate dimensional information, said measurement circuit comprising a measurement circuit input and a measurement circuit output, wherein said measurement circuit input is coupled to said at least one adaptive electronic equalizer; an adaptive decision unit for converting analog data to digital data using said dimensional information, wherein said adaptive decision unit comprises a decision unit input and a decision unit output, and wherein said decision unit input is coupled to said equalizer output, through which said dimensional information is provided; a clock and data recovery circuit for providing at least one recovered clock signal with an adjustable phase and a recovered data signal, wherein said recovery circuit comprises a recovery circuit input and a recovery circuit output, and wherein said recovery circuit input is coupled to said decision unit output and wherein said recovery circuit output is coupled to said measurement circuit input for providing said data signal to said measurement circuit for comparison; a post-processing IC for processing said dimensional information and providing feedback control signals to a compensating device selected from a group consisting of said at least one adaptive optical distortion compensator and said least one adaptive electronic equalizer; an optical source capable of generating an optical signal that can be modulated in response to receiving said recovered data signal, wherein said source comprises a source input and a source output; and a polarization scrambler, having a scrambler optical input coupled to said optical source output for providing a polarization-scrambled optical output signal.
- 6. The adaptive transceiver of claim 5 wherein said polarization scrambler comprises an optical polarization controller with a randomized control input.
- 7. The adaptive transceiver of claim 5 wherein said at least one adaptive optical distortion compensator is selected from a group consisting of a chromatic dispersion compensator, a polarization modes dispersion compensator, and a combination thereof.
- 8. The adaptive transceiver of claim 5 wherein said at least one adaptive electronic equalizer is selected from a group consisting of a transversal equalizer, a decision feedback equalizer, and a combination thereof.
- 9. The adaptive transceiver of claim 5 wherein said eye opening measurement circuit comprises an error measurement circuit.
- 10. The adaptive transceiver of claim 9 wherein said error measurement circuit generates error information for two eye opening dimensions.
- 11. The adaptive transceiver of claim 5 wherein said eye opening measurement circuit measures an eye opening along two dimensions to generate two dimensional parameters.
- 12. The adaptive transceiver of claim 5 wherein said adaptive decision unit converts analog data to digital data by adaptively adjusting at least one decision variable consisting of a threshold and a sample time.
- 13. The adaptive transceiver of claim 5 wherein said clock and data recovery circuit provides four recovered clock signals having an adjustable quadrature phase.
- 14. The adaptive transceiver of claim 5 wherein said post-processing IC comprises a digital signal processor.
- 15. The adaptive transceiver of claim 5 wherein said dimensional information comprises error information.
- 16. The adaptive transceiver of claim 15 wherein said dimensional information comprises error information for two dimensions.
- 17. The adaptive transceiver of claim 5 wherein said post-processing IC delivers all adaptive feedback signals for an automatic gain controller, a chromatic dispersion compensator, a polarization mode dispersion compensator, a feed-forward equalizer, a decision feedback equalizer, a decision threshold and sample time controller.
- 18. A sample time measurement unit comprising:
a left edge detector comprising:
a left delay unit; for varying the phase of a left clock signal, a left comparator unit which compares a recovered data signal with a left error signal based on said left clock signal, and a left error counter for accumulating errors in said left error signal; and a right edge detector comprising:
a right delay unit for varying the phase of a right clock signal, a right comparator unit which compares a recovered data signal with a right error signal based on said right clock signal, and a right error counter for accumulating errors in said right error signal.
- 19. An error detection circuit for analyzing a data eye opening along both time and amplitude dimensions, said detector comprising:
a sample time measurement unit comprising:
a left edge detector comprising:
a left delay unit for varying the phase of a left clock signal, a left comparator unit which compares a recovered data signal with a left error signal based on said left clock signal, and a left error counter for accumulating errors in said left error signal; and a right edge detector comprising:
a right delay unit for varying the phase of a right clock signal, a right comparator unit which compares a recovered data signal with a right error signal based on said right clock signal, and a right error counter for accumulating errors in said right error signal; and a threshold measurement unit.
- 20. A clock and data recovery circuit for generating at least one clock signal and a recovered data signal, wherein each of said clock signals has a phase, and wherein said circuit comprises:
a phase detector for providing phase error information; a low-pass loop filter for determining a loop performance and generating a filtered error signal; a voltage controlled oscillator for generating a sinusoidal waveform in response to receiving said filtered error signal; and a tunable delay unit for tuning said phases of said clock signals.
- 21. The circuit of claim 20 wherein said phase detector comprises at least one D-type flip-flop.
- 22. The circuit of claim 21 wherein said phase detector comprises four D-type flip-flops.
- 23. The circuit of claim 20 wherein said phase error information comprises a voltage error signal, and wherein said circuit further comprises a charge pump for converting said voltage error signal into a current signal.
- 24. The circuit of claim 20 wherein said low-pass loop filter determines a phase lock loop performance.
- 25. The circuit of claim 24 wherein said low-pass loop filter determines a clock jitter performance of a clock and data recovery unit.
- 26. An integrated apparatus comprising:
an error detector for generating an error signal; a transversal equalizer for electronic distortion compensation; a decision circuit having an embedded decision feedback equalizer for further electronic distortion compensation; and an adaptive gain and threshold controller for controlling said equalizers based on said error signal.
Parent Case Info
[0001] This application claims the benefit of U.S. Provisional Application No. 60/296,551 filed Jun. 7, 2001.
Provisional Applications (1)
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Number |
Date |
Country |
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60296551 |
Jun 2001 |
US |