Claims
- 1. A method of addressing a memory having M banks using a memory controller configured to address N banks, M being larger than N, the method comprising:
- in an activate portion of a memory address sequence in a memory controller configured for N banks;
- generating a N bank memory first bank select;
- generating a N bank memory first row address;
- saving said N bank memory first row address as a M bank memory second bank select; and
- identifying a bank of the M bank memory in response to
- said N bank memory first bank select and said M bank memory second bank select.
- 2. The method of claim 1 further comprising:
- in an access portion of the memory address sequence in said memory controller configured to address N banks;
- generating a N bank memory first bank select;
- retrieving said saved M bank memory second bank select; and
- identifying a bank of the said M bank memory in response to
- said N bank memory first bank select and said M bank memory second bank select.
- 3. The method of claim 1 wherein said saving of said N bank memory first row address as a M bank memory second bank select comprises saving said M bank memory second bank select as a function of
- said N bank memory first bank select.
- 4. The method of claim 2 wherein said retrieving of said saved M bank memory second bank select comprises retrieving said M bank memory second bank select based on a value of said N bank memory first bank select.
- 5. A system including:
- a memory controller configured to address N banks and a memory having M banks, M being larger than N, the memory controller generating a N bank memory first bank select and a N bank memory row address identifying one or more rows in a selected bank; and,
- a storage device for storing said N bank memory row address and presenting said N bank memory row address as a M bank memory second bank select to identify a bank of the said M bank memory.
- 6. The system of claim 5 wherein said storage device presents said M bank memory second bank select during an activation portion of a memory access sequence.
- 7. The system of claim 5 wherein said storage device presents said M bank memory second bank select during an access portion of a memory access sequence.
- 8. The system of claim 5 wherein said storage device stores two M bank memory second bank selects; said M bank memory second bank select and an additional M bank memory second bank select, said improvement further comprising:
- a switching device for selecting between the two said M bank memory second bank selects to identify a bank of the M bank memory.
- 9. The system of claim 8 wherein said switching device is responsive to said N bank memory first bank select.
- 10. The method of claim 1 wherein N is equal to two and M is equal to four.
- 11. The system of claim 5 wherein N is equal to two and M is equal to four.
Parent Case Info
This application is a continuation of pending application Ser. No. 08/892,627, filed Jul. 14, 1997.
US Referenced Citations (3)