Patent Application
20080191923
This application claims priority under 35 U.S.C. §119(a) to an application entitled “Method and Apparatus for Analog-to-Digital Conversion Using Switched Capacitors” filed in the Korean Industrial Property Office on Feb. 13, 2007 and assigned Serial No. 2007-0015051, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to analog-to-digital conversion, and more particularly, to an Analog-to-Digital Converter (ADC) using switched capacitors for quantizing an input current, and a method for analog-to-digital conversion corresponding to such an ADC.
2. Description of the Related Art
Digital signal processing has been widely used throughout the industry in various application fields. Digital signal processing typically operates on a digital signal obtained from an analog signal. The conversion of an analog signal into a digital signal is often performed by an ADC.
An ADC refers to an apparatus that is input with an analog signal in the form of a continuously varying physical quantity, and converts the input analog signal into a digital signal in the form of a discretely varying physical quantity. The types of ADCs include a parallel comparator type ADC, a flash ADC, a pipelined ADC, an algorithmic ADC, a successive approximation ADC, and so forth.
In the parallel comparator type ADC, an analog input voltage is applied to a plurality of comparators, the number of which is 2n−1. Here, “n” is the number of digital bits to be generated. Different reference voltages in a range from the highest expected voltage to the lowest expected voltage are applied to the respective comparators. Also, outputs of the respective comparators are logically synthesized to thereby generate i digital bits.
Analog-to-digital conversion is an electronic process of continuously converting an analog signal into a multi level discretely varying digital signal without changing essential contents, and the ADC converts an analog signal into a signal that has discrete levels or states, that is, a digital signal.
The discrete states are represented by a combination of one or more binary digits (bits). The number of the states is always equal to a power of 2, including 2, 4, 8, 16, etc. The simplest digital signal has only two states (either “0” or “1”) that are called a binary signal.
In various aspects, digital signals are generally more suitable for signal processing in most communication applications than analog signals, which results from the following two factors.
First, digital signals have a high error margin as compared to analog signals. Digital signals are in the form of well-defined orderly digital impulses. Moreover, most electronic circuits easily discern digital signals from noise.
Secondly, while a considerable number of error detection and correction schemes have evolved toward digital signals, there is substantially no error detection and correction scheme for analog signals. Moreover, the most recent technologies in communication applications convert analog data into digital data for the purpose of data transmission.
In addition, all computers perform processing in the format of binary digital signals. These computers also use a plurality of applications requiring interactions with analog interfaces.
Some examples of such applications include voice processing, digital signal processing, modems, and the like.
In order to handle these applications, computers must convert analog signals into digital signals. The use of computers for handling these applications has increased the necessity of analog-to-digital conversion.
If an input signal is of analog form, an ADC is generally required in all digital signal processing systems. Some examples of ADC-based applications include phone modems, xDSL (x Digital Subscribe Line) modems, and cellular phones. Typical phone modems use an ADC to transform audio, input from a twisted pair line, into a computer-processable form.
Many ADC architectures are well known. Different ADC architectures provide different gains in conversion speed, conversion resolution, implementation cost (or complexity), power consumption, etc.
In a typical ADC architecture called a flash ADC, an input signal is compared to a reference voltage, and a result of the comparison is decoded into a digital signal. The flash ADC architecture converts an analog signal into a digital signal by using a series of comparators with different threshold voltages.
The flash ADC architecture uses the fastest ADC technology. However, a number of comparators (2.sup.N comparators) are required to implement a flash ADC. Here, “N” is the number of bits of resolution. The resolution of an ADC may be defined by the number of bits, each of which is representative of each sample of a digital signal corresponding to an analog signal. As a result of using 2.sup.N comparators for N-bit resolution, the number of comparators exponentially increases with an increase in resolution. Thus, power consumption also exponentially increases with an increase in resolution. Moreover, flash ADCs have a drawback in that high power consumption and cost are required for their circuit implementations. Although many architectures are proposed for improving flash ADCs, most of them are limited to 8-bit resolution so as to provide appropriate performance.
A well-known ADC architecture other than the above-mentioned flash ADC architecture is a pipelined ADC.
Pipelined ADCs are performed together using cascaded multiple stages. Each of the multiple stages is performed using a 2-step flash ADC. Pipelined ADCs are implemented with a lower cost than flash ADCs. Also, pipelined ADCs exhibit less complexity than flash ADCs while providing similar resolution to flash ADCs. Further, pipelined ADCs have lower power drain than flash ADCs. However, pipelined ADCs cause a considerable delay between an analog sample of an analog signal and a digital value representative of the analog sample. The delay interval depends on the number of pipelined stages. Another drawback of pipelined ADCs is that conversion speed decreases with an increase in conversion resolution.
In the pipelined ADC architecture, conversion speed decreases as input stages increase so as to provide more accurate processing for an input signal, which results from the setting time of an amplifier. To address such a drawback, time interleaving technology for multiple pipelined ADCs has been proposed.
However, the time interleaving technology is restricted by sampling intervals related to other stages, relative gain and offset match, and the accuracy of timing jitter of sampling clocks.
Another type of ADC architecture is a successive approximation ADC. The successive approximation ADC considers high resolution. However, the successive approximation ADC has low speed because it typically requires N cycles for performing analog-to-digital conversion with N-bit resolution.
Therefore, a high-speed ADC architecture is employed in a folding ADC.
Folding ADC technology is used for implementing high-speed ADC technology. Here, the folding ADC technology refers to technology for generating a folded signal, that is, technology for replicating an input signal using a plurality of folding amplifiers.
A digital output signal is produced by detecting a zero crossing of the folding amplifiers. Although folding ADCs are faster than successive approximation ADCs, the folding technology requires many amplifiers for implementing high resolution. This results in relatively high power consumption. Also, the main disadvantage of the folding ADC is that a bandwidth is reduced due to the internal multiplication of an input signal frequency considered by a folding rate.
The number of folding amplifiers may be reduced using interpolation, but the interpolation used as folding restricts the dynamic range of an ADC.
Another famous type of ADC architecture is a sigma-delta ADC. The sigma-delta ADC allows higher resolution (10 to 24 bits). However, such an ADC is relatively slow because requisite level resolution is performed by oversampling of an input signal and noise shaping.
Further, the performance of the sigma-delta ADC is affected directly by an oversampling rate used by the ADC. A sigma-delta ADC used for an advanced wideband application is largely divided into two types, that is, a multi-bit sigma-delta ADC and a continuous time sigma-delta ADC.
The multi-bit sigma-delta ADC does not require a high sampling rate, but has high power dissipation (about 40 to 50 mWin W-CDMA). Contrarily, the continuous time sigma-delta ADC is low in analog power dissipation (less than 5 mW), but has a high sampling frequency (300 Mhz), which causes an increase in power dissipation.
Thereupon, there is a need for an ADC that provides high conversion resolution and does not require a high oversampling rate. Additionally, there is a need for an ADC with low power dissipation.
Further, an ADC with less hardware complexity and cost for implementation is needed. Power consumption and implementation cost are very important elements of ADC applications. As described above, ADC technology is a requisite and an important technology in signal processing in communication systems.
The present invention has been made to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an aspect of the present invention provides a method and apparatus for analog-to-digital conversion, which has low power consumption and is easy to implement in a CMOS process.
According to one aspect of the present invention, an apparatus is provided for analog-to-digital conversion. The apparatus includes a plurality of charge units configured for being input with a current signal in an analog form, being sequentially charged with the input current signal, and providing a high-level or low-level signal to each next sequentially connected charge unit according to whether or not the corresponding charged charge unit is charged above a predetermined threshold value. The apparatus also includes a latch register for receiving the high-level or low-level signals output from the plurality of charge units, converting the received high-level or low-level signals into a linear code, and outputting the converted linear code. Preferably, the high-level signal is used for starting to charge each charge unit connected next to each charged charge unit.
According to another aspect of the present invention, a method for analog-to-digital conversion is provided. A plurality of charge units are sequentially charged with an input current signal in an analog form. A high-level or low-level signal is provided to each charge unit connected next to each charged charge unit according to whether or not the corresponding charged charge unit is charged above a predetermined threshold value. The high-level or low-level signals output from the plurality of charge units are received, the received high-level or low-level signals are converted into a linear code, and the converted linear code is output. Preferably, the high-level signal is used for starting to charge each charge unit connected next to each charged charge unit.
The above and other aspects, features and advantages of the present invention will be more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:
Preferred embodiments of the present invention are described in detail with reference to the accompanying drawings. In the following description, the same or similar elements are designated by the same reference numerals although they are shown in different drawings. Detailed descriptions of constructions or processes known in the art may be omitted to avoid obscuring subject matter of the present invention.
The ADC 100 according to the first embodiment of the present invention includes: an analog signal input terminal 102; a start signal input terminal 110; a sample-and-hold circuit 106 for being input with an analog signal through the analog signal input terminal 102 and sampling/holding the input analog signal; a voltage-to-current converter 108 for converting a voltage into a current; a plurality of capacitors C1 to Cn 138, 140, 142, 144 for being charged with electric charges corresponding to the amount of current output from the voltage-to-current converter 108; a plurality of switches SW1 to SWn 122, 124, 126, 128 for preventing the capacitors C1 to Cn 138, 140, 142, 144 from being simultaneously charged; a plurality of reset switches R_SW1 to R_SWn 146, 148, 150, 152 for discharging voltages charged in the capacitors C1 to Cn 138, 140, 142, 144; a plurality of comparators Cmp
A sample of the analog signal input through the analog signal input terminal 102 is obtained from the rising edge of the start signal input through the start signal input terminal 110 using the sample-and-hold circuit 106. The voltage-to-current converter 108 supplies a constant current in proportion to a voltage maintained by the sample-and-hold circuit 106.
The implementation of the sample-and-hold circuit 106 and the voltage-to-current converter 108 is well known in the art. Also, in the present invention, it is assumed that any delay due to the sample-and-hold circuit 106 and the voltage-to-current converter 108 is negligible.
The delay element 112 is used for generating an internal clock corresponding to a replica of the start signal, which is delayed by the conversion time Tcnv. That is, the delay element 112 delays the start signal by Tcnv to thereby generate a clock signal for allowing the n-bit latch register 114 to store the output values D1 to Dn from the plurality of comparators 130, 132, 134, 136. Logical signals output from the comparators 130, 132, 134, 136, that is, D1 to Dn, are latched in the n-bit latch register 114 by the rising edge of the clock signal generated in the delay element 112. The conversion time is a time taken to convert the analog signal into a digital signal.
In other words, the delay element 112 delays the start signal until the capacitors C1 to Cn 138, 140, 142, 144 are charged with electric charges corresponding to the amount of current of the analog signal, and the output values from the comparators 130, 132, 134, 136 are stored in the latch.
The inverter 120 is used to generate an internal reset signal for resetting the capacitors 138, 140, 142, 144 from the signal input through the start signal input terminal 110. That is, the inverter 120 generates a reset signal for operating the reset switches 146, 148, 150, 152 to thereby discharge all the capacitors that have been charged before a new start signal is input. When the start signal is changed to “low”, the reset signal is in an active state (at a high-logic level) by the inverter 120, which turns on the reset switches R_SW1 to R_SWn 146, 148, 150, 152 to thereby discharge the capacitors 138, 140, 142, 144 through the reset switches R_SW1 to R_SWn 146, 148, 150, 152.
Although the internal clock and reset signals generated in the delay element 112 and the inverter 120 respectively are described as originating form the start signal in this embodiment of the present invention, they may also be generated by any other element or from an external signal.
The delay element 112 and the inverter 120 will be described in detail below with reference to a timing chart of
The principle of analog-to-digital conversion according to the present invention is based on a sequential charging series of capacitors C1 to Cn 138, 140, 142, 144 with the same capacitance value, which are sequentially charged with a constant current. The switches SW1 to SWn prevent the capacitors C1 to Cn from being simultaneously charged. During the time when the charged voltage of a previous capacitor is less than a threshold voltage Vth of each comparator Cmp
If each capacitor can store electric charges, the quantity of which is qcap, when being charged with a maximum voltage Vcap, then the total quantity of electric charges, Qtotal, stored from a current source Isource 118 that is output from the voltage-to-current converter 108 during the conversion time Tcnv can be calculated by Equation (1):
Q
total
=I
source
*T
cnv (1)
Also, if the number of capacitors fully charged during the conversion time Tcnv is N, Qtotal can be calculated by Equation (2):
Q
total
=q
cap
*N (2)
Further, N, that is, the number of capacitors fully charged during the conversion time Tcnv, can be calculated by Equation (3) derived from Equations (1) and (2):
N=I
source
*T
cnv
/q
cap (3)
In addition, the number of fully charged capacitors is proportional to the current source Isource. The number of fully charged capacitors is stored in the output latch, that is, the n-bit latch register 114, in a linear form corresponding to a result of the conversion. A result of the conversion represents the magnitude of a digitized signal. That is, it represents a digital value according to how many capacitors are charged. For example, if three capacitors are charged, a result of the conversion has a linear code value of “111”, which is equivalent to binary “11”. Of course, if eight capacitors are charged, a result of the conversion has a linear code value of “11111111” equivalent to binary “100”.
In the first embodiment, all the switches SW1 to SWn have a common connection point (i.e., all the switches SW1 to SWn are connected with the voltage-to-current converter 108 at any one point). However, in the second embodiment, the switches SW1 to SWn have no common connection point (i.e., the end point of one switch is connected with the beginning point of a next switch).
In the first embodiment, the current from the voltage-to-current converter 108 has only to pass through a single switch for each capacitor when the corresponding capacitor is charged. Contrarily, in the second embodiment, the current must pass through N switches until it reaches the nth capacitor.
Assuming that each of the switches is an ideal switch with a resistance of 0 ohm, the first and second embodiments of the present invention have no difference in functionality. However, if the switches are transistors that are actually manufactured in a CMOS process, they probably have a small resistance value. When a current “I” passes through a resistance “R”, a voltage drop of “V=I*R” occurs. Thus, the same voltage drop occurs for all the capacitors in the first embodiment, but different voltage drops occur for the respective capacitors in the second embodiment. This means that the respective capacitors in the second embodiment are charged with different levels of voltage and different quantity of electric charges. However, the main principle of analog-to-digital conversion (more exactly analog-to-linear code conversion) according to the present invention requires all the capacitors to be charged with the same quantity of electric charges. Therefore, when the present invention is implemented using transistors, the first embodiment is advantageous over the second embodiment.
Hereinafter, a more detailed description will be given of a procedure where the capacitors C1 to Cn are charged by the current source Isource 118, and the number of the charged capacitors is stored in the n-bit latch register 114 in
First, since the inverter 120 is at a high level before any start signal is input through the start signal input terminal 110, it turns on all the reset switches R_SW1 to R_SWn, thereby discharging all the capacitors. Then, a start signal is input through the start signal input terminal 110, and the sample-and-hold circuit 106 outputs an analog signal, input through the analog signal input terminal 102, to the voltage-to-current converter 108, which in turn outputs a converted current Isource. The start signal input through the start signal input terminal 110 is applied to the switch SW1 122 to thereby turn on the switch SW1 122, and the delay element 112 delays the start signal by the conversion time Tcnv and then generates a clock for operating the n-bit latch register 114 to store a value (linear code value) output from the comparator. Also, if the start signal is input through the start signal input terminal 110, the inverter 120 outputs a low-level signal, and thus the reset switches R_SW1 to R_SWn 146, 148, 150, 152 are all turned off.
If the capacitor C1 138 is fully charged after the switch SW1 122 is turned on, the comparator Cmp
Once the capacitor C2 140 is charged, the comparator Cmp
After the final comparator Cmp
The delay element 112 generates a clock signal, necessary for storing the output values D1 to Dn, from the start signal input through the start signal input terminal 110, and a delay time for generating the clock signal by delaying the start signal may be determined by the ADC conversion time Tcnv.
In the embodiments of the present invention, Tcnv may be set to different values according to designers of ADC circuits. For example, if a maximum current processable by an ADC circuit is predefined, and a relation between charging and a current, the inherent capacitance of each capacitor, etc, are known, the number of fully chargeable capacitance can be known, and thus a point of time when the n-bit latch register 114 reads the output values D1 to Dn from the comparators can also be known. Additionally, in the specification, the capacitors, the switches, the reset switches, and the comparators are generally referred to as “charge units”.
Similarly, the capacitor C2 212 is charged after the switch SW2 204 is turned on, the comparator Cmp
The above-mentioned operation is repeatedly performed over the circuit portions covering SW3 206 to SWn 208, Cn−1 214, Cn 216, Cmp
Upon storing the output values D1 to Dn through the procedure described above, the n-bit latch register 114 outputs a linear code through the output terminals Q1 to Qn, and the output linear code is converted into a binary code by a linear-to-binary encoder 116 illustrated in
Examples of converting a linear code output from the n-bit latch register 114 into a binary code are shown below in Table 1.
In
The timing chart of
In
That is, by providing the time interval Treset 308, all the capacitors C1 to Cn existing in the ADC circuit 100 or 200 are fully discharged, and outputs D1 to Dn of all the comparators Cmp
If a voltage VC1 charged in the capacitor C1 138 or 210 is greater than a predetermined threshold value Vth, the comparator Cmp
In
In a chain of CMOS inverters, every even inverter 452, 456, 460, 464 is connected with a voltage source 410, and every odd inverter 450, 454, 458, 462 is connected with a current source 412.
Every odd inverter 450, 454, 458, 462 functions as a switch, and every even inverter 452, 456, 460, 464 functions as a capacitor and a comparator at the same time. More specially, in the first CMOS inverter 450, reference numeral “402” corresponds to the switch SW1 122 or 202 of
As described above, an ADC according to the present invention can be simply and easily implemented in a CMOS process, and has low power consumption.
The embodiments of the present invention described above propose new ways for analog to digital conversion. Main features of an ADC proposed include a simple architecture, easy and efficient implementation in a CMOS process, and low power consumption. A conversion rate is proportional to ADC resolution. Such an ADC is used in all applications that require low power consumption, moderate resolution, and moderate sampling rate. Examples of such applications include RF transceivers in mobile communication systems, software defined radio receivers, and digital video and image processing systems.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 15051/2007 | Feb 2007 | KR | national |
