Method and apparatus for analyzing performance, and computer product

Abstract

In a performance analyzing apparatus, a setting unit sets an event of which the performance is desired to be monitored, a detecting unit detects an instruction address at the time of generation of an interrupt signal from a timer, and a calculating unit calculates a variation amount of a counted value by a hardware counter at a detected instruction address. The variation amount is accumulatively retained for each detected instruction address. A specifying unit specifies an instruction address that corresponds to the event, and a display unit displays a graph of the total variation amounts.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic for illustrating a hardware configuration of a performance analyzing apparatus according to an embodiment of the present invention;

FIG. 2 is a block diagram of a partial hardware configuration of the performance analyzing apparatus shown in FIG. 1;

FIG. 3 a block diagram of a functional configuration of the performance analyzing apparatus;

FIG. 4 is a schematic of an address/variation amount table;

FIG. 5A is a graph of a total variation amount for each instruction address;

FIG. 5B is a graph of a total variation amount for each function; and

FIG. 6 is a flowchart of a performance analyzing process by the performance analyzing apparatus.

Claims

1. A performance analyzing apparatus comprising: a setting unit configured to set an event for which number of times of occurrence are counted by a hardware counter provided in a processor on which a program to be analyzed is executed;a detecting unit configured to detect instruction addresses at a time of generation of interrupt signals that are generated at predetermined time intervals from the processor while the program is being executed;a calculating unit configured to calculate a total amount of variation in values counted by the hardware counter for each of the instruction addresses; anda display control unit configured to control a display unit to display the total amount of variation for each of the instruction addresses.

2. The performance analyzing apparatus according to claim 1, further comprising a specifying unit configured to specify an instruction address that corresponds to the event from among the instruction addresses, wherein the display control unit is configured to control the display unit to display the specified instruction address in association with the total amount of variation of the specified instruction address.

3. The performance analyzing apparatus according to claim 1, wherein the display control unit is configured to control the display unit to display the total amount of variation for each of the instruction addresses based on an execution unit including an instruction of the instruction addresses.

4. The performance analyzing apparatus according to claim 2, wherein the display control unit is configured to control the display unit to display the total amount of variation for each of the instruction addresses based on an execution unit including an instruction of the instruction addresses.

5. A performance analyzing method comprising: setting an event for which number of times of occurrence are counted by a hardware counter provided in a processor on which a program to be analyzed is executed;detecting instruction addresses at a time of generation of interrupt signals that are generated at predetermined time intervals from the processor while the program is being executed;calculating a total amount of variation in values counted by the hardware counter for each of the instruction addresses; anddisplaying the total amount of variation for each of the instruction addresses.

6. The performance analyzing method according to claim 5, further comprising specifying an instruction address that corresponds to the event from among the instruction addresses, wherein the displaying includes displaying the specified instruction address in association with the total amount of variation of the specified instruction address.

7. The performance analyzing method according to claim 5, wherein the displaying includes displaying the total amount of variation for each of the instruction addresses based on an execution unit including an instruction of the instruction addresses.

8. The performance analyzing method according to claim 6, wherein the displaying includes displaying the total amount of variation for each of the instruction addresses based on an execution unit including an instruction of the instruction addresses.

9. A computer-readable recording medium that stores therein a computer program for realizing a performance analyzing method on a computer, the computer program making the computer execute: setting an event for which number of times of occurrence are counted by a hardware counter provided in a processor on which a program to be analyzed is executed;detecting instruction addresses at a time of generation of interrupt signals that are generated at predetermined time intervals from the processor while the program is being executed;calculating a total amount of variation in values counted by the hardware counter for each of the instruction addresses; anddisplaying the total amount of variation for each of the instruction addresses.

10. The computer-readable recording medium according to claim 9, wherein the computer program further makes the computer execute specifying an instruction address that corresponds to the event from among the instruction addresses, wherein the displaying includes displaying the specified instruction address in association with the total amount of variation of the specified instruction address.

11. The computer-readable recording medium according to claim 9, wherein the displaying includes displaying the total amount of variation for each of the instruction addresses based on an execution unit including an instruction of the instruction addresses.

12. The computer-readable recording medium according to claim 10, wherein the displaying includes displaying the total amount of variation for each of the instruction addresses based on an execution unit including an instruction of the instruction addresses.