Claims
- 1. A method for testing a digital circuit that includes combinational logic and a scan chain of memory elements, the method comprising:
clocking a test pattern into the memory elements of the scan chain at a shift frequency; clocking the digital circuit including the memory elements of the scan chain at an operating frequency of the digital circuit, the operating frequency being different from the shift frequency; and capturing a response to the test pattern in the memory elements of the scan chain.
- 2. The method of claim 1 including clocking the test pattern response out of memory elements of the scan chain at the shift frequency.
- 3. The method of claim 1 wherein the shift frequency is lower than the operating frequency.
- 4. The method of claim 1 wherein the shift frequency is provided by selectively suppressing clock pulses that provide the operating frequency.
- 5. The method of claim 1 wherein the shift frequency is higher than the operating frequency.
- 6. The method of claim 1 wherein the shift frequency is provided by multiplexing clock pulses that provide the operating frequency with clock pulses that provide a higher frequency than the operating frequency.
- 7. The method of claim 1 including:
applying a capture state of a scan enable signal to the memory elements of the scan chain; and suppressing one or more clock pulses that provide the operating frequency until the capture state of the scan enable signal has reached the memory elements.
- 8. The method of claim 1 including capturing the test pattern response in the scan chain within one clock cycle after the test pattern is launched into the combinational logic, the clock cycle being of the clock that provides the operating frequency.
- 9. A computer-readable medium on which is stored a computer program having instructions for executing the method of claim 1.
- 10. A method for testing a digital circuit that includes combinational logic interconnecting at least two interactive clock domains clocked at respective operating frequencies, each domain including a scan chain of memory elements, the method comprising:
providing a test pattern in the memory elements of a scan chain in the first clock domain; clocking each clock domain at the domain's respective operating frequency, thereby launching the test pattern into the combinational logic; and at a first time, capturing a response to the test pattern in the memory elements of a scan chain in one clock domain but not the other clock domain.
- 11. The method of claim 10 including, at a second time different from the first, capturing a response to the test pattern in the memory elements of a scan chain in the other clock domain.
- 12. The method of claim 11 wherein the first and second times correspond to clock pulses occurring at different times.
- 13. The method of claim 10 wherein the other clock domain is prevented from capturing a test pattern response by suppressing one or more clock pulses of the other clock domain.
- 14. The method of claim 10 wherein a test pattern is clocked simultaneously into the memory elements of a scan chain in each clock domain at a same shift frequency.
- 15. The method of claim 10 wherein the operating frequencies of the clock domains are the same frequency.
- 16. The method of claim 10 including:
applying a capture state of a scan enable signal to the memory elements of the scan chain in the second domain; and suppressing one or more clock pulses that provide the operating frequency for the first domain until the capture state of the scan enable signal has reached the memory elements of the scan chain in the second clock domain.
- 17. The method of claim 10 wherein the test pattern response is captured within one clock cycle, the clock cycle being of the clock domain that provides the fastest operating frequency.
- 18. A method for testing a digital circuit that includes combinational logic and a scan chain of memory elements, the method comprising:
providing a test pattern in the memory elements of the scan chain; applying a capture state of a scan enable signal to the memory elements of the scan chain; suppressing one or more clock pulses that provide an operating frequency for the digital circuit until the capture state of the scan enable signal has reached the memory elements of the scan chain; clocking the digital circuit including the memory elements of the scan chain at an operating frequency; and capturing a response to the test pattern in the memory elements of the scan chain.
- 19. The method of claim 18 including:
clocking a second time the digital circuit including the memory elements of the scan chain at an operating frequency capturing a second time a response the test pattern within one clock cycle after the first capture.
- 20. A method for at-speed testing a digital circuit that includes combinational logic interconnecting at least two clock domains, the first clock domain having an operating frequency slower than the operating frequency in the second clock domain, each domain including a scan chain of memory elements, the method comprising:
providing a test pattern in the memory elements of a scan chain in the first clock domain; clocking each clock domain at the domain's respective operating frequency and thereby launching the test pattern into the combinational logic; and capturing a response to the test pattern in the memory elements of a scan chain in the second clock domain within one second domain clock cycle after the test pattern is launched.
- 21. Apparatus for testing a digital circuit that includes combinational logic and a scan chain of memory elements, comprising:
a clock for clocking a test pattern into the memory elements of the scan chain at a shift frequency and for clocking the digital circuit at an operating frequency; and a clock suppression circuit suppressing one or more clock pulses providing the operating frequency.
- 22. The apparatus of claim 21 including a clock suppression circuit suppressing one or more clock pulses providing the shift frequency.
- 23. The apparatus of claim 21 including a multiplexer multiplexing clock pulses providing the operating frequency with clock pulses providing a higher frequency than the operating frequency.
RELATED APPLICATION DATA
[0001] This patent is based on U.S. Provision Patent Application No. 60/089,620, filed Jun. 16, 1998.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60089620 |
Jun 1998 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
09342162 |
Jun 1999 |
US |
Child |
10301127 |
Nov 2002 |
US |