Patent Application
20050188125
The present invention relates to a method and apparatus for burst mode data transfers between a CPU and a FIFO (“first-in-first-out”) memory.
FIFO memories are often employed as buffers between a CPU and a peripheral device in order to facilitate the transfer of data. For example, a cellular telephone includes a CPU adapted to interface via a FIFO with a peripheral camera. Another example of the use of FIFO memories is in a UART (“Universal Asynchronous Receiver Transmitter”), where the UART interfaces between a parallel bus coupled to the CPU and a peripheral device adapted for serial communications. FIFO memories are ordinarily accessible only through a single memory address.
CPU's are commonly provided with “burst” mode instructions for transferring data between corresponding memory spaces. For example, processors known in the art by the tradename “ARM” provide for a “Read Multiple” and a “Write Multiple” instruction that efficiently transfers a block of data from one contiguous memory space to another. Particularly, the “Read Multiple” instruction of the ARM processor provides for reading 32 bytes of data from a contiguous memory space and storing the 32 bytes of data in internal registers with a single instruction fetch. Similarly, the “Write Multiple” instruction provides for writing 32 bytes of data from the internal registers to a contiguous memory space, with a single instruction fetch. Without such burst mode capabilities, the processor can read or write only 4 bytes per instruction fetch and the contents of an address register must be incremented each time. In addition, implementing a read or write multiple instruction in software requires the execution of a loop which adds further processing overhead.
The burst mode instructions, “Read Multiple” and “Write Multiple,” therefore permit the CPU to function much more efficiently, by saving many of the clock cycles that would ordinarily be required. However, the burst mode instructions require a contiguous block of memory identified by sequential addresses with which to interact and therefore do not work with a FIFO, which is identified with a single address. Accordingly, there is a need for a method and apparatus for burst mode data transfers between a CPU and a FIFO.
A preferred method and apparatus is provided for burst mode data transfers between a CPU and a FIFO. The CPU executes a burst mode memory access instruction defining multiple memory addresses. The multiple memory addresses are decoded to produce an output that is the same for each of the multiple memory addresses. The FIFO is accessed repeatedly, for each of the multiple memory addresses, by use of the output. Preferably, the multiple addresses are placed sequentially on a bus, and the multiple memory addresses are sequentially received from the bus for decoding.
More particularly, as exemplary context for the present invention, the circuit 20 may be a UART containing two FIFOs, e.g., a read FIFO RX (22) and a write FIFO TX (24); however, it will be understood that a single FIFO may be used for both reading and writing. Because there are two FIFOs, the circuit 20 preferably includes separate control circuits for controlling each FIFO, e.g., a read control circuit 26 for controlling the FIFO RX (22) and a write control circuit 28 for controlling the FIFO TX (24). However, it will be understood that a single control circuit incorporating both functions may be used.
The output of the read control circuit 26 is a READ signal 42 that, when active, causes the FIFO RX (22) to output four bytes to the bus 16. Similarly, the write control circuit 28 outputs a WRITE signal 43 to the FIFO TX (24) to cause the FIFO TX to sample four bytes from the bus 16.
Turning to
Turning to
The memory address “SA” is decoded by the read control circuit 26 and, if it matches the address of a read address register (not shown) for the FIFO RX (22), the read control circuit 26 causes the FIFO RX 22 to place the data “RD” that it has is stored within it on the bus 32. During the data cycle 36, ADDRESS ENABLE # is high, and on the transition of READ ENABLE # from low to high, the CPU samples the data “RD” from the bus 32.
The same principle of operation applies in reverse for a WRITE instruction, through use of a write address register (also not shown) of the FIFO TX (24).
The CPU's READ and WRITE instructions can be used to effectuate a pseudo “burst mode” by employing a software loop as is well known. However, the CPU 12 also supports hardware burst memory access instructions. The system described herein assumes instructions for an ARM processor, e.g., the ARM7TDMI, but it should be understood that any other processor having similar features may be used. The exemplary ARM7TDMI CPU provides a “Read Multiple” instruction whereby 32 bytes of data are read from contiguous specified memory locations in a burst and stored in internal registers, and provides a corresponding “Write Multiple” instruction whereby 32 bytes of data are written from the CPU's internal registers to specified contiguous memory locations in a burst. While the burst mode instructions preferably employ registers internal to the CPU, registers external to the CPU may be employed without departing from the principles of the invention provided the external registers may be accessed by the CPU within an appropriate time frame.
In a burst mode transfer from the CPU to a memory, the memory address is incremented in hardware to provide, with minimum processing overhead, a range of multiple addresses for accessing respective multiple memory locations. Typically, as in the ARM processor, the burst mode instructions increment the memory address monotonically in steps of 1, corresponding to contiguous memory locations defining a block of memory space, but this is not essential. Using these instructions, the bus timing shown in
According to the invention, the CPU accesses the read FIFO RX (22) and the write FIFO TX (124) in burst modes, wherein a FIFO is repeatedly accessed using a set of predetermined multiple addresses.
In
Turning to
The invention provides for an outstanding savings in CPU overhead. Turning to
In a set-up step 39, four clock cycles are first required to establish the first source address and the FIFO destination address. Eight clock cycles are then required to transfer consecutive blocks of four bytes of data as a result of the following actions: (1) instruction fetch “read memory” (clock cycle C1); (2) read 4 bytes from the memory (clock cycle C2); (3) instruction fetch “write FIFO” (clock cycle C3); (4) write 4 bytes to the FIFO (clock cycle C4); (5) fetch “increment source address” instruction (clock cycle C5); (6) increment the source address (clock cycle C6); (7) instruction fetch “check address” (clock cycle C7); and (8) check the address to determine whether 32 bytes have been transferred (clock cycle C8). Accordingly 4+(N·8)=68 clock cycles are required for transferring 32 bytes (where N=32/4=8).
The 68 clock cycles required for transferring 32 bytes conventionally is reduced as shown in
It will be immediately appreciated by persons of ordinary skill in the art that the above-described functionality may be implemented in hardware by a number of different means. Moreover, methods and apparatus according to the invention may be implemented in hardware, software, or both, and machine readable media may be provided embodying one or more programs of instructions executable by the machine to perform one or more methods according to the invention. In addition, it is to be recognized that while a particular methods and apparatus for efficient transfer of data between a FIFO and a RAM have been shown and described as preferred, other configurations and methods could be utilized, in addition to those already mentioned, without departing from the principles of the invention.
The terms and expressions which have been employed in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention in the use of such terms and expressions to exclude equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims which follow.
