Method and apparatus for calculating power consumption, and computer product

Abstract

A power consumption calculating apparatus includes a receiving unit, a specifying unit, a determining unit, an average calculating unit, an estimating unit, and a power consumption calculating unit. The receiving unit receives data of a target circuit. The specifying unit specifies a sequential circuit in the circuit. The determining unit, by developing a sequential circuit to a combinational circuit, determines a clock cycle to be input into the combinational circuit. The average calculating unit calculates the average number of transition after the number of transition of 2N-clock cycle is calculated. The estimating unit estimates the estimated number of transition. And the power consumption calculating unit calculates the maximum power consumption.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of a power consumption calculating apparatus according to embodiments of the present invention;

FIG. 2 is a block diagram of the power consumption calculating apparatus;

FIG. 3 is a schematic of a sequential circuit;

FIG. 4 is a schematic for illustrating a method of developing the sequential circuit;

FIG. 5 is a schematic for illustrating a method of calculating the number of transition;

FIG. 6 is a schematic for illustrating a method of calculating the estimated number of transition of a gate output; and

FIG. 7 is a flowchart of a power consumption calculating process performed by the power consumption calculating apparatus.

Claims

1. A computer-readable recording medium that stores therein a computer program for calculating power consumption, the computer program making a computer execute: receiving data of a target circuit;specifying a sequential circuit in the circuit based on the data;determining a clock cycle of a test pattern to be input into a combinational circuit in the sequential circuit by developing the sequential circuit;estimating number of transition of a logic gate output that is output from a logic gate in the combinational circuit while the circuit is under processing, based on the clock cycle; andcalculating power consumption of the circuit based on the number of transition.

2. The computer-readable recording medium according to claim 1, wherein the computer program further makes the computer execute calculating average number of transition of the clock cycle based on the test pattern, andthe estimating includes estimating the number of transition based on a larger clock cycle than the clock cycle determined at the determining.

3. The computer-readable recording medium according to claim 1, wherein the test pattern includes a test vector.

4. A method of calculating power consumption, comprising: receiving data of a target circuit;specifying a sequential circuit in the circuit based on the data;determining a clock cycle of a test pattern to be input into a combinational circuit in the sequential circuit by developing the sequential circuit;estimating number of transition of a logic gate output that is output from a logic gate in the combinational circuit while the circuit is under processing, based on the clock cycle; andcalculating power consumption of the circuit based on the number of transition.

5. The method according to claim 4, further comprising calculating average number of transition of the clock cycle based on the test pattern, and the estimating includes estimating the number of transition based on a larger clock cycle than the clock cycle determined at the determining.

6. The method according to claim 4, wherein the test pattern includes a test vector.

7. An apparatus for calculating power consumption, comprising: a receiving unit configured to receive data of a target circuit;a specifying unit configured to specify a sequential circuit in the circuit based on the data;a determining unit configured to determine a clock cycle of a test pattern to be input into a combinational circuit in the sequential circuit by developing the sequential circuit;an estimating unit configured to estimate number of transition of a logic gate output that is output from a logic gate in the combinational circuit while the circuit is under processing, based on the clock cycle; anda consumption calculating unit configured to calculate power consumption of the circuit based on the number of transition.

8. The apparatus according to claim 7, further comprising an average calculating unit configured to calculate average number of transition of the clock cycle based on the test pattern, and the estimating unit is configured to estimate the number of transition based on a larger clock cycle than the clock cycle determined by the determining unit.

9. The apparatus according to claim 7, wherein the test pattern includes a test vector.