Patent Application
20070285515
The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
In one embodiment, the present invention is a stand-alone device that calibrates a video signal (i.e., a series of video images) in substantially real time (i.e., as the video signal is received). One embodiment of the present invention is a device that corrects the chrominance and luminance of the video signal before sending the video signal on to a display device (e.g., a television, a computer monitor or the like). The device stores calibration coefficients that enable the device to improve the image going to the display. In one embodiment, the calibration coefficients are determined using a Spyder colorimeter, commercially available from Datacolor of Lawrenceville, N.J. The present invention externalizes the calibration of the video signal and corrects the image on any display device, on the fly, without relying on the display device manufacturer to expose adjustments, or even relying on the user to find the adjustments and set them correctly.
The present invention allows a user to calibrate any input that he/she chooses without having to personally generate test patterns for the format he/she is calibrating (e.g., high-definition television). The user can calibrate as many, or as few, of the inputs on the display device as he/she chooses by simply pressing a button.
The video processing FPGA 200 can be represented by one or more software applications (or even a combination of software and hardware, e.g., using application specific integrated circuits (ASIC)), where the software is operated by the CPU 210 in the memory (e.g., Flash memory 214 or SRAM 216) of the calibration device 100.
The input video connectors 202 are adapted to connect to the source of the uncalibrated video signal and receive the uncalibrated video signal therefrom. The uncalibrated video signal is then provided to the input ADC/decoder 204 for analog-to-digital conversion (if the video signal is not already in a usable digital form) before being provided to the video processing FPGA 200 for further processing.
The video processing FPGA 200 performs video data correction on the input, uncalibrated video signal and controls the output of the calibrated video signal to the output DAC/encoder 206. The video processing FPGA 200 is further coupled to the CPU 210 and to memory (e.g., SDRAM 212). As discussed in further detail below, the memory coupled to the video processing FPGA 200 (e.g., SDRAM 212) is used to store bitmaps of incoming images in the video signal and look-up tables (LUT's) for caption letters.
The output video connectors 208 are adapted to connect to the display of the display device. The output video connectors 208 receive the calibrated video signal from the output DAC/encoder 206 and provide the calibrated video signal to the display.
The USB connector 220 is adapted to connect to a calorimeter (e.g., colorimeter 108 of
In one embodiment, the number and type (e.g., component video, separate video (S-video), high-definition multimedia interface (HDMI), digital video interface (DVI) or the like) of outputs are the same as the number and type of inputs (i.e., the calibration device 100 does not perform conversion in the illustrated embodiment). Although both the input video connectors 202 and the output video connectors 208 are illustrated in
If the calibration device 100 is not in operating mode (e.g., is turned off), the output video connectors 208 simply pass the unchanged (i.e., uncalibrated) video signal to the display.
In order to adapt the calibration device 100 for processing of multiple video sources, additional components may be incorporated in the calibration device 100, including additional input and output ports, input and output switching capabilities, format/resolution tracking for each input/output, look-up table storage for each input/output, calibration status tracking for each input/output, a receiver (e.g., an infrared (IR) receiver) to handle control, and remote control (e.g., an IR remote control) for controlling the calibration device and ASIC modification to support logic and flow. Alternatively, multiple single-purpose calibration devices 100 (i.e., each supporting only one input/output type) may be implemented (e.g., “stacked”) to support processing for multiple video sources.
The LUT's 300 store correction data for the incoming video channels. Specifically, the LUT's 300 map each input color in an uncalibrated video signal to an output (calibrated) color. In one embodiment, the LUT's 300 are simplified video cards with LUT table memory.
The control/caption registers 302 are internal registers that store information including data control, setup, transfer type, and calibration. In one embodiment, 128 registers, each of which is five bits deep, are used to store the necessary captioning information during calibration of a video signal.
The calibration module comprises state machines and logic that control calibration routines. The image decode module 304 comprises state machines and logic that control image sizing requirements for other components of the video processing FPGA 200. The caption decode module 306 comprises state machines, logic and registers that control the captioning during calibration.
The output video data module 310 comprises a video data multiplexer. The output video data module 310 provides video signals to the output DAC and/or encoder 206 of the calibration device 100. When the calibration device 100 is in operating mode, the output video data module 310 provides a calibrated video signal. In other modes, the output video data module 310 may provide an uncalibrated signal, a split screen signal, or a calibration signal.
The interfaces include an SDRAM peripheral interface 312 to the SDRAM 212 of the calibration device 100 and a CPU peripheral interface 314 to the CPU 210 of the calibration device 100. In one embodiment, one or both of the interfaces 312 and 314 is an eight-bit data interface. In another embodiment, one or both of the interfaces 312 and 314 is a sixteen-bit data interface.
The method 400 is initialized at step 402 and proceeds to step 404, the method 400 determines whether a user signal requesting calibration of the display device has been received. In one embodiment, the user signal is received via the press of a button (e.g., on the external housing of the calibration device). In another embodiment, the user signal is received via the placement of the calibration device in the path of a video signal from a source to the display device (i.e., “connecting” the calibration device to the video source, the display device and a power supply).
If the method 400 concludes in step 404 that a user signal has not been received, the method 400 proceeds to step 406, where the method 400 receives an input (uncalibrated) video signal from the video source.
In step 408, the method 400 passes the input video signal through a LUT. That is, the method 400 calibrates the input video signal using the corrections stored in the LUT. The method 400 then outputs the calibrated video signal to the display device in step 410 before returning to step 406 and proceeding as described above to receive and calibrate the incoming video signal.
Referring back to step 404, if the method 400 concludes that a user signal requesting calibration of the display device has been received, the method 400 proceeds to step 412 and verifies communication with a calorimeter that is deployed to measure the color of the display.
The method 400 then proceeds to step 414 and creates a test pattern for display on the display device. In one embodiment, the test pattern is generated internally by the video processing FPGA, and any incoming video data stream is effectively ignored while the method 400 outputs its own internally generated video stream for presentation to the display device. In another embodiment, the test pattern is generated by writing coefficients to the LUTs in order to effectively overwrite the incoming video data stream and output any arbitrary test pattern that the application may require. The method 400 displays the test pattern on the display device in step 416.
In step 418, the method 400 receives measurements of the displayed test pattern from the calorimeter. The method 400 then proceeds to step 420 and calculates the corrections that are required to calibrate the chrominance and/or luminance displayed on the display device, in accordance with the measurements received from the calorimeter. The calculated corrections are stored in the LUT in step 422, before the method 400 advances to step 406 and proceeds as described above to receive and calibrate the incoming video signal using the newly calculated corrections.
It should be noted that although not explicitly specified, one or more steps of the methods described herein may include a storing, displaying and/or outputting step as required for a particular application. In other words, any data, records, fields, and/or intermediate results discussed in the methods can be stored, displayed, and/or outputted to another device as required for a particular application. Furthermore, steps or blocks in the accompanying Figures that recite a determining operation or involve a decision, do not necessarily require that both branches of the determining operation be practiced. In other words, one of the branches of the determining operation can be deemed as an optional step.
While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/812,553, filed Jun. 9, 2006, which is herein incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 60812553 | Jun 2006 | US |
