METHOD AND APPARATUS FOR COMPUTING @$apos;N-BIT AT A TIME@$apos; CRC@$apos;s OF DATA FRAMES OF LENGTHS NOT MULTIPLE OF N

Abstract

The present invention discloses CRC checking 'N-bit at a time' of data frames of lengths not necessarily in a multiple of the N-bit. While receiving the data frame, the data frame length is extracted from the protocol header and a misalignment is computed versus the 'N-bit at a time' value. Simultaneously, CRC is computed on each received N-bit of the data frame and an FCS register is updated. At each cycle, a checking is performed to know whether the data frame length has been extracted from the protocol header. While the data frame length is not yet known and more bits are left to process, the data frame is continued to be received and computed 'N-bit at a time'. When the data frame length is known and no more bits are to be processed, the current value of the FCS register is compared to a pre-stored vector corresponding to the misalignment. If a match occurs, checking of the data frame passes and the data frame is accepted. If a match does not occur, checking of the data frame fails and the data frame may be rejected. Therefore, the present invention is capable of computing CRC of a data frame 'N-bit at a time' while the data frame length is not yet known.

Description

Brief Summary of the Invention

[0012] Thus, it is an object of the present invention to provide a method and an apparatus whichdoes not assume that frame lengths are known prior to starting the computation of CRC'sn-bit or n-byte at a time.

[0013] Another object of the present invention is to not require that data frames be left padded,so as their lengths become a multiple of n-bit or n-byte, to be able to perform thechecking of the received data frames.

[0014] Another object of the present invention is to restore the result of the CRC computation asif it had been performed with the necessary left padding.

[0015] The present invention dislcoses a CRC checking 'N-bit at a time' of data frames havinglengths not necessarily a multiple of the N-bit. While receiving the data frame, the lengthof the data frame is extracted from the protocol header. Then, a misalignment iscomputed for the received data frame versus the 'N-bit at a time' value. Simultaneously,having received N-bit of the data frame, CRC is computed on the received N-bit and anFCS register is updated. A check is performed to determine whether the length has beenextracted from the protocol header. If the length of the data frame is not yet known, thedata frame continues to be received and 'N-bit at a time' continues to be computed. Oncethe length of the data frame is known, the extracted length is compared with the currentnumber of received N-bit of the data frame thus, a checking is performed to determinewhether more bits are to be processed or not. If more bits are left to process, the dataframe continues to be received 'N-bit at a time' continues to be computed. If no more bitsare left to process, the current value of the FCS register is compared to a pre-stored vectorcorresponding to the misalignment. If there is a match, checking of the data frame passesand the data frame is accepted. If there is not a match, checking fails and the data frame isrejected.

[0016] A method and an apparatus are also disclosed for restoring the value of the FCS registeras if computation had actually stopped on the data frame boundary.

[0017] Therefore, the invention manages to start checking CRC of a data frame 'N-bit at a time'while the data frame length is not yet known.

[0018] Further objects, features and advantages of the present invention will become apparent tothose skilled in the art upon examination of the following description in reference to theaccompanying drawings. It is intended that any additional advantages be incorporatedherein.

Brief Description of the Several Views of the Drawings

[0019] FIG. 1 illustrates a data frame protected by a CRC and exchanged from a transmittingside to a receiving side through a network.

[0020] FIG. 2 shows an LFSR aimed at computing CRC's.

[0021] FIG. 3 illustrates a problem encountered when computing CRC's 'N-bit at a time'.

[0022] FIG. 4 shows how a data frame is left padded to obtain the correct result.

[0023] FIG. 5 illustrates the principle of the present invention which does not require leftpadding thus, does not assume that frame length be known to start checking.

[0024] FIG. 6 is an example of the set of vectors that must be stored to allow CRC checkingaccording to the present invention.

[0025] FIG. 7 is a flow chart illustrating the steps of checking a data frame according to thepresent invention.

[0026] FIG. 8 is an example of the set of vectors that must be stored to allow the restoration ofthe FCS register to the right value i.e., as if computation had actually stopped on frameboundary.

[0027] FIG. 9 illustrates a multiplier to restore FCS register value.

[0028] FIG. 10 is a flow chart illustrating the step of allowing the restoration of the FCS register.

Detailed Description of the Invention

[0029] According to the present invention, it is possible to start computing CRC as soon asenough bits and bytes 500 have been accumulated to match the 8-byte computing deviceassumed in the example of FIG. 3, i.e., without having to first make any assumption onthe length of the data frame to check, as shown in FIG. 5. Computation continues inmultiples of 8-bytes 510 until last byte 520 is received. It is known to stop at that timesince the length of the data frame is assumed to have been extracted from the header, aftercomputation has started however, and before the last byte of the data frame is received.Nevertheless, the computation has generally gone too far. Because computing isperformed on an 8-byte boundary, in this particular example used to illustrate the presentinvention, the end result corresponds to 24 bytes received 530 while only 19 bytes(540)should have been processed. This may not be a real problem in some specificapplications though. If the expected result of the checking (i.e., frame has not beenaltered) is an all zero or null vector, then further dividing of 0, like with ordinarynumbers, does not change the final result. However, most standards (if not all) that dealwith CRC, manage to include a provision to prevent an all zero frame from passingchecking for the obvious reason that a failing device could have generated it and this mustbe detectable. To avoid this from happening, standards generally specify that FCS aretransmitted inverted after having been calculated over a string of data bits. Hence, theresult of the checking, on the receiving side, is rather an all 1's vector which correspondsto the inversion of the FCS before transmission by the sending device.

[0030] It is worth noting here that the LFSR shown in FIG. 2 reflects this. This is the invertedresult (210), present in the SR at the end of the computation, which is sent 'one-bit at atime', most significant bit first, as the FCS, while data bits are transmitted withoutinversion (220) while computation continues.

[0031] Therefore, the expected result of a frame checking is not generally an all zero vector. It isthus further divided by the device in charge of computing 'n-byte at a time', of a valuecorresponding to the extra displacement d 550, incurred because the frame could not beleft justified at the start of the computation.

[0032] To accommodate this, it is assumed that enough patterns are stored to take care of allvalues that d can take in a particular application. In the example chosen to illustrate thepresent invention, namely, the CR-32 of ATM and Ethernet, computed '8-byte at a time',only 8 patterns must be stored since frames are always byte aligned. The eight values tobe stored are shown in FIG. 6 as a function of d 600, expressed in number of bytes. Thesepatterns correspond to the extra division supported by the all 1's pattern which is thenormal result of the checking in this case, i.e. when d = 0, when the frame is alignedbecause it is a multiple of the n-bit or n-byte value computation that is performed at eachcycle. The patterns shown here implicitly assume that 0's are automatically padded at theright of the frame when the length is not an exact multiple of the 'n-byte at a time'calculation. Other patterns would have to be calculated if the right padding were different.This would not however change the way frame checking is conducted which is betterdescribed with reference to the flow chart shown in FIG. 7.

[0033] FIG. 7 shows the steps of the method according to the present invention to check CRC.Calculation can actually start as soon as enough bits or bytes have been received in step700 to feed the device in charge of performing calculation 'n-byte at a time'. Thus, n-byteof the incoming data are processed at each cycle in step 710. In parallel, the length of thedata frame is extracted from the frame header of the received data so that the value of themisalignment d can be determined versus the number of bytes that are processed at eachcycle in step 720. When the length is known in step 730, the number of bytes that havebeen processed (in increments of n-bytes) are compared to the length of the frame in step740. If the number of bytes that have been processed is less than the length of the frame,more bytes have to be processed as determined in step 750, then the process resumes atstep 700. If the number of bytes that have been processed is equal to or larger than thelength of the frame, the current value of the calculated FCS must be compared in step 760to the one of the stored vector corresponding to the value of d determined at step 720. Anexample of such vectors are shown in FIG. 6. If matching occurs, i.e. checking of theframe passes, it must be considered that the frame has not been altered en route and canbe further processed via step 770. If matching does not occur, i.e. checking of the framefails, the frame must be handled according to the error recovery procedures in effect inthe receiver via step 780. Typically, the failed frame is discarded.

[0034] Although the examples used to describe the invention are referring to a method and anapparatus where processing is done 'n-byte at a time', it will be obvious to the one skilledin the art that the present invention applies as well to methods and systems where 'n-bit ata time' would be processed. Indeed, 'n-bit' can take any value including the practicalcases where CRC's are computed in a multiple of bytes or octets, that is, in multiples of'8-bit'. More specifically, the invention is illustrated with the case where 'n-byte' isactually '8-byte' and the CRC is the common (4-byte) CRC-32 of many protocols. Anyvalue of n and any CRC could be considered as well and the present invention would stillapply.

[0035] FIG. 8 illustrates the fact that, up to this point, it was implicitly assumed that the receiverside is only interested in checking the integrity of the incoming frame (so that it can besafely further processed). This is most often the only purpose of adding a CRC to a dataframe. However, some applications may want go further and require performingcorrections of errors or analyzing the result of the checking. It is clear that the previousmethod described with reference to FIG. 7 is limited to the first common case. Althoughthe method manages to determine if the result of the checking is good or not, it remainsthat this result is not the one that would have been obtained if computing had actuallystopped on the right boundary of the frame.

[0036] Hence, to obtain the right result of the checking, often referred to as the syndrome in theliterature on CRC and Error Correction Code (ECC), it is necessary to move backwardand restore the value as if computation has indeed stopped on the good boundary. Thiscan be achieved simply by multiplying the result of the checking by a vectorcorresponding to a backward displacement of d 550, as shown in FIG. 5, in the GaloisField or the Multiplicative Group that can be generated with the generator polynomialG(X) of the CRC in use. This must be done in an algebra modulo 2, modulo G(X) anelementary implementation of the circuitry needed to do so being the LFSR of FIG. 2.

[0037] FIG. 8 shows, as an example, the 8 vectors that must be used to multiply 'backward' andobtain the result of the checking as if computation could have stopped on the rightboundary. These vectors are for the specific example used for illustrating the inventionand are 8 vectors among the 4,294,967,295 (232-1) vectors of the Galois Field that can begenerated with the CRC-32 polynomial:

[0038] G(X) = X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X1+1.

[0039] There are numerous practical solutions to multiplying two 32-bit vectors modulo 2,modulo G(X) i.e., the vector result of the checking, as obtained in FIG. 7 by the backwardmultiplying vector of FIG. 8, so as to get the unbiased result. This can be carried out inmany ways known in the art.

[0040] As an example, one can refer to 'Error Correcting Codes', Peterson and Weldon, SecondEdition, the MIT Press, Cambridge, Massachusetts, USA, 1972 and more particularly tochapter 7.3 'Computation in Polynomial Algebras and Galois Fields'. The circuitsproposed in this reference are of the type of the LFSR of FIG. 2. They are, by design('1-bit at a time'), limited in performance.

[0041] A full combinatorial circuit for the example of the CRC-32 is shown in FIGS. 9A and 9Bas a much faster way of performing the backward multiplication that allow move back tothe right syndrome. Figure 9A, shows an array of OE's or 2-way Exclusive OR operators910 in this example, which performs the multiplication modulo 2 of two vectors 920, 930so as the result is 63 bit vector 940. This intermediate result must be reduced, moduloG(X) thus, to 32-bit vector 950 through another matrix of OE's 960 shown in FIG. 9B.For the sake of clarity, this matrix shows a 1 where, on a per row basis, an input to a wideOE function must be connected to get the corresponding output bit. For example bit 0 offinal result 950 is the OE of intermediate result bits 62, 61, 60, 58, 57, 56, 48, 44, 42, 41,38, 32 and 0.

[0042] Hence, if syndrome must be restored, the method of FIG. 7 has to be changed. Step 760 isreplaced by step 1060 of FIG. 10 after it has been determined that all bytes of the framehave been received in step 1050. Thus, step 1060 performs the backward multiplicationas discussed in FIGS. 9A and 9B or through any method known in the art. At this pointthe syndrome is restored as if computation had been done with standard methods and onemay proceed as usual. For example syndrome may be analyzed so as a correction of thereceived frame can be done if it was indeed the purpose of restoring the syndrome.

[0043] It is worth noting that the method illustrated in FIG. 10 can be used as well to computethe FCS on the transmitting side. Although it was assumed, up to this point, that thelength of the frame is not known to the receiver when starting the checking, if the samesituation is encountered on the transmitting side, then the method illustrated in FIG. 10(i.e., method shown in FIG. 7 with the modified step of FIG. 10) can be used to determinethe correct FCS to transmit after the backward multiplication is done at step 1060.

[0044] Although illustrative embodiments and its advantages have been described in detailhereinabove, they have been described by way of example and not by way of limitation. Various changes, substitutions and alterations can be made in the illustrativeembodiments withough departing from the breadth, scope and spirit of the presentinvention.

Claims

A method for allowing a Cyclic Redundancy Check (CRC) checking 'N-bit at a time' of a data frame having a length not necessarily a multiple of said N-bit, said method comprising the steps of: 1. (a) receiving said data frame;(i) extracting a length from a protocol header of said data frame;(ii) determining a misalignment d between said length from the protocol header of said data frame and said N-bit of said data frame; and(b) simultaneously receiving N-bit of said data frame;(i) determining CRC on said received N-bit;(ii) updating a Field Check Sequence (FCS) register;(iii) determining if said length of said data frame is known, wherein when said length of said data frame is not yet known, repeating steps (b)(i)-(iii) 'N-bit at a time', and when said length of said data frame is known, comparing said extracted length from the protocol header of said data frame to a number of said received N-bit of said data frame and determining whether more bits are to be processed,further wherein, when more bits are left to process, repeating steps (b)(i)-(iii) 'N-bit at a time', andwhen no more bits are left to process, comparing a current value of said FCS register to a pre-stored vector corresponding to said misalignment d, wherein when a match occurs checking of said data frame passes and said data frame is accepted, and when a match does not occur checking of said data frame fails and said data frame is rejected.

2. The method according to claim 1 wherein said N-bit comprises an integer number of 8-bit bytes (N-byte).

The method according to claim 1 wherein said step of comparing a current value of said FCS register to a pre-stored vector is replaced by the step of: 3. backward multiplying in algebra modulo 2, modulo G(X), said FCS register value by a pre-stored vector corresponding to said misalignment d;wherein said FCS register value is restored as if computation had stopped on a frame boundary.

4. The method according to claim 3 wherein said method is used to compute said FCS on a transmitting side.