Patent Application
20080098152
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
Embodiments of the invention generally provide a memory device and a method for providing the memory device. In one embodiment, the method includes providing a substrate for the memory device and providing one or more layers including a memory array of the memory, device. The one or more layers are arranged in a manner allowing selection of a configuration for the memory device from at least a first configuration and a second configuration. Operation of the memory device is different in the first configuration with respect to the second configuration. The method also includes selecting a configuration for the memory device from at least the first configuration and the second configuration. The method further includes providing a first layer disposed on the one or more layers if the first configuration is selected. The first layer corresponds to the first configuration. The method also includes providing a second layer disposed on the one or more layers if the second configuration is selected. The second layer corresponds to the second configuration. In some cases, only a single layer and the connections to the layer may be different from the first configuration to the second configuration.
By providing the one or more layers which are arranged to allow selection of a configuration for the memory device, different configurations of the memory device may be manufactured using the base design of the one or more layers. Thus, design modifications between the first configuration and the second configuration may be reduced, thereby reducing design, testing, and manufacturing costs. In one embodiment, differences between the first configuration and the second configuration may be reduced to a single layer. Thus, during manufacturing, where different masks are used to fabricate each layer respectively, a single mask may be used to change between manufacturing of the first configuration and the second configuration. Other embodiments and advantages are also described in greater detail below.
In the following, reference is made to embodiments of the invention. However, it should be understood that the invention is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the invention. Furthermore, in various embodiments the invention provides numerous advantages over the prior art. However, although embodiments of the invention may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the invention. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
Also, signal names used below are exemplary names, indicative of signals used to perform various functions in a given memory device. In some cases, the relative signals may vary from device to device. Furthermore, the circuits and devices described below and depicted in the figures are merely exemplary of embodiments of the invention. As recognized by those of ordinary skill in the art, embodiments of the invention may be utilized with any memory device.
During an access, the address inputs may be used by a wordline decoder 122 and column decoder 124 to access memory cells in a memory array 108 which may include multiple memory banks. For example, using a received address, the column decoder 124 may select bitlines of the memory array 108 to be accessed. Similarly, the wordline decoder 126 may select wordlines to be accessed using the received address. In some cases, an access may also occur based on an address which is internally generated.
During an access, after an address has been used to select wordlines and bitlines in the memory array 108, data may be written to and/or read from the memory array 108 may be transmitted between read/write circuitry for the memory array 108 and the external I/O circuitry 106 via one or more internal data buses 112. The combination of features and elements described above with respect to
As mentioned above, embodiments of the invention provide a memory device and a method for providing or manufacturing the memory device with a given configuration selected from one of multiple configurations. In one embodiment, selection of the given configuration may be provided via one or more layers which are arranged in a manner allowing selection of one of the multiple configurations. After a configuration has been selected, subsequent layers may be added to implement the selected configuration. Each configuration may correspond to a different operating characteristic of the memory device. For example, where a first configuration is selected during manufacturing, the resulting memory device may be a single data rate (SDR) dynamic random access memory (DRAM) device where data is transmitted to and from the memory device on a single clock edge (e.g., on the rising edge). Where a second configuration is selected, the resulting memory device may be a double data rate (DDR) DRAM device where data is transmitted to and from the memory device on both clock edges (e.g., on the rising and falling edges).
In one embodiment, separate masks 204, 206 may be provided for each different configuration 210, 220. For example, masks 204 may be used to deposit layers 216 for a first configuration of the memory device 210. Similarly, masks 206 may be used to deposit layers 226 for a second configuration of the memory device 220. In one embodiment, changing a single mask corresponding to a single layer may be used to select between the first and second configuration of the memory device 210, 220. In some cases, interconnections to the single layer (e.g., vias) in addition to the single layer may also be used to select between the first configuration and the second configuration of the memory device 210, 220. In one embodiment, the single layer may be a layer of metal, such as the metal one (M1) layer. In some cases, metal layers below the M1 layer, such as metal zero (M0) as well as any layers above the M1 layer, such as the metal two (M2) layer may be the same for each configuration.
As depicted, layers 214, 218, 224, 228 above and below the different configuration layers 216, 226 may remain the same for each configuration of the memory device 210, 220. As described above, in one embodiment, by maintaining identical layers 214, 218, 224, 228 and masks 202 used for depositing layers 214, 218, 224, 228 below and/or above the different configuration layers 216, 226, the costs for design, testing, and manufacturing of each of the configurations of the memory device 210, 220 may be reduced.
At step 306, a configuration for the memory device may be selected from at least the first configuration and the second configuration. Where the first configuration is selected, a first layer disposed on the one or more layers and corresponding to the first configuration may be provided at step 308. As described above, the first layer may be deposited, for example, using a first set of one or more masks 204. In some cases, additional layers corresponding to the first configuration may also be deposited on the first layer. Similarly, where the second configuration is selected, a second layer disposed on the one or more layers and corresponding to the second configuration may be provided at step 318. Additional layers corresponding to the second configuration may also be deposited on the second layer. In some cases, the first and second configurations may also have differing numbers of layers.
In one embodiment, after the configuration has been selected and appropriate layers for the given configuration have been provided as described above, subsequent layers may be deposited on the previously deposited layers at step 312. As described above, in one embodiment, a single set of masks 202 may also be used for the subsequent layers (e.g., the subsequent layers may be identical), regardless of the selected configuration of the memory device. Thus, as described above, the cost of designing, testing, and manufacturing the memory device may be reduced. While described above with respect to a first configuration and a second configuration, embodiments of the invention may generally be used to provide any number of configurations.
As described above, in one embodiment of the invention, each configuration of the memory device may differ in only a single layer and/or the interconnections to the single layer. In some cases, the single layer may only contain inactive elements such as metal interconnections and may not contain active elements such as transistors. For example, in one embodiment of the invention, each configuration of the memory device may differ with respect to the data path used for transmitting data (e.g., as opposed to commands or addresses) within the memory device. The data path may control data flow between read/write data lines (RWDL) and an external data bus (DQ) as described below. The different configurations implemented by the different data paths may correspond to SDR DRAM and DDR DRAM as described above.
As depicted in
When the column 404, 406, 414, 416 to be accessed has been identified as indicated by a column address bit ADDC<0>, the column may be selected for access by asserting a column select signal (CSL) for the appropriate column 404, 406, 414, 416. During a DDR access where data is read to or written from the memory device 100 on both the rising and falling edges of a clock signal, the column address bit ADDC<0> may be changed to select a column. For example, if an access starts with reading odd data (ADDC=1) on a rising edge of the clock signal, a subsequent access on the falling edge of the clock signal may read even data (ADDC=0).
In one embodiment, to improve the timing of each access, odd and even read/write data lines (RWDL) 408, 418 used by each bank 402, 412 may be twisted such that each of the banks 402, 412 shares the RWDL connections. Thus, during an access to a single bank (e.g., BANK<1>) 412, a first access on a rising edge of the clock signal may use a first RWDL 408 while a second access on a falling edge of the clock signal may use a second RWDL 418. Each data line (both RWDL 408, 418 and the SRWDL 426, 428 described below) may transmit multiple bits of data in parallel (e.g., each data line may transmit 32 bits in parallel). Timing may be improved, for example, because data for each of the separate accesses may use the separate RWDL connections without interference between each of the accesses.
Data from RWDL may be transmitted between RWDL and spine read/write data lines (SRWDL) 426, 428 via a buffer 420. For the DDR configuration, odd and even RWDL 408, 418 may be connected via the buffer 420 and connections 422, 424 to odd and even SRWDL 428, 426 respectively. SRWDL may be used to transmit data between read and write portions of the I/O circuitry 106 which may include an input latch (DINLATCH) 430 which receives data from an external data bus (DQ) via DQ pad 450 and an output first-in, first out (FIFO) circuit 440 which outputs data to the external data bus DQ via an off-chip driver (OCD) 448 connected to the DQ pad 450.
During a write access to the memory device 100 in the DDR configuration, write data may be received serially via the external data bus DQ on the DQ pad 450 and read in to the input latch 430 via receive circuitry 432 which receives the data on the rising and falling edge of the data clock signal DQS. The write data may be selected and provided to the even or odd SRWDL 426, 428 via a multiplexer (MUX) 438 controlled by the column address bit ADDC<0> and buffers 434, 436. In some cases, the control signals to the multiplexer 438 and buffers 434, 436 may only be activated or modified during a write access.
During a read access to the memory device 100 in the DDR configuration, data may be selected from the even or odd SRWDL 426, 428 using a MUX 442 controlled by the column address bit ADDC<0> and input into the FIFO 440 using a data-in signal DPNT_IN. Data for the rising and falling edge (DATAR and DATAF) may be output from the FIFO 440 using a data-out signal DPNT_OUT. The data for the rising and falling edge may output to the OCD 448 via output circuitry 444, 446 which is controlled by the rising and falling edge of the DQS clock signal, (CLK-RISE and CLK-FALL). The OCD 448 may drive the data being output onto the external data bus DQ via the DQ pad 450.
With respect to
In one embodiment, changes to the data path may be implemented by changing connections between the data lines RWDL 408, 418 and SRWDL 426, 428, by changing connections between active elements (e.g., by connecting different active elements to each other or by routing the data path to bypass active elements entirely), and/or by changing control signals which are applied to a given active element (e.g., changes between each of the configurations may route different control signals to a given active element such as the multiplexer 438).
In one embodiment, in the SDR configuration (depicted in
In one embodiment, in the SDR configuration, control signals may be provided to active elements which are different from the control signals provided to the same elements in the DDR configuration. For example, as depicted in
In one embodiment, in the SDR configuration, active elements may be interconnected differently with respect to the connections which are provided to the same elements in the DDR configuration. For example, in addition to providing different control signals and other interconnections, the SDR configuration may provide connections which bypass certain active elements. In the SDR configuration, where a single SRWDL 426 is used, multiplexers 438, 442 for switching data between both SRDWL 426, 428 may not be needed. Thus, the multiplexers 438, 442 may be bypassed by a direct connection between the receive circuitry 432 and buffer circuitry 434 in the input latch 430 and by a direct connection between the SRWDL 426 and FIFO circuitry 440 bypassing the multiplexer 442. Optionally, in one embodiment of the invention, instead of using bypass connections, the control circuitry for each of the multiplexers 438, 442 may be connected to a selected value which provides an appropriate connection through the multiplexers 438, 442 to the SRWDL 426 being used. As mentioned above, the connections described above may be implemented in a single layer such as the M1 metal layer or any other layer.
In some cases, the connections described above may provide benefits which may be useful to a given configuration. For example, with respect to the SDR configuration, when data is being written to the device, the input latch 430 and appropriate portion of the buffer 420 between RWDL 408, 418 may be activated as soon as the write command and address are received without any additional decoding, thereby improving the timing performance of the write command.
Thus, as described above, the SDR configuration and DDR configuration of the memory device 100 may be provided with minimal changes between the configurations. Because changes between each of the configurations may be minimal, the cost of designing, testing, and manufacturing each of the device configurations may be reduced.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
