Patent Application
20150145462
Power converters are often employed to generate and provide AC output power to a load, such as a single or multi-phase AC motor. In certain situations, it is desirable to connect the AC inverter outputs of two or more motor drives or two or more individual inverters to drive a single motor load. Various applications may also employ two parallel-connected rectifiers between an AC grid or other AC power system and a DC bus. In some situations, moreover, parallel-connected inverters are driven by a single (shared) input rectifier or other common DC source, which may include two or more parallel-connected rectifiers. In these situations, the parallel-connected inverters individually provide AC output waveforms (currents, voltages), and the inverters communicate with one another and/or with a main controller to exchange timing and control information such that the AC outputs are synchronized with respect to phase and amplitude. Moreover, parallel inverter configurations typically employ current sharing inductors connected to the output lines of each of the inverters to facilitate current sharing among the parallel-connected inverter stages. Other circuits are sometimes employed at the inverter outputs, such as R-L (du/dt) filters to mitigate reflected wave issues. The addition of current sharing and/or du/dt inductors in the output lines of the parallel-connected inverters, as well as current imbalances in the AC outputs of the inverters generally requires derating of the overall system. For instance, a parallel configuration of two inverters each having a rated output current of 1 A will generally be rated to provide less than 2 A of output current. Moreover, the derating as an overall percentage is typically lowered as additional inverters are connected in parallel (e.g., 2 parallel-connected inverters may be derated by 10%, whereas 5 parallel-connected inverters may be derated by 20%). Output current imbalance among parallel-connected inverters may result from a variety of other causes, including without limitation mismatches between the switching devices of the individual inverters, including collector-emitter saturation voltage differences (Vice-sat) for inverter IGBTs and/or forward voltage (Vf) mismatches between inverter diodes. In addition, certain installations involve connecting two or more inverter modules in an industrial control cabinet or enclosure, where common or shared DC and/or AC connections are made by way of aluminum or copper busbars. In a typical configuration, one inverter module is connected through a longer bus bar length than is another inverter module, and the bus bar impedance leads to differences in voltages and/or currents provided to and/or from a given inverter module. Moreover, propagation delay differences in the signal path of the switching control signals provided to the inverter switching devices (e.g., IGBT gate drive signals) can lead to output current imbalance between parallel-connected inverters, as can propagation delay differences in the communications cabling connecting the individual inverters and local control boards thereof with one another and/or with a main control device. Thus, the derating required for parallel-connected inverters limits the amount of output current and/or voltage that can be provided in the overall system. The amount of required derating can be combated through use of closely matched components, and/or higher precision components (e.g., IGBTs), but component matching increases the overall system cost, and may prevent or inhibit the ability to use multiple manufacturing sources for a given component. Accordingly, there is need for improved parallel inverter system apparatus and control techniques to mitigate output current imbalance and thus reduce the amount of derating required in such systems without increasing system size, cost or complexity.
One or more aspects of the present disclosure are now summarized to facilitate a basic understanding of the disclosure, wherein this summary is not an extensive overview of the disclosure, and is intended neither to identify certain elements of the disclosure, nor to delineate the scope thereof. Rather, the primary purpose of this summary is to present various concepts of the disclosure in a simplified form prior to the more detailed description that is presented hereinafter. The present disclosure provides power conversion systems as well as operating methods and computer readable mediums by which the above and other shortcomings of conventional parallel inverter and/or parallel rectifier system operation can be avoided or mitigated without increasing system cost or complexity, and potentially allowing looser restrictions on system component matching while increasing potential system AC ratings compared with prior approaches.
A power conversion system is provided according to one or more aspects of the present disclosure, including two or more parallel-connected converters such as inverters having AC outputs connected to drive a single load or parallel rectifiers having AC inputs connected to a single AC system, as well as a controller that determines a nominal modulation index for a given AC phase and determines adjusted modulation indices individually associated with a corresponding converter based on individual converter AC current values associated with a given AC phase. The controller further controls pulse width modulation (PWM) operation of the converters for the given AC phase according to the corresponding adjusted modulation indices to counteract AC current imbalance in the power conversion system. In this manner, the controller mitigates imbalance in parallel-connected converters without requiring high precision system components and/or closely matched components and bus bar or cabling impedances. Consequently, higher overall system ratings can be achieved without increasing system cost or size.
The controller in certain embodiments selectively decreases one of the modulation indices and increases another, for example, by adjusting the modulation indices of the converters having the highest and lowest AC currents associated with a given AC phase. Different adjustment techniques may be employed in certain embodiments depending on whether the AC load is motoring or regenerating, for example, lowering the modulation index and hence the controlled AC voltage for the converter having the highest AC current, and increasing the modulation index and hence the AC voltage for the converter having the lowest AC current with respect to a given phase when the load is motoring. Conversely, if the load is regenerating, the converter AC voltage can be increased by raising the modulation index for the converter having the highest AC current, while lowering the AC voltage by decreasing the modulation index for the converter having the lowest AC current.
In certain embodiments, moreover, the controller refrains from adjusting a given converter modulation index beyond a certain predetermined limit, thereby controlling common mode currents within the parallel converter system, and may issue a diagnostic warning or message in the event that the modulation index offset has reached the predetermined limit, as this may indicate the need for replacement of one or more system components or other remedial maintenance.
A method and computer readable medium are provided in accordance with further aspects of the disclosure for operating parallel converters to drive a load. In the method, individual switching converter absolute AC current values associated with a given AC phase are determined, along with a nominal modulation index for the given AC phase. The method further includes offsetting adjusted modulation indices in a given pulse width modulation switching cycle for converters for the given AC phase at least partially according to the individual switching converter absolute AC current values, and controlling converter operation for the given phase according to the corresponding adjusted modulation indices.
In certain implementations a modulation index offset value associated with one of the converters is decreased while the offset value of another converter is increased for the given AC phase at least partially according to the individual switching converter absolute AC current values, and the individual adjusted modulation indices are determined as a sum of the corresponding modulation index offset value and the nominal modulation index for the given AC phase. Certain embodiments involve determining a first converter having a highest absolute AC current value for the given AC phase, determining a second converter having a lowest absolute AC current value, as well as decreasing the adjusted modulation index of one of the first and second converters, and increasing the adjusted modulation index of another of the first and second converters for the given AC phase.
In certain embodiments, the method provides for selectively decreasing the adjusted modulation index of the first switching converter and increasing the adjusted modulation index of the second switching converter when the load is motoring, and vice versa when the load is regenerating. The method may also include selectively refraining from decreasing or increasing an adjusted modulation index beyond a predetermined limit in certain embodiments, whether limited in absolute terms or relative to a computed nominal modulation index, and the method may further involve issuing or initiating a diagnostic signal or warning when an adjusted modulation index reaches the limit.
Further methods and computer readable mediums are provided, including if the load is motoring, selectively decreasing the AC voltage of a first switching converter having a highest absolute AC current value associated with the given AC phase, and selectively increasing the AC voltage of a second switching converter having a lowest absolute AC current value associated with the given AC phase. Otherwise, if the load is regenerating, the method provides for selectively increasing the AC voltage of the first switching converter, and selectively decreasing the AC voltage of the second switching converter associated with the given AC phase.
The following description and drawings set forth certain illustrative implementations of the disclosure in detail, which are indicative of several exemplary ways in which the various principles of the disclosure may be carried out. The illustrated examples, however, are not exhaustive of the many possible embodiments of the disclosure. Other objects, advantages and novel features of the disclosure will be set forth in the following detailed description when considered in conjunction with the drawings, in which:
Referring now to the figures, several embodiments or implementations are hereinafter described in conjunction with the drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the various features are not necessarily drawn to scale. The various concepts of the present disclosure can be implemented for controlling AC current imbalance with respect to parallel-connected inverters and/or with regard to controlling AC current imbalance for parallel-connected rectifiers, which are collectively referred to as “converters” or “switching converters”. In the illustrated embodiments, the disclosed concepts are described in the context of parallel-connected switching inverter type converters within a power conversion system, although the described concepts can alternatively or in combination be employed in controlling operation of parallel-connected rectifiers.
The DC bus in the example of
The individual inverter modules or stages 14-1, 14-2 through 14-N include corresponding local switching controllers 16-1, 16-2 . . . 16-N, respectively, providing switching control signals 15-1, 15-2 through 15-N to corresponding switches S1-S6. Any suitable inverter switching devices S1-S6 may be used, including without limitation insulated gate bipolar transistors (IGBTs), silicon controlled rectifiers (SCRs), gate turn-off thyristors (GTOs), integrated gate commutated thyristors (IGCTs), etc. As seen in
The controllers 16 can include suitable logic or processor-based circuitry and electronic memory storing data and programming code, and may also include signal level amplification and/or driver circuitry (not shown) to provide suitable drive voltage and/or current levels sufficient to selectively actuate the switching devices S1-S6, for instance, such as comparators, carrier wave generators or digital logic/processor elements and signal drivers or combinations of such. Moreover, the controllers 16 can provide the switching control signals 15 according to any suitable pulse width modulation (PWM) technique, including without limitation vector modulation (SVM) carrier-based pulse width modulation, selective harmonic elimination (SHE), etc. In the parallel inverter configuration, moreover, the local controllers 16-1, 16-2 through 16-N are operatively communicatively coupled via the communications cables 19-1, 19-2 through 19N with a main or master controller 18, where the controllers 16, 18 can be any suitable hardware, processor-executed software, processor-executed firmware, programmable logic, analog circuitry, etc. which performs normal motor control tasks, including pulse width modulation operation of the local inverter switches S1-S6. In addition, the local switching controllers 16 receive phase-specific signals or values 30-U, 30-V and 30-W (iU, iV and iW in
As further shown in
The main controller 18 in the illustrated example provides motor control functions 22 according to one or more setpoints 24, such as a motor speed setpoint, torque setpoint, or combinations thereof, etc. In certain implementations, the main controller 18 (or one of the local controllers 16 configured as a master controller) implements one or more closed loop type motor control functions via the motor control component 22 to provide pulse width modulation control of the switches of the parallel-connected inverters 14, by communication via the communications cabling 19. In one possible implementation, the main controller 18 computes modulation indices 28 and corresponding phase angles 26 according to the measured currents 30 and/or one or more further feedback signals or values, such as voltages, torques, motor speed, motor angle, etc., whether sensed or measured or computed or combinations thereof (not shown) for space vector modulation (SVM) operation of the inverters 14. In certain implementations, the unbalanced operation involves the main controller 18 providing a reference vector including a corresponding modulation index 28 (MU, MY and MW, e.g., expressed as percentages in one example) and angle 26 (θU, θY and θW) for each of the phases U, V and W to each of the inverters 14-1, 14-2 through 14-N. The local switching controllers 16 individually control the corresponding inverter stage switching devices according to the three phase-specific reference vectors represented by the corresponding modulation index 28 and angle 26. With these, the local controllers 16 generate the pulse width modulated switching control signals 15 (
The main controller 18 further implements the output current balancing component 20 in order to selectively offset the inverter operation relative to the computed modulation indices 28, and provides individualized sets of adjusted modulation indices 34-1, 34-2 through 34-N to the corresponding local inverter controllers 16-1, 16-2 through 16-N via the communications cables 19-1, 19-2 through 19-N. This offsetting or adjustment is done, at least partially, according to the measured current values 30 provided through the cabling 19 from the local switching controllers 16 to the main controller 18. As seen in
The main controller 18 implements the balancing component 20 which operates generally according to the method 40 illustrated in
In one embodiment, the controller 18 selectively updates one or more of the modulation index offset or change values 32 (ΔMj,k) in each PWM switching cycle according to the output current signals or values iU,k, iV,k and iW,k for each output phase and adds these to the most recent modulation indices 28 (MU, MV and MW) to obtain the adjusted modulation indices 34, and provides the inverter-specific adjusted modulation indices sets 34-1, 34-2 . . . 34-N to the local controllers 16-1, 16-2 . . . 16-N, respectively, along with the most recent phase specific angles 26 (θU, θV and θW) computed via the motor control component 22. The local controllers 16 then utilize the received reference vectors (including an adjusted modulation index 34 and a phase angle 26 for each output phase U, V and W) to generate the corresponding switching control signals 15 for PWM operation of the switches S1-S6 by digital space vector modulation and/or analog sine-triangle pulse width modulation in certain non-limiting examples. For instance, the first controller 16-1 receives the angles θU, θV and θW (26) and the adjusted modulation index set 34-1 (M′U1, M′V1 and M′W1) via the cable 19-1 from the main controller 18, and uses θU and M′U1 to control the switches S1 and S4 associated with the U output phase by implementing two corresponding active vectors and a zero vector according to computed dwell times. Similarly, the controller 16-1 uses θV and M′V1 to control switches S2 and S5 for phase U and uses θW and M′W1 to control switches S3 and S6 for phase W during the current switching cycle.
In certain embodiments, the local controllers 16 compute the dwell times and select the appropriate active and zero vectors and generate the corresponding switching control signals 15 accordingly. In other embodiments, analog sine-triangle pulse width modulation circuitry is implemented in the controllers 16 for generating the switching signals 15. In other embodiments, the controller 18 performs the current balancing by selective adjustment of the modulation indices for only one or two of the phases U, V or W. In various embodiments, moreover, the controller 18 implements the selective modulation index adjustment for output current balancing only with respect to a subset of the controlled inverters 14. In this manner, the central controller 18 coordinates the PWM switching of the N parallel inverters 14 via the communications connections 19, through which the local phase output current values 30 are obtained for computing the balancing offset values 32 and the computed reference vectors 26, 34 are sent to the local controllers 16. This coordination can be augmented by transmission of synchronization signaling via the cabling 19 as needed such that the carriers used in the parallel-connected inverter outputs are synchronized to mitigate circulating currents, with carrier wave information sent through a digital data path via cables 19 in certain implementations.
Referring also to
The process 40 begins at 41 to initiate a new inverter switching cycle, and the local currents iU,k, iV,k and iW,k are measured at 42 for each output phase U, V and W. At 43 in
A determination is made at 45 as to whether the load is regenerating. If not (NO at 45), the process 40 proceeds at 46 to incrementally decrease the inverter phase output voltage modulation index offset value 32 by a fixed or variable increment amount, for example by 0.005% in one non-limiting embodiment, for the inverter having the highest output current for each motor phase for a motoring output load 6. In this regard, lowering the modulation index offset value 32 will have the effect of decreasing the output current from the corresponding inverter 14 for the associated motor phase in the case where the load 6 is motoring. At 47, the controller 18 incrementally increases the inverter phase output voltage modulation index offset value 32 for the inverter having the lowest output current for each given motor phase. This results in an increase in the output current for that inverter 14 for the associated output phase. The controller 18 maintains the previously computed modulation index for subsequent use with or without offsetting in the next PWM switching cycle.
In certain embodiments, a determination is made at 50 as to whether the proposed voltage changes (modulation index offset values 32) equal or exceed a predetermined value or threshold TH, such as 0.5% in one non-limiting example. If so (YES at 50), the controller 18 limits the output voltage change at 51 by refraining from increasing or decreasing the associated modulation index offset value 32 beyond the threshold amount, and may optionally signal a diagnostic message for transmission to a user interface or networked device (not shown) operatively coupled with the system 10 at 52. In this regard, the automatic current balancing can optionally be performed only up to a predetermined amount of output voltage offsetting, for example, to control common mode current flow within the parallel-connected inverter system 10. A diagnostic signal or message at 52 may indicate to an operator, for example, that an external component such as a paralleling inductor has a value significantly out of tolerance and that maintenance should be undertaken. At 53 in
In the case where the load is regenerating (YES at 45 in
While the illustrated embodiments employ incremental changes for the inverters having the highest and lowest output current values for a given phase, other embodiments are possible in which the incremental changes are not of equal step size, for example, with the amount of change being based on some computed value, such as the difference between the absolute current value of a particular inverter phase and the average of all the inverter output currents for that phase, etc.
The balancing concepts of the present disclosure advantageously adapt to changes in component value and/or propagation delay mismatches over time, thus compensating for changes that vary with system temperature, or other environmental variables. In addition, the output current balancing aspects of the present disclosure operate to regulate the imbalance even in the presence of changes to the nominal computed modulation indices 28, and therefore the balancing component 20 operates in conjunction with the closed loop motor control component 22 across the operating ranges of the constituent inverters 14 and thus throughout the overall operating range of the entire system 10. Furthermore, as discussed above, the adaptation of the parallel-connected inverters 14 with respect to output current imbalance advantageously allows reduction in the amount of derating for parallel inverter and/or parallel rectifier systems compared with conventional approaches, and does this without introduction of any additional cost or complexity to the system 10. The concepts of the present disclosure thus facilitate extension of the rating for drives having parallel inverters 14 (i.e. less derating), and provide closed loop imbalance regulation to facilitate immunity to component variations such as IGBT Vice(sat) and diode Vf voltage variation in the inverters 14, as well as to communication delays associated with variable communications cabling lengths, and to impedance variations in DC and/or AC bus bars 13, 17 or other connection impedances. In addition, the system compensates for propagation delays associated with the actual switching of the inverter switching devices S1-S6.
The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, systems, circuits, and the like), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component, such as hardware, processor-executed software, or combinations thereof, which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the illustrated implementations of the disclosure. In addition, although a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Also, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in the detailed description and/or in the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.
