The invention relates to a method and to an apparatus for dealing with write errors when writing information data into flash memory devices, wherein multiple flash memory devices are assigned to a common data bus and in a bus write cycle these flash memory devices are sequentially fed with said information data for storage therein.
NAND flash semiconductor devices, as used in storage devices like e.g. the Grass Valley VENOM solid state recorders, are not error-free in operation. For writing, flash memory devices are physically accessed in a page-oriented mode, whereby one ‘page’ includes e.g. 1024 or 2048 data words and related error correction code. Future flash devices will have a 4096 bytes page size. Erase operations on a specific flash memory can be carried out on specific-size data ‘blocks’ only. Such data block may include 64 pages.
Some of the memory defects are already detected during production of the storage devices and the corresponding memory locations or pages are marked as ‘bad’ and not usable. Specific circuitry avoids information data being stored at such ‘bad’ locations. However, further memory defects will occur during the lifetime and operation of a flash semiconductor. A related processing must prevent that information data intended to be written in such newly defect sections of a flash memory will not be lost. A corresponding processing is described e.g. in WO2007/080031 A1 and in WO2006/108755A1.
A disadvantage of such processing is that the information data, which was intended to be written to defective areas of a flash memory and which is cached e.g. into an SRAM memory, is to be copied to ‘save’ areas within the flash memory after the actual recording or take has been finished. This takes some extra time, and the corresponding information is not secured while the information data are not yet stored into the flash memory section of the recording apparatus. Intermediate malfunctions of the recording apparatus, e.g. an operating error or a power-down caused by an empty battery, will lead to information loss. However, such storage malfunctions are not acceptable in a professional storage system.
A problem to be solved by the invention is to deal properly with information data write errors in flash memory devices, such that the error handling occurs during a write cycle for multiple flash memories attached to a common bus. This problem is solved by the method disclosed in claim 1. An apparatus that utilises this method is disclosed in claim 2.
According to the invention, the dynamic defect management is not processed after a recording has been finished but in parallel to that recording.
Advantageously, the required size of the SRAM memory, which stores information data that were initially intended for storage in defect flash memory pages, can be smaller.
Because the I/O data rate of recently commercially available NAND flash devices has been increased with respect to that of previous flash device types, the available bandwidth now remaining can be used for the inventive internal copy process. A save storage of all information data is facilitated, even in case of currently unknown types of defects in flash memory devices. No information will be lost in case of recording apparatus malfunction or a system halt due to low battery status occurring between the beginning of a recording and the end of a take.
In principle, the inventive method is suited for dealing with write errors when writing information data into flash memory devices, wherein two or more flash memory devices are assigned to a common data bus and in a bus write cycle two or more of these flash memory devices are sequentially fed with said information data for storage therein, said method including the steps:
In principle the inventive apparatus is suited for dealing with write errors when writing information data into flash memory devices, said apparatus including:
Advantageous additional embodiments of the invention are disclosed in the respective dependent claims.
Exemplary embodiments of the invention are described with reference to the accompanying drawings, which show in:
The write access to known NAND flash memory devices is performed in two steps:
An amount of e.g. 2048 or 4096 bytes (i.e. one ‘page’) of information data is collected from the I/O pin of a flash memory device and is stored into an internal buffer memory. The content of the internal buffer memory (one page) is copied to the flash memory area.
On one hand, the above copy process is relatively slow, typically 700 μs copy time for one page. On the other hand, the access to the internal buffer memory from the outside of the flash memory device is relatively fast: a bus data rate of 20-40 MB/s for current devices and up to 200 MB/s for next-generation flash memory devices.
For achieving an increased data rate, the NAND flash devices can be arranged in the recording apparatus as a matrix of memories (as depicted in FIG. 1 of WO2007/080031A1 and in FIG. 1 of WO2006/108755A1) that is controlled by several buses, to each bus B of which N NAND flash devices Device0, Device1, Device2, . . . , DeviceN−2, DeviceN−1 are connected, as shown in
According to the invention, extra bandwidth (with respect to the required application bandwidth) is added by either adding one or more additional flash memory devices to bus or buses B, as shown in
During an error-free page writing operation period, one flash device—e.g. Device0 in FIG. 2—on bus B is not used for writing within a current write cycle.
In
During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for initialising and carrying out a copy operation from the SRAM memory to an assumed save or non-defective flash page of that flash memory device, as shown in
In most cases, three or more flash memory devices Device0, Device1, . . . , DeviceN−1 are assigned or connected to the common data bus B, and in a bus write cycle two or more of these flash memory devices are sequentially fed with the information data for storage therein. Within a cache memory device, in a first step the information data are written into the internal cache memory section of the flash device and in a second step are transferred or programmed from that cache memory to the flash memory kernel.
However, in case a ‘cache mode’ is used for the flash memories, the flash memory device allows to write the information data into the cache memory section of the flash device while the previously received information data are programmed (i.e. stored) from the cache memory into the flash memory kernel (the flash memory device has two cache memory sections or two cache memories). In such ‘cache mode’ operation, at least two flash memory devices Device0, Device1, . . . , DeviceN−1 are assigned or connected to the common data bus B.
Number | Date | Country | Kind |
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09305611 | Jun 2009 | EP | regional |
This application is a Continuation of co-pending U.S. patent application Ser. No. 12/819,432 filed on Jun. 21, 2010, which is incorporated herein by reference in its entirety, and which application claims the benefit, under 35 U.S.C. 119 of European Patent application 09305611.7 filed on Jun. 29, 2009.
Number | Name | Date | Kind |
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4694454 | Matsuura | Sep 1987 | A |
20090037652 | Yu et al. | Feb 2009 | A1 |
20090043948 | Wittenburg et al. | Feb 2009 | A1 |
20090083591 | Brune et al. | Mar 2009 | A1 |
Number | Date | Country |
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2006108755 | Oct 2006 | WO |
2007080031 | Jul 2007 | WO |
Entry |
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European Search Report dated Dec. 3, 2009 for EP 09305611. |
Number | Date | Country | |
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20130067272 A1 | Mar 2013 | US |
Number | Date | Country | |
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Parent | 12819432 | Jun 2010 | US |
Child | 13672122 | US |