The invention relates to RF receivers, and in particular, to a demodulation method and apparatus simplifying frequency up and down conversions.
a shows a conventional direct transmitter. A base band signal is provided by a digital signal processor (DSP) 110, processing through two paths, in-phase and quadrature, before transmitting. The digital to analog converters (DAC) 102 digitize the base band signal, the low pass filters (LPF) 104 eliminate noise components, and the variable gain amplifiers (VGA) 106 integrate the signal powers before modulation. Thereafter, the mixer 108 modulates the digital baseband signals by an oscillation frequency generated by a reference generator 130, generating an RF signal. The RF signal is further amplified by a limiting amplifier 140, filtered by an RF filter 150 to eliminate image components, amplified by an amplifier 160 to boost power, and then transmitted via the antenna 120.
b shows a conventional zero intermediate frequency (ZIF) receiver. The demodulation process is subsequently reverse of the transmission in
c shows a conventional very low intermediate frequency (VLIF) receiver. In this case, the mixer 108 does not directly down convert the RF signal to a baseband signal. To the contrary, the RF signal is down converted to a low frequency. The low frequency is typically ¼ channel spacing, for example, 150 KHz for a PHS system. The low frequency signal is then filtered by a band pass filter 105, eliminating image components and reserving low frequency components. The advantages of the VLIF architecture are, high integratablity and a lack of DC offset problems, thus VLIF is applicable for general narrow band communications such as GSM compared to the conventional super heterodyne architecture or ZIF architecture. Additionally, the VLIF architecture has greater signal strength than the ZIF architecture.
The RF signal is down converted to baseband or low frequency without intermediate stages, thus, the ZIF and VLIF architectures can not be utilized for a system requiring IF signals, such as a PHS system. Although a super heterodyne architecture may generate an IF signal, the implementation of the surface acoustic wave (SAW) filter, however, is too complicated to integrate in one chip. Thus, an integrated IF demodulator is desirable.
An exemplary RF receiver is provided, comprising a down converter, a harmonic filter, a first and second up converter. The down converter receives and down converts an RF signal to a first frequency to generate a first in-phase signal and a first quadrature signal. The harmonic filter coupled to the down converter receives the first in-phase signal and the first quadrature signal, and performs limiting amplification to generate a second in-phase signal and a second quadrature signal. The first up converter coupled to the harmonic filter receives the second in-phase and quadrature signals, up converting the frequency thereof to a second frequency to generate a third in-phase signal and a quadrature signal. The second up converter coupled to the first up converter receives the third in-phase and quadrature signals and up converts the frequency thereof to a third frequency to generate an intermediate frequency (IF) signal.
The RF receiver further comprises a local oscillator comprising a reference generator, a PLL circuit, a first divider and a second divider. The reference generator provides a reference signal. The PLL circuit coupled to the reference generator generates a first sinusoidal wave and a first cosine wave based on the reference signal. The first divider coupled to the reference generator generates a second sinusoidal wave and a second cosine wave by looking up a digital table based on the reference signal. The second divider coupled to the reference generator generates a third sinusoidal wave and a third cosine wave based on the reference signal. The reference signal is 19.2 MHz, the first frequency is 1.75 GHz, the second frequency is 1.05 MHz, and the third frequency is 9.6 MHz.
Another embodiment of the invention provides a demodulation method. An RF signal is down converted to generate a first in-phase signal and a first quadrature signal of a first frequency. Limiting amplification is performed on the first in-phase signal and the first quadrature signal to generate a second in-phase signal and a second quadrature signal. The frequency of the second in-phase and quadrature signals are up converted to a third in-phase signal and a quadrature signal of a second frequency. The third in-phase and quadrature signals are up converted to generate an intermediate frequency (IF) signal of a third frequency.
The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which:
a shows a conventional direct transmitter;
b shows a conventional zero intermediate frequency (ZIF) receiver;
c shows a conventional very low intermediate frequency (VLIF) receiver;
The harmonic filter 204 comprises limiting amplifiers 222a and 222b, amplifying the first in-phase signal I1 and first quadrature signal Q1 to make the amplitude unique without losing phase information. The first polyphase filter 224 eliminates harmonic components in the amplified first in-phase signal I1 and first quadrature signal Q1. Thus, as a conventional unit, the harmonic filter 204 is not further described herein.
The first up converter 206 comprises four mixers 232a to 232d, two adders 234 and a second polyphase filter 236. The mixers perform complex mixing to cancel the image components. A complex mixing algorithm is adaptable for a wide range frequency modulation/demodulation with excellent image rejection ability. The second cosine signal cos ω2t and second sinusoidal signal sin ω2t are 1.05 MHz, thereby the second in-phase signal I2 and second quadrature signal Q2 are mixed to obtain 1.2 MHz third in-phase signal I3 and third quadrature signal Q3. The mixer 232a multiplies the second in-phase signal I2 by the second cosine signal cos ω2t, and the mixer 232b multiplies the second in-phase signal I2 and the second sinusoidal signal sin ω2t. The mixer 232c multiplies the second quadrature signal Q2 and the second sinusoidal signal sin ω2t, and the mixer 232d multiplies the second quadrature signal Q2 and the second cosine signal cos ω2t. An adder 234a subtracts the output of mixer 232c from the output of mixer 232a, and an adder 234b adds the output of the mixers 232b and 232d. Thereafter, the second polyphase filter 236 filters the subtraction and the addition result to generate the third in-phase signal I3 and third quadrature signal Q3.
The third in-phase signal I3 and third quadrature signal Q3 are 1.2 MHz, and the second up converter 208 receives the third cosine signal cos ω3t and third sinusoidal signal sin ω3t of 9.6 MHz, thus the mixed IF is 10.8 MHz. The second up converter 208 comprises a mixer 242a mixing the third in-phase signal I3 and the third sinusoidal signal sin ω3t, and a mixer 242b mixing the third quadrature signal Q3 and the third cosine signal cos ω3t. An adder 244 adds the mixed results from the mixers 242a and 242b, and a band pass filter 246 filters the output from the adder 244 to reserve the IF components. The second up converter 208 also comprises a second limiting amplifier 248, amplifying the outputs from the band pass filter 246 to generate the IF signal.
The 9.6 MHz third sinusoidal signal sin ω3t and third cosine signal cos ω3t are required to up convert the second in-phase signal I2 and second quadrature signal Q2 to 10.8 MHz IF. A second divider 308 is coupled to the reference generator 304, dividing the 19.2 MHz fref by half to obtain the desired third sinusoidal signal sin ω3t and third cosine signal cos ω3t. The second divider 308 comprises a duty cycle unit 318, generating a square wave from the fref having a duty cycle of 1:1 to improve sideband rejection quality. A half divider 328 then divides the frequency of the square wave by half to obtain the third sinusoidal signal sin ω3t and the third cosine signal cos ω3t. In local oscillator 300, only one PLL is required, making the implementation compact, reducing cost and avoiding interference problems.
While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Number | Date | Country | Kind |
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94119471 | Jun 2005 | TW | national |