Claims
- 1. An apparatus for detecting periodical pulse signals corresponding to marks from a recording medium in which the marks for generating a clock signal are periodically recorded, comprising:
- a reproducing transducer for reading a reproduction signal including a plurality of said pulse signals from the recording medium by scanning said medium;
- first through n-th gate signal generating circuits, each of which generates a gate signal with a predetermined width from respective first through n-th consecutive pulse signals from among the plurality of pulse signals, where n is an integer of 2 or more;
- a selection circuit for selectively outputting the gate signal which is generated by the lowest-order circuit among said n gate signal generating circuits when none of the n pulse signals to function as the bases of gate signal generation are missing;
- an extracting circuit for extracting from said reproduction signal only pulse signals existing within the period during which the gate signal is being output from the selection circuit; and
- a clock signal generating circuit for generating a clock signal based on said extracted pulse signal.
- 2. An apparatus according to claim 1, further comprising a gate release circuit for suspending extraction by the gate signal and inputting the reproduction signal directly into the clock signal generating circuit when the pulse signals for all of said "n" number of gate signal generating circuits are missing.
- 3. An apparatus according to claim 2, wherein said gate release circuit restarts extraction by the gate signal when a pulse signal is detected from the reproduction signal not subjected to extraction by the gate signal.
- 4. An apparatus according to claim 3, wherein said gate release circuit comprises a retriggerable monostable multivibrator into which the output from the selection circuit is input and an OR gate which outputs a logical sum signal of the outputs of said multivibrator and selection circuit to the signal extracting circuit.
- 5. An apparatus according to claim 1, wherein each of said gate signal generating circuits comprises a delay circuit for causing the detection pulse signal to be delayed by time t.sub.d and a window generator for generating a gate signal with the width t.sub.w from the output of the delay circuit, and wherein the following condition is satisfied:
- t.sub.d <k.multidot.t.sub.c ; and
- t.sub.d +t.sub.w >k.multidot.t.sub.c +t.sub.p.
- when t.sub.c is a period of a pulse signal, t.sub.p is a width of the pulse signal and k is an integer from 1 to n.
- 6. An apparatus according to claim 5, wherein said selection circuit comprises a first OR gate for outputting a logical sum signal of the outputs of the "n" number of gate signal generating circuits to the signal extraction circuit and a second OR gate for resetting the delay circuit for each respective gate signal generating circuit using the logical sum signal of the outputs of the delay circuits in all gate signal generating circuits of a lower order than the respective delay circuit.
- 7. An apparatus according to claim 1, wherein said extraction circuit comprises an AND gate which outputs a logical multiplication signal of the output from the selection circuit and the reproduction signal to the clock signal generating circuit.
- 8. An apparatus according to claim 1, further comprising a binarizing circuit which binarizes the output of said reproducing transducer to be input into the extracting circuit.
- 9. An apparatus according to claim 1, further comprising a decoding circuit which decodes data from the reproduction signal by using the clock signal generated by said clock signal generating circuit.
- 10. An apparatus according to claim 1, wherein marks are recorded on said recording medium according to the format of sample servo method.
- 11. An apparatus according to claim 1, wherein said recording medium possesses tracks divided into plural sectors and said marks comprise sector marks positioned at the head of each sector.
- 12. An apparatus according to claim 1, wherein said marks comprise resynchronizing signals recorded on the recording medium after every predetermined amount of data.
- 13. A detecting method for detecting periodical pulse signals corresponding to marks from a recording medium on which the marks for generating clock signals are periodically recorded, comprising the steps of:
- scanning said recording medium with a reproducing transducer and reading reproduction signals including said pulse signals;
- generating a gate signal with a predetermined width based on one of the pulse signals when said one pulse signal is not missing;
- generating a gate signal with a predetermined width based on a pulse occurring one period before said one pulse signal when said one pulse signal is missing; and
- extracting only pulse signals existing within a period during which the gate signal is being output from said reproduction signal.
- 14. A method according to claim 13 further comprising the step for generating gates signal on the basis of pulse signal in further one period before when the pulse signal in one period before is missing.
- 15. A detecting method according to claim 14, wherein, when a predetermined number of consecutive pulse signals are missing, said gate signal width is extended and the output of the gate signal is continued until a pulse signal appears in the reproduction signal.
- 16. A method according to claim 13, wherein the following condition is satisfied:
- t.sub.d <k.multidot.t.sub.c, and
- t.sub.d +tw>k.multidot.t.sub.c +t.sub.p,
- where t.sub.w is a width of the gate signal, t.sub.d is the time to rise the gate signal from the pulse signal functioning as the base of the gate signal generation, t.sub.c is a period of the pulse signal, t.sub.p is a width of the pulse signal and k is one of the integers of 1 or more.
- 17. An apparatus for extracting pulse signals from a time series signal including pulse signals to be output with a constant period, comprising:
- first through n-th gate signal generating circuits, each of which generates a gate signal with a predetermined width from respective first through n-th consecutive pulse signals from among the plurality of pulse signals, where n is an integer of 2 or more;
- a selection circuit for selectively outputting the gate signal generated by the lowest-order circuit among the gate signal generating circuits when none of the n pulse signals to function as the bases of gate signal generation are missing; and
- an extracting circuit for extracting from said time series signal only pulse signals existing within the period during which the gate signal is being output from said selection circuit.
- 18. An apparatus according to claim 17, further comprising a gate release circuit for suspending the extraction by the gate signal and causing the time series signal to be output as it is when the pulse signals for all of said "n" number of gate signal generating circuits are missing.
- 19. An apparatus according to claim 18, wherein said gate release circuit restarts the extraction by the gate signal when a pulse signal is output from the time series signal not subjected to extraction by the gate signal.
- 20. An apparatus according to claim 19, wherein said gate release circuit comprises a retriggerable monostable multivibrator into which the output from the selection circuit is input and an OR gate which outputs logical sum signal of the outputs of said vibrator and said selection circuit to the extracting circuit.
- 21. An apparatus according to claim 17, wherein said extracting circuit comprises an AND gate which outputs logical multiplication signal of the output of the selection circuit and the time series signal.
- 22. An apparatus according to claim 17, wherein each of said gate signal generating circuits comprises a delay circuit for causing the detection pulse signal to be delayed by time t.sub.d and a window generator for generating a gate signal with the width t.sub.w from the output of the delay circuit, and wherein the following condition is satisfied:
- t.sub.d <k.multidot.t.sub.c, and
- t.sub.d +t.sub.w >k.multidot.t.sub.c +t.sub.p
- where t.sub.c is a period of the pulse signal, t.sub.p is a width of the pulse signal and k is one of the integers from 1 to n.
- 23. An apparatus according to claim 22, wherein said selection circuit comprises a first OR gate for outputting logical sum signal of the outputs of "n" number of gate signal generating circuits to the extracting circuit and a second OR gate for resetting the delay circuit in the respective gate signal generating circuit by logical sum signal of the outputs of the delay circuits in all gate signal generating circuits possessing lower order than the delay circuit.
- 24. An extraction method for extracting a pulse signal from a time series signal including pulse signals which are output at a constant period, comprising the steps of:
- generating a gate signal with a predetermined width based on one of the pulse signals when said one pulse signal is not missing;
- generating a gate signal with a predetermined width based on the pulse signal occurring one period before said one pulse signal when said one pulse signal is missing; and
- extracting from said time series signal only the pulse signals existing during a period when the gate signal is being generated.
- 25. A method according to claim 24 further comprising the step for generating the gate signal on the basis of a pulse signal in a further one period before when the pulse signal in the one period before is missing.
- 26. A method according to claim 24, wherein the following condition is satisfied:
- t.sub.d >k.multidot.t.sub.c, and
- t.sub.d +t.sub.w >k.multidot.t.sub.c +t.sub.p
- where t.sub.w is a width of the gate signal, t.sub.d is the time to rise the gate signal from the pulse signal functioning as the base of the gate signal generation, t.sub.c is a period of the pulse signal, t.sub.p is a width of the pulse signal and k is one of the integers of 1 or more.
- 27. An extraction method according to claim 25, wherein, when a predetermined number of consecutive pulse signals are missing, the gate signal width is extended and the output of the gate signal is continued until a pulse signal appears in the time series signal.
Priority Claims (2)
Number |
Date |
Country |
Kind |
1-242145 |
Sep 1989 |
JPX |
|
2-242793 |
Sep 1990 |
JPX |
|
Parent Case Info
This application is a continuation of application Ser. No. 08/075,342, filed Jun. 11, 1993, now abandoned, which is a continuation of application Ser. No. 07/584,797, filed Sep. 19, 1990, now abandoned.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4580176 |
Graves et al. |
Apr 1986 |
|
4933782 |
Simonson et al. |
Jun 1990 |
|
4979192 |
Shimizume et al. |
Dec 1990 |
|
Continuations (2)
|
Number |
Date |
Country |
Parent |
75342 |
Jun 1993 |
|
Parent |
584797 |
Sep 1990 |
|