By Fancois Gigon, "Modeling and Simulation of the 16 Megabit Eprom Cell for Write/Read Operation with a Compact Spice Model", IEEE, IEDM 90, 1990, pp. 205-208. |
By Valerie Taylor, "Sparse Matrix Computations: Implications for Cache Designs", IEEE, 1992, pp. 598-607. |
By Yan et al., "A New Resonant-Tunnel Diode-Based Multivalued Memory Circuit Using a MESFET Depletion Load", IEEE Journal of Solid-State Circuits, vol. 27, No. 8, Aug. 1992, pp. 1198-1202. |
By Keeney et al., "Complete Transient Simulation of Flash EEPROM Devices", IEEE Transactions on Electron Devices, vol. 39, No. 12, Dec. 1992, pp. 2750-2757. |
By Gjessing et al., "Performance of the RamLink Memory Architecture", IEEE Proceddings of the 27th Annual Hawaii Int'l Conference on System Sciences, 1994, pp. 154-162. |
By Chang et al., "Evaluation of sequential-in-random-out memory device", IEEE Electronics Letters, Apr. 13th, 1995, vol. 31, No. 8, pp. 620-621. |