METHOD AND APPARATUS FOR DIRECT BACKUP OF MEMORY CIRCUITS

Abstract

An integrated circuit employs at least one active memory circuit and at least one memory state backup circuit wherein the at least one memory state backup circuit includes at least one passive variable resistance memory cell and at least one passive variable resistance memory cell interface that are used to backup data from the active memory circuit to the PVRM cell. Data is then placed back into the active memory circuit from the PVRM cell during a restore operation. The PVRM cell interface is operative to read the PVRM cell in response to a restore signal. PVRM cell interface control logic is operative to remove power to the PVRM cell after backup of the data to the PVRM cell from the active memory circuit. A PVRM cell (e.g., a bit cell) is added to each memory circuit that stores state information on an integrated circuit.

Description

BACKGROUND OF THE INVENTION

The disclosure relates generally to circuits and methods to backup state information in integrated circuits and more particularly to circuits and methods that save the state of the processor or logic chip and methods for performing same.

Logic chips and processors such as central processing units (CPUs), graphics processing units (GPUs), DSPs and other processing circuits employ known solutions to save the state information that are in various locations throughout the processor when, for example, power is to be shut down on the device or for switching to handle different processing threads or for other suitable purposes. Flip-flops as known in the art may be used in pipelines to store state information and may be used, for example, in state machines or any other suitable structure to allow devices to start and stop when power is to be removed, for example or if a pipeline is to be temporarily held to allow another thread to be processed. Saving the state of the processor can involve the tedious process of reading all of the architected states of the chip (or part of the chip) that is to be powered off and saved out to a section of the chip not to be powered off or power gated. Other solutions utilize the writing of the state of the chip onto a system bus to an off-chip non-volatile storage device that retains the data after power has been removed, such as a ROM disk or other non-volatile storage.

FIG. 1 illustrates one example of a prior art device 100 that employs a chip or system bus 102 that communicate with a non-volatile disk memory 104 (e.g., hard drive) or other storage 106. An integrated circuit chip 108 (e.g., die or packaged die) may be connected to the disk memory 104 via the chip or system bus 102. The integrated circuit chip 108 may include, for example, an input/output stage 110, cache memory 112, register files 114 and one or more execution units 116. Control logic 118 provides control of the various stages to effect processing. Active memory circuits (e.g., that are made from CMOS transistors or other active memory structures) in the form of flip-flops 120, for example, may be used to store information throughout the integrated circuit as well. Other memory circuits such as the register file, as known in the art, may store state elements for computations for the execution unit. The flip-flops 120 store states of the processor and the cache memory 112 may be SRAM cache or other suitable cache. Memory circuits such as flip-flops, registers, register files, SRAM and other memory circuits that store state information can be quite voluminous particularly in complex processors such as CPUs, GPUs and other processors. Memory circuits as used herein include, for example, active memory circuits that employ, for example, active transistors such as CMOS transistors or other suitable active devices. The flip-flops 120 may be connected to scan chains that are used for testing the integrated circuit prior to packaging and may also be used to scan out state information from various circuits in the chip prior to power down as known in the art. The scan chains may typically operate at a low frequency such as 100 MHz and typically scan out state data in a serialized fashion which can take an inordinate amount of time. The state information may be saved onto the non-volatile disk 104. Once stored, power to the section of the chip or system can be removed. This is sometimes referred to as power gating.

To restore the state, the reverse process is executed. The section of the chip, entire chip or system is powered up and the state is restored to its previous state from the save location and execution is resumed from the previous store point. Such state saving techniques can require significant amounts of power to save and restore the state of entire sections of a chip, the entire chip or system. This can defeat the purpose of power gating in an integrated circuit which allows the reduction or removal of power from subsections or portions of the chip to save power when they are not in use or otherwise slow down the operation to conserve power. Such power gating is useful for mobile devices for example. Such power gated integrated circuits may be used, for example, in handheld devices such as smart phones, laptops, tablet devices or any other suitable mobile devices. Energy efficiency is becoming more commonplace in non-mobile devices as well.

It is also known in the art to use shadow flip-flops that are active circuits that are connected to active flip-flops to attempt to save state. However, shadow flip-flops are typically connected to a separate supply voltage to keep the flip-flop on during power gating so that the data is not lost. This results in additional leakage current from the many shadow flip-flops that are employed to save state, drawing unnecessary power and adding unnecessary temperature increases.

A need exists for an improved state saving circuit and method.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more readily understood in view of the following description when accompanied by the below figures and wherein like reference numerals represent like elements, wherein:

FIG. 1 is a block diagram illustrating one example of a prior art system that employs a state saving operation;

FIG. 2 is a block diagram illustrating one example of a prior art flip-flop;

FIG. 3 is a block diagram illustrating one example of an integrated circuit employing a memory state backup circuit in accordance with one example set forth in the disclosure;

FIG. 4 is a block diagram of a portion of an integrated circuit in accordance with one example set forth in the disclosure;

FIG. 5 is a block diagram of a portion of an integrated circuit in accordance with one example set forth in the disclosure;

FIG. 6 is a block diagram generally illustrating a register with a memory state backup circuit in accordance with one example set forth in the disclosure; and

FIG. 7 is a flowchart illustrating one example of a method for providing state backup in an integrated circuit in accordance with one example set forth in the disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Briefly, an integrated circuit employs at least one active memory circuit and at least one memory state backup circuit wherein at least one memory state backup circuit includes at least one passive variable resistance memory (PVRM) cell and at least one passive variable resistance memory cell interface that are used to backup data from the active memory circuit to the PVRM cell. Data is then placed back into the active memory circuit from the PVRM cell during a restore operation. The PVRM cell interface is operative to read the PVRM cell in response to a restore signal. PVRM cell interface control logic is operative to remove power to the PVRM cell after backup of the data to the PVRM cell from the active memory circuit. A PVRM cell (e.g., a bit cell) is added to each memory circuit that stores state information on an integrated circuit. At the point of power gating the memory circuit, the data therein is transferred from the volatile section of the active memory circuit into the non-volatile PVRM cell using the appropriate save control signals. Once the PVRM cell is populated, power may be removed from the active memory circuit and from the PVRM cell since it is a non-volatile storage mechanism. Once data is restored to the memory circuit using restore control signals, the normal operation of the memory circuit may resume.

In one example, a new flip-flop design is employed that may provide direct backup of data in a flip-flop. In another example, the PVRM cell is written to each time the memory circuit is written to provide an always backed up and ready to be power gated flip-flop. In another example, a flip-flop or other memory circuit employs an active master latch stage and subsequent (serial) passive variable resistance memory based slave stage that stores the state from the master latch each time data is latched in the master latch.

Among other benefits, simplified power gating may be employed on a circuit, system level or integrated circuit level as there is no need to provide methods and paths to read the state of each flip-flop, register file and SRAM. Instead, when the clock is stopped to a flip-flop, for example, the data in the active memory circuit is captured in the co-resident passive variable resistance memory cell and power can be removed to the circuit. In order to return to the operational state, the power can be turned back on for the flip-flop and the state of the co-resident passive variable memory cell can be immediately written to the memory circuit and the clock can be started again. The resulting operation can be much faster than conventional techniques and more efficient allowing power savings over smaller intervals of time and may be easier to implement since the passive variable resistance cell can be built as co-resident with a flip-flop within an integrated circuit. In addition, power to the passive variable resistance memory cells can also be removed providing additional power savings. Since the passive variable resistance state backup circuitry is located on-die, the power supply of the chip may be shut off without losing state information on a chip level. Other benefits will be recognized by those of ordinary skill in the art.

FIG. 2 illustrates a prior art flip-flop circuit 200 made with active devices as known in the art. A block diagram of the flip-flop is shown as block 202. The active memory circuit 200, in this case a flip-flop, receives input data 208 on an input of the memory circuit and generates an output Q 210. A clock input 212 clocks the data into a master latch 214 through an inverter 216 and a switch transistor 218 as known in the art. A slave latch 220 has an input connected to the output of the master latch through a second switch transistor 222 that receives the output from a second inverter 224 as known in the art. The switch transistor 222 passes output data from the master latch 214 based on the clock input signal 212 to the slave latch 220. The clock signal 212 may be generated by any suitable clock source as known in the art.

FIG. 3 illustrates one example of an integrated circuit 300 employing an active memory circuit 200, in this example a flip-flop of the type shown in FIG. 2 and at least one memory state backup circuit 302 that is connected to the active memory circuit 200. The memory state backup circuit 302 includes at least one passive variable resistance memory (PVRM) cell 304 which in this example is illustrated as being a 1 bit cell, and at least one PVRM cell interface 306 that is coupled to the active memory circuit in this example through a save switch 307 and restore switch 308. The switches are shown to be active CMOS transistors, but other types of switches may also be used. The PVRM cell interface 306 and PVRM cell 304 backup data from the active memory circuit 200. The PVRM cell interface 306 controls reads and writes (e.g., the setting of a resistance value and sensing thereof) to the PVRM cell to back up data from the active memory circuit 200 to the PVRM cell 304 and can be constructed as known in the art. The integrated circuit 300 also includes PVRM cell interface control logic 310 that provides a power control signal 312 to the PVRM cell interface 306 to remove power to the PVRM cell after backup of the data from the active memory circuit to the PVRM cell. The PVRM cell interface control logic 310 may be made from active circuits such as transistors, state machines, programmed processors or any suitable logic to operate as described herein. In operation, the PVRM cell interface control logic 310 also may control power (e.g., remove or add) to the slave latch and master latch shown by power control signals 312 and 314 or other logic in the circuit if desired. However, separate power control logic may be employed if desired.

FIG. 3 illustrates a clock circuit 307 that is coupled to the input of the switch 222 provide clocking of the switch. The clock circuit may be any suitable clock generation circuit as known in the art.

The PVRM interface 306 controls the PVRM cell to store a logical 1 when the save switch is closed and Q is a logical 1 and stores a 0 if Q is 0. Other logic levels may also be used. For example, since the PVRM cell is a passive variable resistance structure, the single bit can be used to represent multiple states.

The restore switch 308 is coupled to an input 311 of the active memory circuit, in this example to the input of master latch 214 and to an output of the PVRM cell interface 306. The restore switch 308 is responsive to a restore signal 320 to cause the backup data in the PVRM cell to be input to the active memory circuit (e.g., the master latch). The PVRM interface reads out the PVRM value when the restore switch 308 is active. The save switch 307 is coupled to an output of the active memory circuit 200 and in this case, is coupled to the output of slave latch 220 and is also coupled to an input of the PVRM interface 306. The save switch is responsive to a backup signal 322 to pass data from the active memory circuit for example stored in slave latch 220 to PVRM cell 304. The control signals such as the save signal 322 and the restore signal 320 may be generated by any suitable control logic such as a processor executing a software application on the integrated circuit 300, dedicated hardware that automatically controls the state store operation during power gating, or any other suitable control mechanism. FIG. 3 also illustrates a diagrammatic representation 330 of the circuit shown illustrating a new flip-flop circuit with a built-in non-volatile state store mechanism which in this example is done with a passive memory circuit configuration.

The passive variable resistance memory cell 304 may be formed by thin-film deposition techniques such as CVD, thermal evaporation, sputtering, MBE, electroplating, spin-coating, or any other suitable techniques. The material of the passive variable resistance memory cell may be any suitable variable resistance material that is capable of storing state by resistance. Depending on the specific type of passive variable resistance memory, the material of the passive variable resistance memory layer may include, for example, one or more thin-film oxides (e.g., TiO₂, SiO₂, NiO, CeO₂, VO₂, V₂O₅, Nb₂O₅, Ti₂O₃, WO₃, Ta₂O₅, ZrO₂, IZO, ITO, etc.) for memristors, chalcogenide for phase-change memory, and ferromagnetic materials (e.g., CoFeB incorporated in MgO) for magnetoresistive memory.

It is known in the art that memory may be implemented by an array of memory cells. Each memory cell of the array includes a memory region as a place to store state, which represents one bit of information. In order to access each memory cell, the array of memory is organized by rows and columns, and the intersection point of each row-column pair is a memory region. The rows are also called word lines, whereas the columns are named bit lines.

In this example embodiment, the passive variable resistance memory cell 304 (e.g. one bit) may be a memristor of any suitable design. The passive variable resistance memory cell in this example embodiment, is implemented as a memory layer including a memristor passive variable-resistive memory cell (e.g., each 1 bit) and may be of any suitable design. Since a memristor includes a memory region (e.g., a layer of TiO₂) between two metal contacts (e.g., platinum wires), memristors could be accessed in a cross point array style (i.e., crossed-wire pairs) with alternating current to non-destructively read out the resistance of each memory cell. A cross point array is an array of memory regions that can connect each wire in one set of parallel wires to every member of a second set of parallel wires that intersects the first set (usually the two sets of wires are perpendicular to each other, but this is not a necessary condition). The memristor disclosed herein may be fabricated using a wide range of material deposition and processing techniques. One example is disclosed in corresponding U.S. Patent Application Publication No. 2008/0090337, having a title “ELECTRICALLY ACTUATED SWITCH”, which is incorporated herein by reference.

In this example, first, a lower electrode is fabricated above the actual memory cell using conventional techniques such as photolithography or electron beam lithography, or by more advanced techniques, such as imprint lithography. This may be, for example, a bottom wire of a crossed-wire pair. The material of the lower electrode may be either metal or semiconductor material, preferably, platinum.

In this example, the next component of the memristor to be fabricated is the non-covalent interface layer, and may be omitted if greater mechanical strength is required, at the expense of slower switching at higher applied voltages. In this case, a layer of some inert material is deposited. This could be a molecular monolayer formed by a Langmuir-Blodgett (LB) process or it could be a self-assembled monolayer (SAM). In general, this interface layer may form only weak van der Waals-type bonds to the lower electrode and a primary layer of the memory region. Alternatively, this interface layer may be a thin layer of ice deposited onto a cooled substrate. The material to form the ice may be an inert gas such as argon, or it could be a species such as CO₂. In this case, the ice is a sacrificial layer that prevents strong chemical bonding between the lower electrode and the primary layer, and is lost from the system by heating the substrate later in the processing sequence to sublime the ice away. One skilled in this art can easily conceive of other ways to form weakly bonded interfaces between the lower electrode and the primary layer.

Next, the material for the primary layer is deposited. This can be done by a wide variety of conventional physical and chemical techniques, including evaporation from a Knudsen cell, electron beam evaporation from a crucible, sputtering from a target, or various forms of chemical vapor or beam growth from reactive precursors. The film may be in the range from 1 to 30 nanometers (nm) thick, and it may be grown to be free of dopants. Depending on the thickness of the primary layer, it may be nanocrystalline, nanoporous or amorphous in order to increase the speed with which ions can drift in the material to achieve doping by ion injection or undoping by ion ejection from the primary layer. Appropriate growth conditions, such as deposition speed and substrate temperature, may be chosen to achieve the chemical composition and local atomic structure desired for this initially insulating or low conductivity primary layer.

The next layer is a dopant source layer, or a secondary layer, for the primary layer, which may also be deposited by any of the techniques mentioned above. This material is chosen to provide the appropriate doping species for the primary layer. This secondary layer is chosen to be chemically compatible with the primary layer, e.g., the two materials should not react chemically and irreversibly with each other to form a third material. One example of a pair of materials that can be used as the primary and secondary layers is TiO₂ and TiO_2-x, respectively. TiO₂ is a semiconductor with an approximately 3.2 eV bandgap. It is also a weak ionic conductor. A thin film of TiO₂ creates the tunnel barrier, and the TiO_2-x forms an ideal source of oxygen vacancies to dope the TiO₂ and make it conductive.

Finally, the upper electrode in the passive variable resistance memory layer is fabricated on top of the secondary layer in a manner similar to which the lower electrode was created. This may be, for example, a top wire of a crossed-wire pair. The material of the upper electrode may be either metal or semiconductor material, preferably, platinum. If the memory cell is in a cross point array style, an etching process may be necessary to remove the deposited memory region material that is not under the top wires in order to isolate the memory cell. It is understood, however, that any other suitable material deposition and processing techniques may be used to fabricate memristors for the passive variable-resistive memory. It will also be recognized that any other suitable passive variable resistance technology may be employed as mentioned above or that the order of operation may be rearranged in any suitable manner.

It will be understood that PVRM is a term used to describe any memory technology that stores state in the form of resistance instead of charge. That is, PVRM technologies use the resistance of a cell to store the state of a bit, in contrast to charge-based memory technologies that use electric charge to store the state of a bit. PVRM is referred to as being passive due to the fact that it does not require any active semiconductor devices, such as transistors, to act as switches. These types of memory are said to be “non-volatile” due to the fact that they retain state information following a power loss or power cycle. Passive variable resistive memory is also known as resistive non-volatile random access memory (RNVRAM or RRAM).

Examples of PVRM include, but are not limited to, Ferroelectric RAM (FeRAM), Magnetoresistive RAM (MRAM), Memristors, PRAM, Phase Change Memory (PCM), and Spin-Torque Transfer MRAM (STT-MRAM). While any of these technologies may be suitable for use in the IC 102 disclosed herein, PCM, memristors, and STT-MRAM are discussed below in additional detail.

Phase change memory (PCM) is a PVRM technology that relies on the properties of a phase change material, generally chalcogenides, to store state. Writes are performed by injecting current into the storage device, thermally heating the phase change material. An abrupt shutoff of current causes the material to freeze in an amorphous state, which has high resistivity, whereas a slow, gradual reduction in current results in the formation of crystals in the material. The crystalline state has lower resistance than the amorphous state; thus a value of 1 or 0 corresponds to the resistivity of a cell. Varied current reduction slopes can produce in-between states, allowing for potential multi-level cells. A PCM storage element consists of a heating resistor and chalcogenide between electrodes, while a PCM cell is comprised of the storage element and an access transistor.

Memristors are commonly referred to as the “fourth circuit element,” the other three being the resistor, the capacitor, and the inductor. A memristor is essentially a two-terminal variable resistor, with resistance dependent upon the amount of charge that passed between the terminals. Thus, a memristor's resistance varies with the amount of current going through it, and that resistance is remembered even when the current flow is stopped.

Spin-Torque Transfer Magnetoresistive RAM (STT-MRAM) is a second-generation version of MRAM, the original of which was deemed “prototypical” by the International Technology Roadmap for Semiconductors (ITRS). MRAM stores information in the form of a magnetic tunnel junction (MTJ), which separates two ferromagnetic materials with a layer of thin insulating material. The storage value changes when one layer switches to align with or oppose the direction of its counterpart layer, which then affects the junction's resistance. Original MRAM required an adequate magnetic field in order to induce this change. This was both difficult and inefficient, resulting in impractically high write energy. STT-MRAM uses spin-polarized current to reverse polarity without needing an external magnetic field. Thus, the STT technique reduces write energy as well as eliminating the difficult aspect of producing reliable and adequately strengthen magnetic fields. However, STT-MRAM, like PCM, requires an access transistor and thus its cell size scaling depends on transistor scaling.

FIG. 4 illustrates an integrated circuit 400 that employs a memory circuit, in this example a flip-flop that includes a direct backup wherein the output Q is always backed up automatically by the memory state backup circuit 302. In this example, the restore switch 308 which is connected to the input of the active memory circuit, in this case master latch 214, is also connected to an output of the PVRM interface 306. The restore switch 308 is responsive to restore signal 320 to cause the backup data in the PVRM cell 304 to be passed to the input of the master latch 214. The save switch 307 is configured in a different manner from that in FIG. 3. In this example, the save switch 307 has an input 406 that receives the clock signal 212 to clock the output Q of the flip-flop, in this example, out of slave latch 220, into the PVRM cell automatically. The save switch 307 automatically selects output data from an active memory circuit in response to output data being stored in the active memory circuit via clock signal 212. As such, the memory circuit is always backed up and ready to be power gated. The restore operation is still required once power is resumed. Block diagram representation 408 represents a flip-flop requiring only a restore input that includes self activation backup operation.

FIG. 5 illustrates another example of an integrated circuit 500 employing an active memory circuit (an active master latch stage 214) and a passive variable resistance memory slave stage 302 coupled to an output of the active master latch 214 wherein the output is shown as 504. In this example, switch transistor 222 connects the active master latch stage and the passive variable resistance memory slave latch stage. As previously noted, the master latch is made of active CMOS devices or other active devices whereas the PVRM cell is made of a passive variable resistance construction. The PVRM interface 306 in this example is controlled by the switch transistor 222 such that when the output of the master latch is passed via the switch 222, the PVRM interface stores the logic level in the PVRM cell 304. The switch 222 is interposed between the active master latch stage 214 and the passive variable resistance memory slave latch stage 302. The PVRM slave latch stage includes a PVRM cell interface 306 coupled to the switch 222 as well as a PVRM cell 304 coupled to the PVRM cell interface as previously described. The PVRM slave stage stores data such as on the output 504 from the active master latch, in response to clocking of the switch 222 by clock signal. The PVRM slave latch stage 302 stores the data in a non-volatile manner. As such, a PVRM cell is incorporated into the latch structure itself such that the state is always written to the local non-volatile PVRM cell. Power can be removed and restored at any time.

Although simple flip-flops have been illustrated by way of example, the structures described herein may be applied to a wide variety of memory circuits such as register files that include registers and any other suitable memory circuits. By way of example, FIG. 6 illustrates a register 600 that may include a number of bits wherein each bit is stored in the PVRM cell array 604 which includes an array of bit cells of PVRM non-volatile structures. The PVRM interface 602 instead of simply passing a single bit may read and write a plurality of bits depending upon the size of the register 600. Depending on the size of the memory circuit, an array of rows and columns of PVRM cells may be used.

FIG. 6 illustrates a register that includes a plurality of active memory circuits that form the register as known in the art and also includes a plurality of passive variable resistance memory cells that form a cell array 604. The PVRM cell interface 602 controls reads and writes 606 to each of the PVRM cells to facilitate data backup from the plurality of active memory circuits in the register 608.

FIG. 7 illustrates a method for providing state backup in an integrated circuit such as the circuits described above. In block 700, the method includes latching data in an active memory circuit such as in master latch 214 via suitable clock signals. As shown in block 702, the method includes controlling a corresponding passive variable resistance cell 304 to backup the latch data (queue), in a non-volatile manner. As such, when power is removed from the PVRM cell, the cell maintains the value of the data. The method includes, as shown in block 704, powering off the active memory circuit such as master latch 214 and slave latch 220 if desired as well as inverters and any other suitable logic in the memory circuit. The method includes powering off the PVRM cell 304 via, for example, the PVRM interface via the PVRM memory control logic 310. When data is to be restored, the method includes powering on the active memory circuit, powering on the PVRM cell and restoring data in the active memory circuit using the backup data in the PVRM cell as shown in blocks 708, 710 and 712. It will be recognized that the ordering of the steps may be in any suitable order and that the order given above is merely an example.

The method may include controlling a corresponding passive variable resistance memory cell to backup the latch data by generating a backup signal to control reading of the data from the active memory circuit to be stored in the PVRM cell. Restoring data in the active memory circuit may include using the backup data in the PVRM cell by generating a restore signal to cause the backup data from the PVRM cell to be input to the active memory circuit such as performed by the circuit in FIG. 3.

The disclosed integrated circuit designs may be employed in any suitable apparatus including but not limited to, for example, printers, high definition televisions, handheld devices such as smart phones, tablets, portable devices such as laptops or any other suitable device. Such devices may include for example, a display that is operatively coupled to the integrated circuit where the integrated circuit may be, for example, a GPU, CPU or any other suitable integrated circuit that provides image data for output on the display. Such an apparatus may employ the integrated circuits as noted above including the active memory circuit and memory state backup circuits as described as well as one or more of the described configurations.

Also, integrated circuit design systems (e.g., work stations including, as known in the art, one or more processors, associated memory in communication via one or more buses or other suitable interconnect and other known peripherals) are known that create wafers with integrated circuits based on executable instructions stored on a computer readable medium such as but not limited to CDROM, RAM, other forms of ROM, hard drives, distributed memory, etc. The instructions may be represented by any suitable language such as but not limited to hardware descriptor language (HDL), Verilog or other suitable language. As such, the logic and circuits described herein may also be produced as integrated circuits by such systems using the computer readable medium with instructions stored therein. For example, an integrated circuit with the aforedescribed logic and structure may be created using such integrated circuit fabrication systems. In such a system, the computer readable medium stores instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to produce an integrated circuit. The integrated circuit includes at least one active memory circuit, and at least one memory state backup circuit, operatively coupled to the active memory circuit, including at least one passive variable resistance memory (PVRM) cell and at least one PVRM cell interface operatively coupled to the active memory circuit and to the PVRM cell and operative to back up data to the PVRM cell from the active memory circuit. The produced integrated circuit may also include the other structure and operation set forth above.

The above detailed description of the invention and the examples described therein have been presented for the purposes of illustration and description only and not by limitation. It is therefore contemplated that the present invention cover any and all modifications, variations or equivalents that fall within the spirit and scope of the basic underlying principles disclosed above and claimed herein.

Claims

1. An integrated circuit comprising: at least one active memory circuit; andat least one memory state backup circuit, operatively coupled to the active memory circuit, comprising: at least one passive variable resistance memory (PVRM) cell; andat least one PVRM cell interface operatively coupled to the active memory circuit and to the PVRM cell and operative to back up data to the PVRM cell from the active memory circuit.

2. The integrated circuit of claim 1 wherein the PVRM cell interface is operative to read the PVRM cell in response to a restore signal.

3. The integrated circuit of claim 1 comprising PVRM cell interface control logic operative to remove power to the PVRM cell after back up of the data to the PVRM cell.

4. The integrated circuit of claim 2 comprising a restore switch, operatively coupled to an input of the active memory circuit and to an output of the PVRM interface, that is responsive to a restore signal to cause the backup data to be input to the active memory circuit; and a save switch operatively coupled to an output of the active memory circuit and to an input of the PVRM interface, that is responsive to a back up signal to pass data from the active memory circuit to be stored in the PVRM cell.

5. The integrated circuit of claim 2 comprising: a restore switch, operatively coupled to an input of the active memory circuit and to an output of the PVRM interface, that is responsive to a restore signal to cause the backup data to be input to the active memory circuit; anda save switch, operatively coupled to an output of the active memory circuit and to an input of the PVRM interface, that is operative to automatically select output data from the active memory circuit in response to output data being stored by the active memory circuit.

6. The integrated circuit of claim 4 wherein the active memory circuit comprises a flip flop comprised of a master latch serially connected to a slave latch and wherein the output of the active memory circuit is an output of the slave latch and wherein the input of the active memory circuit is an input of the master latch.

7. An integrated circuit comprising: an active memory circuit comprising an active master latch stage and a passive variable resistance memory (PVRM) slave latch stage operatively coupled to an output of the active master latch stage.

8. The integrated circuit of claim 7 comprising a switch interposed between the active master latch stage and a passive variable resistance memory (PVRM) slave latch stage, and wherein the PVRM slave latch stage comprises a PVRM cell interface coupled to the switch and a PVRM cell coupled to the PVRM cell interface, such that the PVRM slave stage stores data output from the active master latch in response to clocking of the switch and wherein the PVRM stage stores data in a non-volatile manner.

9. The integrated circuit of claim 8 comprising a clock circuit operatively coupled to an input of the switch to provide the clocking of the switch for the PVRM slave stage.

10. The integrated circuit of claim 1 comprising a plurality of active memory circuits and a plurality of passive variable resistance memory (PVRM) cells that form a PVRM cell array, and wherein the PVRM cell interface is operative to control reads and writes to each of the PVRM cells to facilitate data backup from the plurality of active memory circuits.

11. A method for providing state backup in an integrated circuit comprising: latching data in a active memory circuit;controlling a corresponding passive variable resistance memory (PVRM) cell to backup the latched data in a non-volatile manner;powering off the active memory circuit;powering off the PVRM cell;powering on the active memory circuit;powering on the PVRM cell; andrestoring data in the active memory circuit using the backup data in the PVRM cell.

12. The method of claim 11 wherein controlling a corresponding passive variable resistance memory (PVRM) cell to backup the latched data in a non-volatile manner comprises: generating a save signal to control reading of data from the active memory circuit to be stored in the PVRM cell; and whereinrestoring data in the active memory circuit using the backup data in the PVRM cell comprises generating a restore signal to cause the backup data from the PVRM cell to be input to the active memory circuit.

13. An apparatus comprising: a display; andan integrated circuit operative to provide data for output on the display comprising: at least one active memory circuit; andat least one memory state backup circuit, operatively coupled to the active memory circuit, comprising: at least one passive variable resistance memory (PVRM) cell; andat least one PVRM cell interface operatively coupled to the active memory circuit and to the PVRM cell and operative to back up data to the PVRM cell from the active memory circuit.

14. The apparatus of claim 13 wherein the PVRM cell interface is operative to read the PVRM cell in response to a restore signal.

15. The apparatus of claim 13 wherein the IC comprises PVRM cell interface control logic operative to remove power to the PVRM cell after back up of the data to the PVRM cell.

16. The apparatus of claim 14 wherein the IC comprises a restore switch, operatively coupled to an input of the active memory circuit and to an output of the PVRM interface, that is responsive to a restore signal to cause the backup data to be input to the active memory circuit; and a save switch operatively coupled to an output of the active memory circuit and to an input of the PVRM interface, that is responsive to a back up signal to pass data from the active memory circuit to be stored in the PVRM cell.

17. The apparatus of claim 14 wherein the IC comprises: a restore switch, operatively coupled to an input of the active memory circuit and to an output of the PVRM interface, that is responsive to a restore signal to cause the backup data to be input to the active memory circuit; anda save switch, operatively coupled to an output of the active memory circuit and to an input of the PVRM interface, that is operative to automatically select output data from the active memory circuit in response to output data being stored by the active memory circuit.

18. A non-transitory computer readable medium comprising executable instructions that when executed by an integrated circuit fabrication system, causes the integrated circuit fabrication system to produce an integrated circuit that comprises: at least one active memory circuit; andat least one memory state backup circuit, operatively coupled to the active memory circuit, comprising: at least one passive variable resistance memory (PVRM) cell; andat least one PVRM cell interface operatively coupled to the active memory circuit and to the PVRM cell and operative to back up data to the PVRM cell from the active memory circuit.

19. The computer readable medium of claim 18 comprising executable instructions that when executed by the integrated circuit fabrication system, causes the integrated circuit fabrication system to produce an integrated circuit that produces the PVRM cell interface to be operative to read the PVRM cell in response to a restore signal.

20. The computer readable medium of claim 18 comprising executable instructions that when executed by an integrated circuit fabrication system, causes the integrated circuit fabrication system to produce an integrated circuit that comprises PVRM cell interface control logic operative to remove power to the PVRM cell after back up of the data to the PVRM cell.