Patent Application
20070284609
The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and
The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention.
Referring to
The memory cell array 102 includes rewritable non-volatile memory cells that are arranged along word lines and bit lines in a matrix fashion well-known to those skilled in the art. Each of the memory cells is a cell wherein the write function is performed through hot electron injection. In this embodiment, SONOS-type cells may be employed as the non-volatile memory cells. The state machine 104 controls the operation of each circuit in the device in response to each control signal.
In accordance with the present invention, the high-voltage generator 106 generates voltage signals having high voltage levels that are used within the semiconductor device for memory operations thereof by applying the high voltages to selected cells within the memory cell array 102 via the X-Decoder 114 and the Y-Decoder 120. The high voltage signals used within the semiconductor memory device include voltage signals with a high voltage level for writing data, a high voltage level for erasing data, a high voltage level for reading data, and a verifying high voltage level for checking whether sufficient write/erase has been performed on a subject memory cell at the time of writing or erasing data.
The command register 108 temporarily stores operation commands that are input through the global buffer 112. The address register and decoder 110 temporarily stores input address signals. The I/O buffer and latch circuit 122 controls various signals or data corresponding to I/O terminals. The input/output driver 124 controls the data to be output from the semiconductor memory device 100 and the data to be input thereto.
Referring to
Referring to
Referring to
A plurality of clock signals are provided to the multiplexer 404. The plurality of clock signals are generated by a base clock signal from the clock 406 passing through the multiple clock signal dividers 408, such as frequency dividers, coupled in series. The plurality of signals are tapped from the output of the clock 406 and the clock signal dividers 408. Therefore, depending on the high voltage level detected by the multi-level detector 402, different ones of the plurality of clock signals are selected to control the operation frequency of the drain pump 200. In this manner, lower frequency clock signals could be selected to achieve high voltage generator 106 current savings, thereby providing a method for power conservation in the semiconductor 100.
Efficient operation of the high voltage generator 106 provides both power conservation and reliable operation. Referring to
To achieve high and almost constant efficiency, the high voltage generator 106 includes a voltage level detector 502 coupled to the output of a drain pump 200 for detecting a high voltage level of the voltage signals generated by the drain pump 200 and generating a voltage control signal in response thereto. The voltage level detector 502 is coupled to a controller 504 which includes a clock oscillator circuit 506 for providing an operation frequency control signal to the drain pump 200. In addition, a large capacitor 508 is coupled between ground and the voltage signals having a high voltage level to provide output current when the drain pump 200 is disabled.
Referring to
If the voltage control signal indicates the detected high voltage level is lower than the first predetermined voltage level 602, the drain pump 200 is enabled 606 by turning on the clock oscillator circuit 506. Conversely, if the voltage control signal indicates the detected high voltage level is higher than the second predetermined voltage level 602, the drain pump 200 is disabled 608 by turning off the clock oscillator circuit 506. Operation then returns to detect the next change in the high voltage level.
While operation in accordance with the third embodiment of the present invention provides relatively constant output voltage to achieve high efficiency, combination of the operation of the third embodiment with the power conservation techniques of the first or second embodiment of the present invention will result in additional power savings and improved operational efficiency of the semiconductor device 100.
While at least one exemplary embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. For example, the description above describes a semiconductor memory device embodiment of the present invention. However, the present invention is not limited to this embodiment and the high voltage generator 106 could be implemented in any semiconductor device to provide the benefits and advantages of the present invention for the operation thereof. It should also be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the claims. Accordingly, the scope of the present invention is only limited by the claims hereinbelow and their equivalents.
