Patent Grant
7333075
1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly to a driving method and apparatus for a plasma display panel that can be driven stably under a high temperature environment.
2. Description of the Related Art
A plasma display panel PDP displays a picture by having an ultraviolet ray make light emitted from a phosphorus material, the ultraviolet ray is generated when inert mixture gas is discharged. The PDP has its picture quality improved in debt to recent technology development as well as being easy to be made thin in thickness and big in size.
Referring to
There are lower dielectric layer 22 and barrier ribs 24 formed on the lower substrate 18 where the address electrode 20X is formed. There is a fluorescent layer 26 spread on the lower dielectric layer 22 and surface of the barrier ribs 24.
There is inert gas such as He+Xe, Ne+Xe and He+Xe+Ne etc. interposed in a discharge space provided between the upper/lower substrates 10 and 18 and the barrier ribs 24.
In order to realize the gray level of a picture, the PDP is time-division driven by dividing one frame into several sub-fields that have their light emission frequencies different. Each sub field can be divided into an initialization period (or a reset period) to initialize a full screen, an address period to select scan lines and select cells among the selected scan lines, and a sustain period to realize gray levels in accordance with a discharge frequency. The initialization period is again divided into a setup period for which a rising ramp waveform is applied and a set-down period for which a falling ramp waveform is applied. For example, in the event of displaying a picture with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second as in
Each of the 8 sub-fields (SF1 to SF8), as described above, is divided into the initialization period, the address period and the sustain period. The initialization period and the address period of each sub-field are the same for each sub-field, while the sustain period increases at the rate of 2n (n=0,1,2,3,4,5,6,7) in each sub-field.
In
Referring to
In the initialization period, a rising ramp waveform Ramp-up is simultaneously applied to all scan electrodes Y for a setup period SU. The rising ramp waveform Ramp-up causes a discharge to occur within the cells of the full screen. The setup discharge causes positive wall charges to be accumulated in the address electrode X and the sustain electrode Z, and negative wall charges to be accumulated in the scan electrode Y. A falling ramp waveform Ramp-down is simultaneously applied to the scan electrodes Y for the set-down period after the rising ramp waveform Ramp-up being applied. Herein, the falling ramp waveform begins to fall at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up.
The falling ramp waveform Ramp-down causes a weak erasure discharge within the cells so as to eliminate the wall charges formed excessively. The wall charges are uniformly sustained within the cells so that an address discharge can be stably caused by the set-down discharge.
In the address period, negative scan pulses SCAN are sequentially applied to the scan electrodes Y and at the same time positive data pulses DATA synchronized with the scan pulses SCAN are applied to the address electrodes X. When the voltage difference between the scan pulse SCAN and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied. When sustain voltages are applied, wall charges are formed within the cells selected by the address discharge so that the discharge can be caused.
Positive DC voltage Zdc is applied to the sustain electrode Z for the set-down period and the address period. The DC voltage Zdc sets the voltage difference between the sustain electrode Z and the scan electrode Y or the sustain electrode Z and the address electrode X so as to cause the set-down discharge to occur between the sustain electrode Z and the scan electrode Y for the set-down period, and at the same time so as not to cause a discharge to be generated on a large scale between the scan electrode Y and the sustain electrode Z for the address period.
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge, i.e., display discharge, between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS.
Lastly, after completion of the sustain discharge, a ramp waveform ERASE with narrow pulse width and low voltage level is applied to the sustain electrode Z, thereby to erase the wall charges remaining behind within the cells of the full screen.
However, the prior art PDP has a problem that the driving is not stable, i.e., there is no discharge generated in the event that it is made to run in a high temperature environment. For instance, in a high temperature environment of 50° C. or more, when the PDP, as in
Upon the high temperature environment experiment and the analysis result thereof, the principal cause for the occurrence of mis-discharge under the high temperature environment is the scanning order, as it gets later, the amount of loss of the wall charges generated in the initialization period is increased. To describe this cause on the basis of the discharge characteristic within the cell, firstly, as the internal/external temperature of the cell increases, the insulation characteristic of a dielectric material and a passivation material within the cell is deteriorated to generate leakage current, thereby leaking the wall charges. More specifically, in the event that the wall charges of the scan electrode Y and the sustain electrode Z is made to leak, it is easy for the address discharge to be mis-discharged. Secondly, as the movement of the space charge within the cell generated by the discharge in the high temperature environment gets active, the space discharge is easily recombined with the atom that has lost electrons so that the wall charges and space charges contributing to the discharge are lost as time passes by.
Accordingly, it is an object of the present invention to provide a driving method and apparatus for a plasma display panel that can be driven stably under a high temperature environment.
In order to achieve these and other objects of the invention, a method for driving a plasma display panel according to an aspect of the present invention, wherein the plasma display panel includes a plurality of scan electrodes, a plurality of sustain electrodes and a plurality of address electrodes, the method includes steps of increasing a voltage, which is applied to at least one of the scan electrode and the sustain electrode, in accordance with their scanning order; and selecting a cell by applying data to the address electrode.
Herein, the voltage applied to at least one of the scan electrode and the sustain electrode increases as the scanning order gets later.
Herein, the high temperature is 50° C. or more.
In the step of increasing the voltage, the voltage applied to the sustain electrode is increased linearly as the scanning order gets later.
The method further includes a step of continuously applying a rising ramp waveform and a falling ramp waveform to the scan electrode to initialize the cells of a full screen.
Herein, the falling ramp waveform falls down to a designated negative voltage.
The step of increasing the voltage further includes steps of applying a designated positive voltage to the sustain electrode while the falling ramp waveform is applied to the scan electrode; and applying to the sustain electrode a voltage that rises linearly from a lower voltage level than the positive voltage.
In the step of increasing the voltage, a second positive voltage higher than the positive voltage is applied to the sustain electrode that comes late in scanning order after applying a designated positive voltage to the sustain electrode that comes early in scanning order.
The step of increasing the voltage further includes steps of applying a designated positive voltage to the sustain electrode while the falling ramp waveform is applied to the scan electrode; and applying a third positive voltage lower than the positive voltage to the sustain electrode that comes early in scanning order, and then applying a fourth positive voltage higher than the third positive voltage to the sustain electrode that comes late in scanning order.
An apparatus for driving a plasma display panel under a high temperature environment according to the another aspect of the present invention, wherein the plasma display panel includes a plurality of scan electrodes, a plurality of sustain electrodes and a plurality of address electrodes, the apparatus includes a scan driver for applying a scan voltage to the scan electrode; a sustain driver for applying a voltage to the sustain electrode, the voltage is increased in accordance with a scanning order; and a data driver for applying data to the address electrode to select a cell.
Herein, the sustain driver increases the voltage applied to the sustain electrode as the scanning order gets later.
Herein, the high temperature is 50° C. or more.
Herein, the sustain driver increases the voltage applied to the sustain electrode linearly as the scanning order gets later.
Herein, the scan driver initialize the cells of a full screen by continuously applying a rising ramp waveform and a falling ramp waveform to the scan electrode.
Herein, the scan driver makes the falling rams waveform fall down to a designated negative voltage.
Herein, the sustain driver applies a designated positive voltage to the sustain electrode while the falling ramp waveform is applied to the scan electrode, and applies to the sustain electrode a voltage that rises linearly from a lower voltage level than the positive voltage.
Herein, the sustain driver applies a second positive voltage higher than the positive voltage to the sustain electrode that comes late in scanning order after applying a designated positive voltage to the sustain electrode that comes early in scanning order.
Herein, the sustain driver applies a designated positive voltage to the sustain electrode while the falling ramp waveform is applied to the scan electrode, and applies a fourth positive voltage higher than the third positive voltage to the sustain electrode that comes late in scanning order after applying a third positive voltage lower than the positive voltage to the sustain electrode that comes early in scanning order.
An apparatus for driving a plasma display panel under a high temperature environment according to still another aspect of the present invention, wherein the plasma display panel includes a plurality of scan electrodes, a plurality of sustain electrodes and a plurality of address electrodes, the apparatus includes a scan driver for applying a scan voltage to the scan electrode, the scan voltage is increased in accordance with a scanning order; a sustain driver for applying a voltage to the sustain electrode, the voltage is increased in accordance with a scanning order; and a data driver for applying data to the address electrode to select a cell.
Herein, the scan driver increases the scan voltage as the scanning order gets later.
These and other objects of the invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which:
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
Referring to
The data driver 62 latches data by one line portion under the control of the timing controller 60 and applies the latched data to the data lines Xl to Xm simultaneously, wherein the data are mapped to each of sub fields by a sub field mapping unit (not shown) after being reverse-gamma corrected and error-diffused by a reverse gamma correction circuit and an error diffusion circuit (not shown) etc.
The scan driver 64 applies a rising ramp waveform and a falling ramp waveform to the scan electrodes Yl to Yn in an initialization period, and then sequentially applies to the scan electrodes Yl to Yn a scan pulse for selecting the scan lines in the address period. Herein, as the scanning order of the scan pulse comes later under a high temperature environment of 50° C. or more, the scan pulse has its voltage level go higher linearly or non-linearly, or heighten step by step in multi-steps. This is for making an address discharge generated stably even when the wall charges are excessively lost at the line where the scanning order is late under the high temperature environment by having a scan voltage at the line where the scanning order is late set higher than a scan voltage at the line where the scanning order is early. And the scanning driver 64 applies to the sustain electrodes Yl to Yn the sustain pulse simultaneously for generating the sustain discharge with respect to the cells selected during the address period.
The sustain driver 66 applies a DC voltage in the set-down period, and then applies a high-temperature compensation voltage during the address period under a high temperature environment of 50° C. or more, wherein the high-temperature compensation voltage has its voltage level increase as the line is later in the scanning order. Herein, the voltage level of the high-temperature compensation voltage can be increased linearly or non-linearly, or can be increased step by step.
The timing controller 60 receives vertical/horizontal synchronization signals, generates timing control signals necessary for each of the drivers 62, 64 and 66, and applies the timing control signals to each of the drivers 62, 64 and 66.
The driving waveform generated from each of the drivers 62, 64 and 66 may be implemented in various forms as in
Referring to
In the initialization period, a rising ramp waveform Ramp-up that rises up to a peak voltage higher than a sustain voltage is simultaneously applied to all scan electrodes Y for a setup period SU. The rising ramp waveform Ramp-up causes a discharge to occur within the cells of the full screen. As a result, positive wall charges are accumulated in the address electrode X and the sustain electrode Z, and negative wall charges is accumulated in the scan electrode Y. A falling ramp waveform Ramp-down that falls down to a ground voltage GND is simultaneously applied to the scan electrodes Y for the set-down period to eliminate the wall charges formed excessively within the cells. The wall charges are uniformly sustained within the cells so that an address discharge can be stably caused by the set-down discharge.
During the set-down period SD, the sustain electrode Z is supplied with a positive DC voltage Zdc so that an erasure discharge can be generated between the sustain electrode Z and the scan electrode Y.
In the address period, negative scan pulses SCAN are sequentially applied to the scan electrodes Y and at the same time positive data pulses DATA synchronized with the scan pulses SCAN are applied to the address electrodes X. The scan pulses SCAN and the data pulses DATA each have the same voltage level in all the lines. When the voltage difference between the scan pulse SCAN and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied.
During such an address period, the sustain electrode Z is supplied with the high-temperature compensation voltage LHTC, the voltage level of which is increased linearly in proportion to the scanning order. The high-temperature compensation voltage LHTC increases the voltage of the sustain electrode Z at the line where wall charges and space charges are excessively lost, i.e., the line where its scanning order is late, to increase the amount of positive wall charges which are accumulated in the scan electrode Y and of negative wall charges accumulated in the sustain electrode Z. If the sustain voltage is applied even to the line with late scanning order by the high-temperature compensation voltage LHTC, the wall charges that can cause a discharge are formed within the cell.
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge, i.e., display discharge, between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. More specifically, in the prior art, because of low wall voltages due to the wall charges excessively lost at the line where its scanning order is late, the discharge is not generated even though the sustain voltage is applied to the cell, however, the driving method and apparatus of the PDP according to the embodiment of the present invention increases the wall voltages sufficiently enough at the line having late scanning order in use of the high-temperature compensation voltage, thus the sustain discharge can be generated stably even at the line having late scanning order. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z removes the wall charges generated upon the sustain discharge.
Referring to
During the set-down period SD, the sustain electrode Z is supplied with a positive DC voltage Zdc so that an erasure discharge can be generated between the sustain electrode Z and the scan electrode Y.
In the address period, negative scan pulses SCAN are sequentially applied to the scan electrodes Y and at the same time positive data pulses DATA synchronized with the scan pulses SCAN are applied to the address electrodes X. The scan pulses SCAN and the data pulses DATA each have the same voltage level in all the lines. When the voltage difference between the scan pulse SCAN and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied.
During the address period, the sustain electrode Z is supplied with the high-temperature compensation voltage LHTC, which rises from a voltage level lower than the positive DC voltage Zdc applied during the set-down period in view of the voltage level of the scan electrode Y that dropped to a designated negative potential in the set-down period. In other words, the start voltage of the high temperature compensation voltage LHTC is lower than the DC voltage Zdc of the set-down period SD by Vza. The reason why the high-temperature compensation voltage LHTC rises from the voltage level lower than the positive DC voltage Zdc is that the negative wall voltages in the scan electrode Y gets lower than the falling ramp waveform Ramp-down which falls down to the ground voltage because the falling ramp waveform Ramp-down drops down to the designated negative voltage level in the set-down period SD. That is, for the high-temperature compensation voltage LHTC to rise from the voltage level lower than the positive DC voltage Zdc is to prevent a mis-discharge between the scan electrode Y and the sustain electrode Z by lowering the voltage in the sustain electrode Z as much as the wall voltage in the scan electrode Y is decreased.
The high-temperature compensation voltage LHTC having its voltage level rise linearly in proportion to the scanning order increases the voltage of the sustain electrode Z at the line where its scanning order is late, to increase the amount of positive wall charges which are accumulated in the scan electrode Y and of negative wall charges accumulated in the sustain electrode Z. If the sustain voltage is applied even to the line with late scanning order by the high-temperature compensation voltage LHTC, the wall charges that can cause a discharge are formed within the cell.
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS.
In the address period, because of the high temperature compensation voltage LHTC applied to the sustain electrode Z, the wall charges are increased sufficiently at the line having late scanning order, thus the sustain discharge can be generated stably even at the line having late scanning order. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z removes the wall charges generated upon the sustain discharge.
In
Referring to
In the address period, negative scan pulses SCAN are sequentially applied to the scan electrodes Y and at the same time positive data pulses DATA synchronized with the scan pulses SCAN are applied to the address electrodes X. When the voltage difference between the scan pulse SCAN and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied.
After being supplied with the positive DC voltage Zdc during the set-down period SD and the first half of the address period, the sustain voltage Z is supplied with a second positive DC voltage 2Zdc higher than the positive DC voltage Zdc during the second half of the address period The second positive DC voltage 2Zdc increases the voltage of the sustain electrode Z at the line where its scanning order is relatively late, so as to increase the amount of the positive wall charges accumulated in the scan electrode Y and the negative wall charges accumulated in the sustain electrode Z. The wall voltages that can cause a discharge are formed within the cell if the sustain voltage is applied even at the line scanned in the second half by the second positive DC voltage 2Zdc.
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. Because of the second positive DC voltage 2Zdc, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
Referring to
In the address period, negative scan pulses SCAN are sequentially applied to the scan electrodes Y and at the same time positive data pulses DATA synchronized with the scan pulses SCAN are applied to the address electrodes X. When the voltage difference between the scan pulse SCAN and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied.
The sustain electrode Z is supplied with the positive DC voltage Zdc during the set-down period SD. And after the sustain voltage Z is supplied with a third positive DC voltage 3Zdc lower than the positive DC voltage Zdc during the first half of the address period, a fourth positive DC voltage 4Zdc equal to or higher than the positive DC voltage Zdc is applied during the second half of the address period. The reason why the third and fourth positive DC voltage 3Zdc, 4Zdc are lower than that of the third embodiment of the present invention is that a mis-discharge between the scan electrode Y and the sustain electrode Z is to be prevented by lowering the voltage in the sustain electrode Z as much as the wall voltage in the scan electrode Y is reduced more because or the falling ramp waveform Ramp-down that falls down to the negative voltage level. The fourth positive DC voltage 4Zdc increases the voltage in the sustain electrode Z at the lines where their scanning order are relatively late, thereby increasing the amount of positive wall charges accumulated in the scan electrode Y and of negative wall charges accumulated in the sustain electrode Z. This fourth positive DC voltage 4Zdc causes the wall charges to be formed within the cell even at the lines that are scanned in the second half of the address period, wherein the wall charges are capable of generating the discharge when the sustain voltage is applied.
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. Because of the fourth positive DC voltage 4Zdc, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
In
Referring to
In the address period, scan pulses VSCAN are sequentially applied to the scan electrodes Y, wherein the scan pulses VSCAN has a higher voltage level in a negative direction as their scanning order gets later. Positive data pulses DATA synchronized with the scan pulses VSCAN are applied to the address electrodes X. When the voltage difference between the scan pulse VSCAN and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied. The scan pulses VSCAN has its voltage level increase linearly in a negative direction in proportion to the scanning order to increase the voltage in the scan electrode Y at the line where its scanning order is late, thereby increasing the amount of positive wall charges accumulated in the scan electrode Y and of negative wall charges accumulated in the sustain electrode Z. This scan pulse VSCAN causes the wall voltages to be formed within the cell even at the line where its scanning order is late, wherein the wall voltages are capable of generating the discharge when the sustain voltage is applied.
The sustain electrode Z is supplied with the positive DC voltage Zdc during the set-down period and the address period. The DC voltage Zdc sets the voltage difference between the sustain electrode Z and the scan electrode Y or the sustain electrode Z and the address electrode X so as to cause a set-down discharge to occur between the sustain electrode Z and the scan electrode Y for the set-down period, and at the same time so as not to cause a discharge to be generated on a large scale between the scan electrode Y and the sustain electrode Z for the address period.
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. During the address period, because of the scan pulse VSCAN applied to the scan electrode Y, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
Referring to
In the address period, scan pulses VSCAN are sequentially applied to the scan electrodes Y, wherein the scan pulses VSCAN has a higher voltage level in a negative direction as their scanning order gets later. Positive data pulses DATA synchronized with the scan pulses VSCAN are applied to the address electrodes X. When the voltage difference between the scan pulse VSCAN and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied. During the address period, the sustain electrode Z is supplied with a high-temperature compensation voltage LHTC that has its voltage level increase linearly in proportion to the scanning order. The scan pulse VSCAN and the high-temperature compensation voltage LHTC increase the voltage of the sustain electrode Z at the line where its scanning order is late, thereby increasing the amount of the positive wall charges accumulated in the scan electrode Y and of the negative wall charges accumulated in the sustain electrode Z. The scan pulse VSCAN and the high-temperature compensation voltage LHTC cause the wall voltages to be formed within the cell even at the line where its scanning order is late, wherein the wall voltages are capable of generating the discharge when the sustain voltage is applied. In each of the scan pulse VSCAN and the high-temperature compensation voltage LHTC, because both the scan pulse VSCAN and the high-temperature compensation voltage LHTC have their voltage level increase in proportion to the scanning order, the difference between the minimum voltage and the maximum voltage is smaller than that in the scan pulse VSCAN and the high-temperature compensation voltage LHTC shown in
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. During the address period, because of the scan pulse VSCAN and the high-temperature compensation voltage LHTC applied to the scan electrode Y and the sustain electrode Z respectively, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
Referring to
During the set-down period SD, the sustain electrode Z is supplied with a positive DC voltage Zdc so that an erasure discharge can be generated between the sustain electrode Z and the scan electrode Y.
In the address period, scan pulses VSCAN are sequentially applied to the scan electrodes Y, wherein the scan pulses VSCAN has a higher voltage level in a negative direction as their scanning order gets later. Positive data pulses DATA synchronized with the scan pulses VSCAN are applied to the address electrodes X. When the voltage difference between the scan pulse VSCAN and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied. During the address period, the sustain electrode Z is supplied with a high-temperature compensation voltage LHTC that rises from a voltage level lower than the positive DC voltage Zdc applied for the set-down period SD in consideration of the voltage level of the scan electrode Y, which has been dropped to a designated negative potential for the set-down period. The scan pulse VSCAN and the high-temperature compensation voltage LHTC increase the voltage of the sustain electrode Z at the line where its scanning order is late, thereby increasing the amount of the positive wall charges accumulated in the scan electrode Y and of the negative wall charges accumulated in the sustain electrode Z. The scan pulse VSCAN and the high-temperature compensation voltage LHTC cause the wall voltages to be formed within the cell even at the line where its scanning order is late, wherein the wall voltages are capable of generating the discharge when the sustain voltage is applied. In each of the scan pulse VSCAN and the high-temperature compensation voltage LHTC, because both the scan pulse VSCAN and the high-temperature compensation voltage LHTC have their voltage level increase in proportion to the scanning order, the difference between the minimum voltage and the maximum voltage is smaller than that in the scan pulse VSCAN and the high-temperature compensation voltage LHTC shown in
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. During the address period, because of the scan pulse VSCAN and the high-temperature compensation voltage LHTC applied to the scan electrode Y and the sustain electrode Z respectively, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
Referring to
In the address period, scan pulses VSCAN are sequentially applied to the scan electrodes Y, wherein the scan pulses VSCAN has a higher voltage level in a negative direction as their scanning order gets later. Positive data pulses DATA synchronized with the scan pulses VSCAN are applied to the address electrodes X. When the voltage difference between the scan pulse VSCAN and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied. After a positive DC voltage being applied during the set-down period SD and the first half of the address period, a second positive DC voltage 2Zdc higher than the positive DC voltage Zdc is applied during the second half of the address period. The scan pulse VSCAN and the second positive DC voltage 2Zdc increase the voltage of the sustain electrode Z at the line where its scanning order is relatively late, thereby increasing the amount of the positive wall charges accumulated in the scan electrode Y and of the negative wall charges accumulated in the sustain electrode Z. The scan pulse VSCAN and the second positive DC voltage 2Zdc cause the wall voltages to be formed within the cell even at the line that is scanned in the second half of the address period, wherein the wall voltages are capable of generating the discharge when the sustain voltage is applied. The difference between the minimum voltage and the maximum voltage in the scan pulse VSCAN and the difference between the positive DC voltage Zdc and the second positive DC voltage 2Zdc are smaller than that in the scan pulse VSCAN and the high-temperature compensation voltage LHTC shown in
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. During the address period, because of the scan pulse VSCAN and the second positive DC voltage 2Zdc applied to the scan electrode Y and the sustain electrode Z respectively, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
Referring to
In the address period, scan pulses VSCAN are sequentially applied to the scan electrodes Y, wherein the scan pulses VSCAN has a higher voltage level in a negative direction as their scanning order gets later. Positive data pulses DATA synchronized with the scan pulses VSCAN are applied to the address electrodes X. When the voltage difference between the scan pulse VSCAN and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied.
The sustain electrode Z is supplied with the positive DC voltage Zdc for the set-down period SD. And in the first half of the address period, the sustain electrode Z is supplied with a third positive DC voltage 3Zdc, which has a lower voltage level than the positive DC voltage Zdc, and then in the second half of the address period, supplied with a fourth positive DC voltage 4dc, which has a higher voltage level than the third positive DC voltage 3Zdc.
During the address period, the scan pulse VSCAN and the fourth positive DC voltage 4Zdc increase the voltage of the sustain electrode Z at the line where its scanning order is relatively late, thereby increasing the amount of the positive wall charges accumulated in the scan electrode Y and of the negative wall charges accumulated in the sustain electrode Z. The scan pulse VSCAN and the second positive DC voltage 2Zdc cause the wall voltages to be formed within the cell even at the line that is scanned in the second half of the address period, wherein the wall voltages are capable of generating the discharge when the sustain voltage is applied. The difference between the minimum voltage and the maximum voltage in the scan pulse VSCAN and the third and fourth positive DC voltages 3Zdc, 4Zdc are smaller than that in the scan pulse VSCAN and the third and Fourth positive DC voltages 3Zdc, 4Zdc shown in
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. During the address period, because of the scan pulse VSCAN and the fourth positive DC voltage 4Zdc applied to the scan electrode Y and the sustain electrode Z respectively, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
Referring to
In the first half of the address period, a first scan pulse SCAN1 of designated voltage level is sequentially applied to the scan electrodes Y, which come relatively earlier in scanning order. In the second half of the address period, a second scan pulse SCAN2 is sequentially applied to the scan electrodes Y, which come relatively later in scanning order, wherein the second scan pulse SCAN2 has a higher voltage level in a negative direction as compared with the first scan pulse SCAN1. For instance, assuming that the number of scan electrodes Y is ‘n’ as in
The sustain electrode Z is supplied with the positive DC voltage Zdc during the set-down period and the address period. The DC voltage Zdc sets the voltage difference between the sustain electrode Z and the scan electrode Y or the sustain electrode Z and the address electrode X so as to cause a set-down discharge to occur between the sustain electrode Z and the scan electrode Y for the set-down period, and at the same time so as not to cause a discharge to be generated on a large scale between the scan electrode Y and the sustain electrode Z For the address period.
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. During the address period, because of the second scan pulse SCAN2 applied to the scan electrode Y, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
In
Referring to
In the first half of the address period, a first scan pulse SCAN1 of designated voltage level is sequentially applied to the scan electrodes Y, which come relatively earlier in scanning order. In the second half of the address period, a second scan pulse SCAN2 is sequentially applied to the scan electrodes Y, which come relatively later in scanning order, wherein the second scan pulse SCAN2 has a higher voltage level in a negative direction as compared with the first scan pulse SCAN1. Positive data pulses DATA synchronized with the scan pulses SCAN1, SCAN2 are applied to the address electrodes X. When the voltage difference between the scan pulses SCAN1, SCAN2 and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied. During the address period, the sustain electrode Z is supplied with a high-temperature compensation voltage LHTC, which has its voltage level increase linearly in proportion to the scanning order.
The second scan pulse SCAN2 and the high-temperature compensation voltage LHTC increase the voltage of the scan electrode Y and the sustain electrode Z at the line where its scanning order is late, thereby increasing the amount of the positive wall charges accumulated in the scan electrode Y and of the negative wall charges accumulated in the sustain electrode Z. The second scan pulse SCAN2 and the high-temperature compensation voltage LHTC cause the wall voltages to be formed within the cell even at the line where its scanning order is late, wherein the wall voltages are capable of generating the discharge when the sustain voltage is applied. The difference between the minimum voltage and the maximum voltage in the high-temperature compensation voltage LHTC and the voltage of the second scan pulse SCAN2 become smaller as compared with the high-temperature compensation voltage LHTC and the second scan pulse SCAN2 shown in
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. During the address period, because of the second scan pulse SCAN2 and the high-temperature compensation voltage LHTC applied to the scan electrode Y and the sustain electrode Z respectively, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
Referring to
During the set-down period SD, the sustain electrode Z is supplied with a positive DC voltage Zdc so that an erasure discharge can be generated between the sustain electrode Z and the scan electrode Y.
In the first half of the address period, a first scan pulse SCAN1 of designated voltage level is sequentially applied to the scan electrodes Y, which come relatively earlier in scanning order. In the second half of the address period, a second scan pulse SCAN2 is sequentially applied to the scan electrodes Y, which come relatively later in scanning order, wherein the second scan pulse SCAN2 has a higher voltage level in a negative direction as compared with the first scan pulse SCAN1. Positive data pulses DATA synchronized with the scan pulses SCAN1, SCAN2 are applied to the address electrodes X. When the voltage difference between the scan pulses SCAN1, SCAN2 and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied. During the address period, the sustain electrode Z is supplied with a high-temperature compensation voltage LHTC that rises from a voltage level lower than the positive DC voltage Zdc, wherein the positive DC voltage Zdc has been applied for the set-down period SD in consideration of the voltage level of the scan electrode Y that fell to the designated negative potential for the set-down period SD. The second scan pulse SCAN2 and the high-temperature compensation voltage LHTC increase the voltage of the scan electrode Y and the sustain electrode Z at the line where its scanning order is late, thereby increasing the amount of the positive wall charges accumulated in the scan electrode Y and of the negative wall charges accumulated in the sustain electrode Z. The second scan pulse SCAN2 and the high-temperature compensation voltage LHTC cause the wall voltages to be formed within the cell even at the line where its scanning order is late, wherein the wall voltages are capable of generating the discharge when the sustain voltage is applied. The difference between the minimum voltage and the maximum voltage in the high-temperature compensation voltage LHTC and the voltage of the second scan pulse SCAN2 become smaller as compared with the high-temperature compensation voltage LHTC and the second scan pulse SCAN2 shown in
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. During the address period, because of the second scan pulse SCAN2 and the high-temperature compensation voltage LHTC applied to the scan electrode Y and the sustain electrode Z respectively, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
Referring to
In the first half of the address period, a first scan pulse SCAN1 of designated voltage level is sequentially applied to the scan electrodes Y, which come relatively earlier in scanning order. In the second half of the address period, a second scan pulse SCAN2 is sequentially applied to the scan electrodes Y, which come relatively later in scanning order, wherein the second scan pulse SCAN2 has a higher voltage level in a negative direction as compared with the first scan pulse SCAN1. Positive data pulses DATA synchronized with the scan pulses SCAN1, SCAN2 are applied to the address electrodes X. When the voltage difference between the scan pulses SCAN1, SCAN2 and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied. During the set-down period SD and the first half of the address period, the sustain electrode Z is supplied with a positive DC voltage Zdc, and then during the second half of the address period, there is applied a second positive DC voltage 2Zdc higher than the positive DC voltage Zdc. The second scan pulse SCAN2 and the second DC voltage 2Zdc increase the voltage of the scan electrode Y and the sustain electrode Z at the lines where their scanning order is relatively late, thereby increasing the amount of the positive wall charges accumulated in the scan electrode Y and of the negative wall charges accumulated in the sustain electrode Z. The second scan pulse SCAN2 and the second positive DC voltage 2Zdc cause the wall voltages to be formed within the cell even at the lines where their scanning order is late, wherein the wall voltages are capable of generating the discharge when the sustain voltage is applied. The second positive DC voltage 2Zdc and the voltage of the second scan pulse SCAN2 become smaller as compared with the second positive DC voltage 2Zdc and the second scan pulse SCAN2 shown in
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. During the address period, because of the second scan pulse SCAN2 and the second positive DC voltage 2Zdc applied to the scan electrode Y and the sustain electrode Z respectively, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
Referring to
In the first half of the address period, a first scan pulse SCAN1 of designated voltage level is sequentially applied to the scan electrodes Y, which come relatively earlier in scanning order. In the second half of the address period, a second scan pulse SCAN2 is sequentially applied to the scan electrodes Y, which come relatively later in scanning order, wherein the second scan pulse SCAN2 has a higher voltage level in a negative direction as compared with the first scan pulse SCAN1. Positive data pulses DATA synchronized with the scan pulses SCAN1, SCAN2 are applied to the address electrodes X. When the voltage difference between the scan pulses SCAN1, SCAN2 and the data pulse DATA is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse DATA is applied.
During the set-down period SD, the sustain electrode Z is supplied with a positive DC voltage Zdc. And in the first half of the address period, the sustain electrode Z is supplied with a third positive DC voltage 3Zdc that has a lower voltage level than the positive DC voltage Zdc, and then supplied with a fourth positive DC voltage 4Zdc that has a higher voltage level than the third positive DC voltage 3Zdc in the second half of the address period.
During the address period, the second scan pulse SCAN2 and the fourth DC voltage 4Zdc increase the voltage of the scan electrode Y and the sustain electrode Z at the lines where their scanning order is relatively late, thereby increasing the amount of the positive wall charges accumulated in the scan electrode Y and of the negative wall charges accumulated in the sustain electrode Z. The second scan pulse SCAN2 and the second positive DC voltage 2Zdc cause the wall voltages to be formed within the cell even at the lines where their scanning order is late, wherein the wall voltages are capable of generating the discharge when the sustain voltage is applied. The second scan pulse SCAN2 and the third and fourth positive DC voltages 3Zdc, 4Zdc become smaller as compared with the second scan pulse SCAN2 and the third and fourth positive DC voltages 3Zdc, 4Zdc shown in
In the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, there occurs a sustain discharge between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied as the wall voltage within the cell is added to the sustain pulse SUS. During the address period, because of the second scan pulse SCAN2 and the third and fourth positive DC voltages 3Zdc, 4Zdc applied to the scan electrode Y and the sustain electrode Z respectively, the wall voltages are increased sufficiently at the line where its scanning order is late, thus the sustain discharge is generated stably even at the line where the scanning order is late. After the completion of the sustain discharge, a small ramp waveform ERASE applied to the sustain electrode Z eliminates the wall charges generated upon the sustain discharge.
On the other hand, the foregoing embodiments increase the voltage of the scan electrode Y and the common sustain electrode Z as their scanning order gets later, so as to compensate the mis-discharge caused under the high temperature environment, however it is possible to obtain the same effect by increasing a data voltage or the voltage of the scan electrode and/or the voltage of the sustain electrode together with the data voltage as their scanning order gets later.
As described above, the driving method and apparatus of the PDP according to the present invention, during the address period, can drive the PDP stably under the high temperature environment because the mis-discharge, which occurs under the high temperature environment at the lines where their scanning order is late, can be prevented by increasing the voltage of the scan electrode or the voltage of the sustain electrode as their scanning order gets later.
Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2002-0012001 | Mar 2002 | KR | national |
| Number | Name | Date | Kind |
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| 6492776 | Rutherford | Dec 2002 | B2 |
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| Number | Date | Country |
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| 11065516 | Mar 1999 | JP |
| 11-242460 | Sep 1999 | JP |
| 20000034676 | Jun 2000 | KR |
| 2000-0053573 | Aug 2000 | KR |
| Number | Date | Country | |
|---|---|---|---|
| 20030169216 A1 | Sep 2003 | US |
