Patent Grant
RE41216
The present invention relates to a display driving device for driving a display element such as a liquid crystal, a display device including the display element driving device, an information processing apparatus including the display device, and a display element driving method.
However, since an output voltage is generated by interpolating the voltages V1 to V9 in the above method, the resultant output voltage is different from a voltage to be displayed in an original state, and display characteristics are degraded disadvantageously.
On the other hand,
However, the analog-type data driver 942 has high power consumption because an analog circuit must be incorporated in the data driver 942, and the data driver 942 is generally improper for a display of a portable computer.
In recent years, it is tried to integrally form the data driver 942 or the like on a substrate having a TFT (thin-film transistor) 944. When the TFT 944 is integrally formed, a considerable reduction in size of the liquid-crystal display device and a reduction in cost can be realized. When such integral formation is to be performed, an incorporated analog circuit must be also constituted by a TFT in the analog-type data driver. 942. However, when the analog circuit is constituted by a TFT, the following various problems are posed. That is, the transistor characteristics of the TFT change with time, or it is difficult to obtain desired performance. In addition, when it is tried to incorporate the γ-correction circuit 934 in the data driver 942, a large amount of current flows in the γ-correction circuit 934 serving as an analog circuit. For this reason, a problem of a change in transistor characteristics of a TFT with time is posed.
As described above, the conventional data driver has various problems.
Some information processing apparatus such as a multi-media terminal or a graphic accelerator do not process an RGB signal used in a liquid-crystal display device, but process an image signal called a YUV or processes both RGB and YUV. When the liquid-crystal display device is used as a display of the information processing apparatus, it is desired that both the image signals, i.e., RGB and YUV, can be displayed. For this purpose, in a conventional arrangement, a conversion circuit 950 as shown in
However, in this arrangement, since an analog-type data driver must be used as the data driver 962, a problem about an increase in power consumption is also posed as described above. In addition, there is a problem of difficulty of the data driver 962 integrally formed on a substrate on which a TFT 964 is formed.
The present invention has been made to solve the above problems, and has as its object to provide a display element driving device, a display device, an information processing apparatus, and a display element driving method each of which can obtain a low power consumption, can be increased in scale, and exhibit high performance.
It is another object of the present invention to provide a display element driving device or the like which can compensate for the display characteristics of a display element with an arrangement having low power consumption and a small scale.
It is still another object of the present invention to provide a display element driving device or the like which can display image signals having different formats with an arrangement having a low power consumption and a small scale.
It is still another object of the present invention to provide a display element driving device or the like which is optimally integrated with a substrate on which a TFT and the like are formed.
In order to solve the above problems, according to the present invention, there is provided a display element driving device comprising a D/A converter for giving an applied voltage based on a given image signal to an electrode line electrically connected to the other side of a capacitive display element having one side to which a given voltage is applied.
The D/A converter includes first to Nth charge storage means for respectively receiving first to Nth digital data corresponding to the image signal and storing charges corresponding to the values of the first to Nth digital data first to Nth connection means for electrically connecting the first to Nth charge storage means and the electrode line to each other and discharging the charges stored in the first to Nth charge storage means to the electrode line at a given timing.
According to the present invention, for example, in case of N=2, a charge corresponding to the value of the first digital data and a charge corresponding to the value of the second digital data are stored in the first charge storage means and the second charge storage means. When the first and second connection means electrically connects the first and second charge storage means and the electrode line to each other, the charges stored in the first and second charge storage means are discharged to the electrode line. At this time, on the basis of the discharged charges, capacitances of, e.g., the display element, the electrode line, and the first and second charge storage means, and the like, an applied voltage to the electrode line is determined. According to the present invention, the moment D/A conversion is performed, processes such as addition and subtraction processes between the digital data are performed or the process multiplying the digital data by given coefficients can be performed.
The present invention is characterized in that the first to Nth charge storage means store the charges on the basis of the first to Nth digital data can be performed and at least one given voltage. In this manner, when various-given voltages are prepared, or a given voltage is changed, not only a simple addition process of digital data but also various processes such as a subtraction process, a multiplication process of a coefficient can be easily performed.
The present invention is characterized in that the first to Nth charge storage means include capacitor elements having one sides to which a given voltage is applied and capacitances which are binarily weighted, and the first to Nth connection means include switches for electrically connecting the other sides of the capacitive elements and the electrode line to each other at once. When the capacitances of the capacitor elements are binarily weighted at, e.g., 1:2:4:8 . . . , an addition process, a subtraction process, and the like of digital data can be easily performed.
The present invention is characterized in that the first to Nth charge storage means select at least one capacitor element for storing a charge from the capacitor elements on the basis of the first to Nth digital data, and store a charge in the selected capacitor element at at least one given voltage. For example, given voltages V1, VC, and −V1 (V1−VC=VC−(−V1)), the first charge storage means selects a capacitor element for storing a charge by V1 and VC on the basis of the first digital data, and the second charge storage means selects a capacitor element for storing a charge by −V1 and VC, thereby making it possible to perform a subtraction process or the like. When the given voltages to the first to Nth charge storage means are made different from each other, a display element driving device which has a small scale and is not adversely affected by a variation in manufacturing process can be realized.
The present invention is characterized in that digital data having the complementary format of 2 is output as the first to Nth digital data, and the capacitance of the capacitor element corresponding to an MSB of digital data of capacitor elements included in at least one of the first to Nth charge storage means is made equal to the capacitance of a capacitor element corresponding to an LSB. For example, when digital data to be added is negative, a charge is stored in a capacitor corresponding to the MSB (Most Significant Bit), so that a subtraction process or the like of digital data having the complementary format of 2 can be realized.
According to the present invention, there is provided a display element driving device comprising a D/A converter for giving an applied voltage based on a given image signal to an electrode line electrically connected to the other side of a capacitive display element having one side to which a given voltage is applied, characterized in that the D/A converter includes first charge storage means for receiving image digital data corresponding to the image signal and storing a charge corresponding to the value of the image digital data, second charge storage means for receiving correction digital data for compensating for the display characteristics of the display element and storing a charge corresponding to the value of the correction digital data, first correction means for electrically connecting the first charge storage means and the electrode line to each other and discharging the charge stored in the first charge storage means to the electrode line at a given timing, and second connection means for electrically connecting the second charge storage means and the electrode line to each other and discharging the charge stored in the charge storage means to the electrode line at the same timing as the given timing.
According to the present invention, D/A conversion of image digital data, a γ-correction process of a liquid crystal, and the like, can be simultaneously performed. In addition, the correction process can be accurately performed, and reductions in power consumption and reduction in scale of the device can also be performed.
The present invention is characterized in that when a change value of the applied voltage obtained when the LSB of the image digital data changes is represented by V1, and a change value of the applied voltage obtained when the LSB of the correction digital data changes is represented by V2, a relationship V1>2×V2 is established. In this manner, a state wherein an applied voltage decreases with respect to an increase in image digital data is prevented, and normal gradation expression can be performed.
The present invention is characterized in that when the number of bits of the image digital data is represented by m, and the number of bits of the correction digital data is represented by n, a relationship m≧n is established. In this manner, the display element driving device can be reduced in area while making normal gradation expression possible.
According to the present invention, there is provided a display element driving device for giving applied voltages VR1, VG1, and VB1 generated on the basis of digital data DY1, DU1, and DV1 of a YUV signal to electrode lines for red, green, and blue to which display elements are respectively electrically connected, characterized by comprising a first D/A converter for respectively receiving the digital data DY1 and DV1 and generating an applied voltage VR1 to the electrode line for red by conversion according to a relational expression VR1=aDY1+bDV1, a second D/A converter for respectively receiving the digital data DY1, DU1, and DV1 and generating an applied voltage VG1 to the electrode line for green by conversion according to a relational expression VG1=cDY1+dDU1+eDV1, and a third D/A converter for respectively receiving the digital data DY1 and DU1 and generating an applied voltage VB1 to the electrode for blue by conversion according to a relational expression VB1=fDY1+gDU1.
According to the present invention, D/A conversion, a conversion process from YUV to RGB, and the like can be simultaneously performed. In this manner, a display element driving device which is optimum for an information processing apparatus or the like using a YUV signal can be provided. According to the present invention, various types of YUV signals such as YUV422 or YUV411 signals can be converted into RGB signals.
The present invention is characterized by comprising a fourth D/A converter for respectively receiving digital data DY2 for generating VR2, VG2, and VB2 given to second electrode lines for red, green, and blue adjacent to the electrode lines for red, green, and blue and the digital data DV1 and generating an applied voltage VR2 to the second electrode line for red by conversion according to a relational expression VR2=aDY2+bDV1, a fifth D/A converter for respectively receiving the digital data DY2, DU1, and DV1 and generating an applied voltage VG2 to the second electrode line for green by conversion according to the relational expression VG2=cDY2+dDU1+eDV1, and a sixth D/A converter for respectively receiving the digital data DY2 and DU1 and generating an applied voltage VB2 to the second electrode line for blue by conversion according to a relational expression VB2=fDY2+gDU1. In this manner, a display element driving device having an arrangement which is optimum for conversion of a YUV signal, especially, in a YUV422 scheme can be provided.
The present invention is characterized in that the respective coefficients a, b, c, d, e, f, and g are determined by at least one given voltage and the capacitance of a capacitor element which is incorporated in the D/A converter and in which a charge is stored by the given voltage. As described above, when the D/A converters incorporate the capacitor elements, the coefficients a to g are preferably determined by the capacitances (e.g., total capacitance or capacitance corresponding to the LSB of digital data) of the capacitor elements and the given voltages.
The present invention is characterized in that the capacitances of the capacitor elements for determining the respective coefficients a, b, c, d, e f, and g are made equal to each other, and the voltages for determining the respective coefficients a, b, c, d, e, f, and g are made different from each other. For example, when capacitances Ca to Cg for determining the coefficients a to g are equally set to CEQ, and voltages Va to Vg for determining the coefficients a to g are made different from each other, the coefficients a to g can be set to values which are different from each other. When the coefficient ratio is not an integer, this method is preferable because the method which can make the capacitances Ca to Cg equal to each other is not easily adversely affected by variation in manufacturing process.
The present invention is characterized in that the voltages for determining the respective coefficients a, b, c, d, e, f, and g are made equal to each other, and the capacitances of the capacitor elements for determining the respective coefficients a, b, c, d, e, f, and g are made different from each other. For example, when the voltage Va to Vg for determining the coefficients a to g are equally set to VEQ, and the capacitances Ca to Cg for determining the coefficients a to g are made different from each other. The coefficients a to g can be set to values which are made different from each other.
The present invention is characterized in that the display element is a capacitive display element having one side to which a given voltage is applied; the first D/A converter includes first and second charge storage means for respectively receiving DY1 and DV1 and storing charges according to the values of the DY1 and DV1 and first and second connection means for electrically connecting. The first and second charge storage means and the electrode line for red to each other and discharging the charges stored in the first and second charge storage means to the electrode line for red at a given timing; the second D/A converter includes third, fourth, and fifth charge storage means for respectively receiving DY1, DU1, and DV1 and storing charges according to the values of the DY1, DU1, and DV1 and third, fourth, and fifth connection means for electrically connecting the third, fourth, and fifth charge storage means. The electrode line for green to each other and discharging the charges stored in the third, fourth, and fifth charge storage means to the electrode line for green at a given timing; and the third D/A converter includes sixth and seventh charge storage means for respectively receiving DY1 and DU1 and storing charges according the values of the DY1 and DU1 and sixth and seventh connection means for electrically connecting the sixth and seventh charge storage means and the electrode line for blue to each other and discharging the charges stored in the sixth and seventh charge storage means to the electrode line for blue at a given timing. When the first to seventh charge storage means and the first to seventh connection means are arranged as described above, D/A conversion and conversion from YUV to RGB can be realized at a low power consumption with a relatively simple arrangement.
The present invention is characterized in that the display element is a capacitive display element having one side to which a given voltage is applied; the first D/A converter includes first and second charge storage means for respectively receiving DY1 and DV1 and storing charges according to the values of the DY1 and DV1 and first and second connection means for electrically connecting. The first and second charge storage means and the electrode line for red to each other and discharging the charges stored in the first and second charge storage means to the electrode line for red at a given timing; the second D/A converter includes third, fourth, and fifth charge storage means for respectively receiving DY1, DU1, and DV1 and storing charges according to the values of the DY1, DU1, and DV1 and third, fourth, and fifth connection means for electrically connecting. The third, fourth, and fifth charge storage means and the electrode line for green to each other and discharging the charges stored in the third, fourth, and fifth charge storage means to the electrode line for green at a given timing; the third D/A converter includes sixth and seventh charge storage means for respectively receiving DY1 and DU1 and storing charges according the values of the DY1 and DU1 and sixth and seventh connection means for electrically connecting. The sixth and seventh charge storage means and the electrode line for blue to each other and discharging the charges stored in the sixth and seventh charge storage means to the electrode line for blue at a given timing; the fourth D/A converter includes eighth and ninth charge storage means for respectively receiving DY2 and DV1 and storing charges according to the values of the DY2 and DV1 and eighth and ninth connection means for electrically connecting. The eighth and ninth charge storage means to the second electrode line for red to each other and discharging the charges stored in the eighth and ninth charge storage means to the second electrode line for red at a given timing; the fifth D/A converter includes tenth, eleventh, and twelfth charge storage means for respectively receiving DY2, DU1, and DV1 and storing charges according to the values of the DY2, DU1, and DV1 and tenth, eleventh, and twelfth connection means for electrically connecting the tenth, eleventh, and twelfth charge storage means. The second electrode line for green to each other and discharging the charges stored in the tenth, eleventh, and twelfth to the second electrode line for green at a given timing; and the sixth D/A converter includes thirteenth and fourteenth charge storage means for respectively receiving DY2 and DU1 and storing charges according to the values of the DY2 and DU1 and thirteenth and fourteenth connection means for electrically connecting the thirteenth and fourteenth charge storage means and the second electrode line for blue to each other and discharging the charges stored in the thirteenth and fourteenth charge storage means to the electrode line for blue at a given timing. When the first to fourteenth charge storage means and the first to fourteenth connection means are arranged as described above, D/A conversion and conversion from YUV to RGB can be realized at a low power consumption with a relatively simple arrangement.
The present invention is characterized in that digital data DR1, DG1, and DB1 of a RGB signal are further given, and a YUV mode for generating applied voltages VR1, VG1, and VB1 on the basis of the digital data DY1, DU1, and DV1 and an RGB mode for generating the applied voltages VR1, VG1, and VB1 on the basis of the digital data DR1, DG1, and DB1 are set.
According to the present invention, not only conversion from YUV to RGB but also D/A conversion of RGB digital data can also be performed. In this manner, a display element driving device which is optimum for an information processing apparatus or the like in which both YUV and RGB are set can be provided.
The present invention is characterized by comprising means for, in the RGB mode, inputting DR1 to the first D/A converter in place of DY1 and DV1, inputting DG1 to the second D/A converter in place of DY1, DU1 and DV1, and inputting DB1 to the third D/A converter in place of DY1 and DU1. In this manner, both the conversion processes in the RGB mode and the YUV mode can be realized by the first to third D/A converters, hardware resources can be effectively used.
The present invention is characterized in that digital data DR1, DG1, DB1, DR2, DG2, and DB2 of an RGB signal are further given, and a YUV mode for generating applied voltages VR1, VG1, VB1, VR2, VG2, and VB2 on the basis of the digital data DY1, DU1, DV1, and DY2 and an RGB mode for generating applied voltages VR1, VG1, VB1, VR2, VG2, and VB2 on the basis of the digital data DR1, DG1, DB1, DR2, DG2, and DB2 are arranged. In this manner, a display element driving device which is optimum for an information processing apparatus or the like in which both YUV422 and RGB are set can be provided.
The present invention is characterized by comprising means for, in the RGB mode, inputting DR1 to the first D/A converter in place of DY1 and DV1, inputting DG1 to the second D/A converter in place of DY1, DU1 and DV1, inputting DB1 to the third D/A converter in place of DY1 and DU1, inputting DR2 to the fourth D/A converter in place of DY2 and DV1, inputting DG2 to the fifth D/A converter in place of DY2, DU1, and DV1, and inputting DB2 to the sixth D/A converter in place of DY2 and DU1. In this manner, especially in conversion of a YUV signal in a YUV422 scheme, hardware resources can be effectively used.
According to the present invention, there is provided a display element driving device for giving first and second applied voltages for red, blue, and green generated on the basis of digital data of a YUV signal to first and second electrode lines for red, green, and blue to which display elements are respectively electrically connected, characterized by comprising a first transfer line for sequentially transferring digital data DY1, DY2, DY3, DY4 . . . DY2K−1 DY2k . . . DYL of the YUV signal, a second transfer line for sequentially transferring digital data DV1, DU1, DV2, DU2 . . . DVK, DUK . . . DVL/2, DUL/2 or DU1, DV1, DU2, DV2 . . . DUK, DVK . . . DUL/2, DVL/2 of the YUV signal, a first latch for latching DY2k−1 of the first transfer line, a second latch for latching DVK or DUK of the second transfer line at a timing which is substantially the same as that of the first latch, a third latch for latching DUK or DVK of the second transfer line, a fourth latch for latching DY2K of the first transfer line at a timing which is substantially the same as that of the third latch, and first to sixth D/A converters for generating first and second applied voltages for red, green, and blue on the basis of DY2k−1, DVK, DUK, and DY2K latched by the first to fourth latches.
According to the present invention, data can be caused to flow in the first and second transfer lines without any loss, and data transfer to the first to sixth D/A converters without any loss. For this reason, power consumption and scale of the device can be reduced.
The display device according to the present invention is characterized by comprising one of the display element driving device described above and a display element driven by the display element driving device. The display device according to the present invention further includes a substrate on which a switching element consisting of a thin-film transistor or a thin-film non-linear element is formed, characterized in that the display element driving device is integrally formed on the substrate. When the display element driving device is integrally formed on the substrate as described above, the display device can be reduced in outside dimension and cost.
According to the present invention, there is provided a display device comprising a display element driving device, a display element driven by the display element driving device, and a substrate on which a switching element consisting of a thin-film transistor or a thin-film non-linear element is formed, characterized in that the display element driving device includes a D/A converter for receiving image digital data and correction digital data for compensating for the display characteristics of the display element and outputting an applied voltage subjected to a correction process, and the display element driving device is integrally formed on the substrate.
According to the present invention, since the display element driving device can be integrally formed on the substrate of the TFT, the device can be reduced in scale and cost. The circuit in the display element driving device can be entirely constituted by a digital-based circuit, and the design for the display element driving device can be simplified.
The invention processing apparatus according to the present invention is characterized by comprising any one of the display devices described above and at least one image signal output device for outputting an image signal given to the display device. The information processing apparatus according to the present invention comprises a display element driving device, a display device including a display element driven by the display element driving device, a first image signal output device for outputting digital data of a YUV signal, and a second image signal output device for outputting digital data of an RGB signal, and is characterized in that the display element driving device includes means for directly converting the digital data of the YUV signal into analog applied voltages for red, green, and blue to output the analog applied voltages when the digital data of the YUV signal is input, and converting the digital data of the RGB signal into analog applied voltages for red, green, and blue to output the analog applied voltages when the digital data of the RGB signal is input. In this manner, the display element driving device can be entirely constituted by a digital-based circuit, and an information processing apparatus in which both RGB and YUV are set can be reduced in power consumption and size.
The D/A converter 110 includes first to Nth charge storage sections 112-1 to 112-N and first to Nth connection sections 114-1 to 114-N. The first to Nth charge storage sections 112-1 to 112-N receive first to Nth digital data corresponding an image signal, and store charges corresponding to the values of the first to Nth digital data.
In this case, the first to Nth digital data may correspond to at least an image signal, and the first to Nth digital data are not necessarily digital data obtained by only converting the image signal. More specifically, the first to Nth digital data include various digital data such as digital data generated on the basis of, e.g., an image signal or digital data for correcting the image signal.
Amount of charge stored in the first to Nth charge storage sections 112-1 to 112-N may correspond to the values of at least the first to Nth digital data, and the amounts are not necessarily proportional to the values of the first to Nth digital data. For example, the amounts of stored charge may be determined on the basis of the first to Nth digital data and one given voltage or a plurality of given voltages. More specifically, the following various methods may be used: any one of the plurality of given voltages is selected on the basis of the first to Nth digital data, and charges are stored depending on the selected voltage; charges corresponding to multiplication values between the first to Nth digital data and a given voltage are stored; or the like.
The first to Nth connection sections 114-1 to 114-N electrically connect the first to Nth charge storage sections 112-1 to 112-N and the electrode line 130 to each other, and discharge charges stored in the first to Nth charge storage sections 112-1 to 112-N to the electrode line 130 at a given timing. At this time, the first to Nth charge storage sections 112-1 to 112-N desirably discharge the stored charges to the electrode line 130 at substantially the same timing. When the charges are discharged to the electrode line 130, an applied voltage on the electrode line 130 is determined on the basis of the charge amounts, the capacitance of CSO, the capacitances of the first to Nth charge storage sections 112-1 to 112-N, and the like. The applied voltage is given to the display element to drive the display element. The other D/A converters such as a D/A converter 120 have the same arrangements as that of the D/A converter 110 and generate applied voltages to other electrode lines such as an electrode line 132.
A case wherein (0101)2=5 is given by the first digital data and (0010)2=2 is given by the second digital data will be considered. Referring to
VS0=D1/D2 (1)
D1=(4Ca+Ca)×Va+2Cb×Vb
=5Ca×Va+2Cb×Vb
D2=(8Ca+4Ca+2Ca+Ca)+(Cb+4Cb+2Cb+Cb)+CS0 (2)
As is apparent from the above equations, since the denominator D2 is constant without depending on the first and second digital data, the magnitude of the VS0 depends on the numerator D1. More specifically, when the values of the first and second digital data, Ca, Cb, Va, and Vb are set to various values, respectively, VS0 having various values can be obtained. For example, when Ca=Cb and Va=Vb, D1=7Ca×Va is satisfied, and VS0 corresponding to the sum of values of the first and second digital data. According to this embodiment, D/A conversion and an addition process of the first and second digital data can be simultaneously performed.
A case wherein (0101)2=5 is given by the first digital data and (1110)2=−2 is given by the second digital data will be considered. In this case, digital data in the complementary format of 2 are input as the first and second digital data. Since the first digital data is (0101)2, CA2 and CA0 are selected as in the above description, Va is applied to the CA2 and CA0. On the other hand, since the second digital data (1110)2 is a negative number because bit 3 serving as the MSB (Most Significant Bit) is 1. Therefore, the difference between (1110)2 and (1111)2 is set, or (1110)2 is inverted to generate (0001)2. Bit 0 of the obtained digital data is 1, so that CB0 is selected. In addition, in this embodiment, CB3 having a capacitance equal to that of CB0 corresponding to bit 0 serving as the LSB (Least Significant Bit) is also selected. A negative voltage −Vb is applied to the CB0 and CB3. In this case, the applied voltage VS0 is given by the following equations:
VS0=D3/D4 (3)
D3=(4Ca+Ca)×Va+(Cb+Cb)×(−Vb)
=5Ca×Va+2Cb×Vb
D4=(8Ca+4Ca+2Ca+Ca)+(Cb+4Cb+2Cb+Cb)+CS0 (4)
In this case, the value of the denominator is not different from the D2, and D4=D2 is satisfied. When Ca=Cb and Va=Vb, D3=5Ca×Va−2Ca×Va=3Ca×Va is satisfied. More specifically, according to this embodiment, not only an addition process but also a subtraction process (addition of a negative number) can be performed, D/A converter and the addition/subtraction process can be simultaneously performed.
In particular, in this embodiment, when the capacitance of CB3 corresponding to the MSB of the CB3 to CB0 is made equal to CB0 corresponding to the LSB, subtraction in the complementary format of 2 can be performed. More specifically, when subtraction in the complementary format of 2 is performed as is well known, data is inverted, and 1 (corresponding to LSB) must be added. In this case, a method of arranging another capacitor for adding 1 may be used. However, this method increases the circuit scale. In this embodiment, the addition process of 1 is performed using CB3. When the second digital data is a negative number, bit 3 becomes 1; when the second digital data is entirely inverted, bit 3 becomes 0. Therefore, in the subtraction (addition of a negative number) process, in general, charge need not be discharged from the CB3. In this embodiment, CB3 which is not used in the addition process of a negative number is effectively used, and the addition process of 1 is performed by using the CB3 so that the device is reduced in scale.
As described above, it is the first characteristic feature of this embodiment that D/A converter of digital data and various processes such as addition and subtraction processes between digital data or a multiplication process of a coefficient can be simultaneously performed. Therefore, as will be described later, for example, D/A conversion and γ-correction, or D/A conversion and YUV/RGB conversion can be simultaneously performed. As a result, γ-correction, YUV/RGB conversion, and the like can be performed by a digital processing system, and the device can be reduced in scale and power consumption.
It is a second characteristic feature that a display element is driven by effectively using that the display element to be driven is a capacitive element. More specifically, it is the second characteristic feature that an applied voltage applied to the electrode line is determined on the basis of the display element, the capacitance or the like of the electrode line, and charge discharged from the charge storage section. In this manner, a waste current such as a bias current flowing in an operational amplifier need not be consumed, and the power consumption of the device can be reduced. A display element driving device which is optimum for a portable display can be provided.
It is a third characteristic feature of this embodiment that the capacitance of the electrode line during a disharging operation of charge can be made constant without depending on the values of the first to Nth digital data. More specifically, as described in Equations (2) and (4), the values of denominators D2 and D4 are always kept constant without depending on the values of the digital data. Therefore, according to this embodiment, the value of an applied voltage given to the electrode line can be determined with a simple arrangement and simple control.
Embodiments 2 to 6 (to be described below) mainly exemplify a case wherein the present invention is applied to a data driver (display element driving device) for driving a liquid crystal (display element), a liquid-crystal display device (display device) including the data driver, an information processing apparatus including the liquid-crystal display device, and a liquid-crystal driving method (display element driving method).
Embodiment 2 is an embodiment wherein D/A converter and correction of the display characteristics of a liquid crystal are simultaneously performed. The arrangement of this embodiment is shown in FIG. 3. The m-bit digital data corresponding to an image signal is latched by an image digital data latch 212. A correction digital data generator 214 generates correction digital data on the basis of the image digital data. Generation of the correction digital data can be realized by using a memory such as a γ-correction ROM or a circuit or the like for performing an arithmetic operation according to a given arithmetic equation (sin wave or the like). When the γ-correction ROM is used, the γ characteristics of a liquid crystal may be actually measured to construct a γ-correction table for outputting correction digital data using image digital data as an address on the ROM. The generated correction digital data is latched by a correction digital data latch 216.
A D/A converter 200 includes first and second charge storage sections 202 and 204 and first and second connection sections 206 and 208. The first and second charge storage sections 202 and 204 receive image digital data and correction digital data and store charges corresponding to these data. The first and second connection sections 206 and 208 discharge the stored charges to a signal line (electrode line) 210 at a given timing. In this manner, according to the principle of Embodiment 1 described above, the applied voltage VS0 subjected to γ-correction can be applied to the signal line 210. Although not shown in
In
As indicated by G in
In this embodiment, when the number of bits of the image digital data is set to m, and the number of bits of the correction digital data is set to n, the relationship m≧n is established. In this manner, while a state wherein the applied voltage decreases with an increase in image digital data is prevented, the area of the capacitors of the first and second charge storage sections 202 and 204 and the area of the data driver can be reduced. More specifically, according to this embodiment, when the capacitance of the capacitor of the second charge storage section 204 is made smaller than the capacitance of the capacitor of the first charge storage section 202, m≧n can be established. In this manner, each time the number n of bits is made smaller than the number m of bits by 1, the area of the capacitor can be made ½. According to this embodiment, when a voltage for storing a charge in the capacitor of the second charge storage section 204 is made smaller than a voltage for storing a charge in the first charge storage section 202, m≧n can be established. In this manner, the area of the data driver can be reduced to (n+m)/2m. When m=6 and n=4 which may be set within a practical range, about 20% of the area can be saved.
Embodiment 3 is an embodiment for simultaneously performing D/A conversion and YUV/RGB conversion. The arrangement of Embodiment 3 is shown in
Here, the YUV signal is a color signal which is generally used in a television set or a video cassette recorder. Reference symbol Y indicates a total luminance (brightness) of red, green, and blue, reference symbol U indicates the color difference of red, and reference symbol V indicates the color difference of blue. In the YUV signal, it is considered that human eyes are more insensible of a change in color than of a change in luminance. That is, with respect to four pixels, Y information is given to all the four pixels, U information and V information are given to two pixels each. This scheme is called YUV422 (4:2:2). Furthermore, a scheme called YUV411 (4:1:1) in which rates of U information and V information are more reduced may be used.
In recent years, in many multi-media terminals or the like using personal computers, both the YUV and RGB signals are set. On the other hand, a RGB signal is generally used for a display of a liquid-crystal display device. Therefore, when a liquid-crystal display device is used as the display of a multi-media terminal or the like, a YUV signal must be converted into an RGB signal. As conversion equations, the following equations may be used:
R=Y+1.367V
G=Y−0.703125V−0.34375U
B=Y+1.7345U (5)
where Y=0 to 255, U=−128 to 127, V=−128 to 127.
The first to third D/A converters 300 to 304 simultaneously perform the conversion expressed by the above equations and D/A conversion. More specifically, the first to third D/A converters 300 to 304 directly generate analog circuit applied voltages VR1 to VB1 for red, green, and blue from digital data DY1 to DU1 of an input YUV signal. In this manner, a circuit in the data driver can be entirely constituted by a digital system. Therefore, an analog which consumes a lot of power and is not easily designed need not be arranged, and the device can be reduced in power consumption and scale.
When the YUV422 is employed, fourth to sixth D/A converters 306 to 310 having the arrangement shown in
VG1=cDY1+dDU1+eDV1 (6)
=DY1−0.703125DU1−0.34375DV1
In this embodiment, DY1, DU1, and DV1 are input in the complementary format of 2, and DU1 and DV1 have both positive and negative values. For this reason, a subtraction (addition of a negative number) process must be performed. In this embodiment, the capacitances of the capacitors CU7 and CV7 corresponding to the MBSs of DU1 and DV1 are made equal to capacitances Cu and Cv of the capacitors CU0 and CV0, respectively.
As described in Equation (6) described above, since coefficients c, d, and e of DY1, DU1, and DV1 are different from each other, the capacitances of capacitors (capacitors corresponding LSBs), voltages used in storing charges, and the like must be different from each other among the first to third charge storage sections 340 to 343. When the capacitances of the capacitors are made different from each other, for example, Cy:Cu:Cv=c:d:e must be established. However, this condition is not preferable in consideration of a variation in manufacturing process. For example, a case wherein a capacitor using a first polysilicon layer as a lower electrode, a second polysilicon layer as an upper electrode, and an insulation film between the first and second polysilicon layers as a dielectric material is formed will be considered. At this time, in order to cause the ratio of Cy to Cv to satisfy c:e=1:0.34375, the area ratio of the pattern shape on the upper electrode must satisfy c:e=1:0.34375. However, although a pattern shape having an area ratio which can be represented by integers can be easily formed, a pattern shape having an area ratio which is not represented by integers cannot be easily formed. In addition, even if the pattern is formed, the area ratio is considerably influenced by a variation in manufacturing process or the like, and a correct applied voltage cannot be easily generated.
Therefore, in this embodiment, the capacitances of capacitors corresponding to LSBs are made equal to each other (Cy=Cu=Cv), and voltages used in storing charges are made different from each other among the first to third charge storage sections 340 to 343. For example, when voltages VY, VU, and VV are used to store charges of CY7 to CY0, CU7 to CU0, and CV7 to CV0, VY:VU:VV=c:d:e is established. In this manner, the pattern shapes of the upper electrodes of, e.g., CY0, CU0, and CV0 can be made equal to each other, so that simple design can be obtained, and an influence of the variation in manufacturing process on an obtained applied voltage can be optimized. In this case, although the capacitances of, e.g., CY0 and CY1 are different from each other, this difference has no problem because the ratio of these capacitances is an integer ratio.
In order to obtain an integer capacitance ratio regardless of a variation in manufacturing process, a plurality of capacitors having upper electrodes having the same pattern shapes may be connected in parallel to each other.
As shown in
On the other hand, when Y7 is 1, the switch SA7 is turned on, and a voltage VB−Y is selected. A charge is stored in CY7 by the voltage VB−Y.
As shown in
As shown in
In the timing chart shown in
The first latch 420 latches DY2K−1 of the first transfer line 460, and the second latch 422 latches DVK of the second transfer line 462 at a timing which is substantially the same as that of the first latch 420. More specifically, switches 432 and 434 are simultaneously turned on by a signal B1 from the shift resistor 466, and, i.e., digital data DY1 and DV1 are latched by the first and second latches 420 and 422, respectively. The third latch 424 latches DUK of the second transfer line 462, and the fourth latch 426 latches DY2K of the first transfer line 460 at a timing which is substantially equal to that of the third latch 424. More specifically, switches 436 and 438 are simultaneously turned on by a signal B2 from the shift resistor 466, and, e.g., digital data DU1 and DY2 are latched by the third and fourth latches 424 and 426, respectively. The first to sixth D/A converters 400 to 410 generate first and second applied voltages VR1, VG1, VB1, VR2, VG2, and VB2 for red, green, and blue on the basis of DY2−1, DVK, DUK, and DY2K, e.g., DY1, DV1, DU1, and DY2 which are latched by the first to fourth latches 420 to 426. In this case, although the first to sixth D/A converters 400 to 410 preferably have the arrangement shown in
When data is transferred and latched at a timing as shown in
In
In the RGB mode, data input to first to sixth D/A converters 500 to 510 are switched as described below. More specifically, DR1 is input to the first D/A converter 500 in place of DY1 and DV1. DG1 is input to the second D/A converter 502 in place of DY1, DU1, and DV1. DB1 is input to the third D/A converter 504 in place of DY1 and DU1. Similarly, DR2, DG2, and DB2 are input to the fourth, fifth, and sixth D/A converters 506, 508, and 510 in place of DY2 and DV1, DY2, DY1, and DV1, and DY2 and DU1, respectively.
The above switching process will be further described below. In a first transfer line 532, data (to be referred to as RGB/YUV data hereinafter) for determining whether a target image signal is an RGB signal or a YUV signal is transferred. DR, DU, and DV are transferred in a second transfer line 534, DG and DY are transferred in a third transfer line 536, and DB is transferred in a fourth transfer line 538. The switches 540 to 546 are turned on by a B1 signal from a shift resistor 530, so that data flowing in the first to fourth transfer lines 532 to 538 are latched by an RGB/YUV switching circuit 524 and first to third latches 512 to 516. Switches 548 to 554 are turned on by a B2 signal from the shift resistor 530, and data flowing in the first to fourth transfer lines 532 to 538 are latched by the RGB/YUV switching circuit 524 and fourth to sixth latches 518 to 522.
In the YUV mode, DU1, DY1, DV1, and DY2 are latched by the first, second, fourth, and fifth latches 512, 514, 518, and 520, respectively. When the RGB/YUV switching circuit 524 is controlled, switches 560, 562, 564, 566, 568, and 570 are turned off, and switches 580, 582, 584, 586, 588, and 590 are turned on. In this manner, the same signal connection relationship as in
On the other hand, in the RGB mode, DR1, DG1, DB1, DR2, DG2, and DB2 are latched by fourth to sixth latches 512 to 522. When the RGB/YUV switching circuit 524 is controlled, the switches 580 to 590 are turned off, and switches 560 to 570 are turned off. In this manner, RGB digital data are input to the first to sixth D/A converters 500 to 510. A conversion process of converting digital RGB into the analog applied voltages VR1 to VB1 and VR2 to VB2 is performed.
According to this embodiment, both digital YUV and digital RGB can be handled. Therefore, digital YUV and RGB can be directly received from a multi-media terminal in which both YUV and RGB are set, a graphic accelerator, or the like without using a D/A converter or the like, and an analog applied voltage can be generated. In this manner, the data driver can be entirely constituted by a digital system, and the device can be reduced in power consumption and scale.
Embodiment 5 is an embodiment related to a liquid-crystal display device integrally formed on a substrate on which a TFT is formed. Referring to
As shown in
As shown in
Finally, as shown in
Embodiment 6 is an embodiment related to an information processing apparatus (multi-media terminal or the like) including a liquid-crystal display device and an image signal output device for outputting an image signal given to the liquid-crystal display device.
A liquid-crystal display device 700 includes an active matrix section 710 in which data drivers 702 and 704, a gate driver 706, a TFT 708, and the like are formed. As an image information reproducing device 720, for example, a DVD, a CD-ROM, a digital video cassette recorder, or the like may be used. Static image information of, e.g., the JPEG standards output from the image information reproducing device 720 is input to a static image information decoder 722. The static image information decoder 722 decodes the static image information which is subjected to compression or the like of the JPEG standards to output a digital YUV signal. Similarly, moving image information of, e.g., the MPEG standards output from the image information reproducing device 720 is input to a moving image information decoder 724. The moving image information decoder. 724 decodes the moving image information which is subjected to compression or the like of the MPEG standards to output a digital YUV signal. On the other hand, as a computer processing image storage device 726, a VRAM or the like may be used. A digital RGB signal is output from the computer processing image storage device 726.
A digital YUV signal output from a first image signal output device (the image information reproducing device 720, the static image information decoder 722, and the moving image information decoder 724) and a digital RGB signal output from a second image signal output device (the computer processing image storage device 726) are input to an image signal selector 728. One of the YUV signal and the RGB signal is selected to be input to the data drivers 702 and 704. Input/output timings of the signals are controlled by an RGB/YUV timing controller 730 and a computer 732.
The data drivers 702 and 704 include means which, when digital data of the YUV signal is input, directly convert the digital data into analog applied voltages for red, green, and blue to output the analog applied voltages and, when digital data of the RGB signal is input, convert the digital data into analog applied voltages for red, green, and blue to output the applied voltage. As such means, means having the arrangement described in
It is preferable to integrally form the data drivers 702 and 704 and the gate driver 706 on a substrate on which the active matrix 710 is formed. In addition, the static image information decoder 722, the moving image information decoder 724, the image signal selector 728, and the RGB/YUV timing controller 730 may be incorporated in a data driver, so that the data driver may be integrally formed on a substrate on which the active matrix 710 is formed.
The present invention is not limited to Embodiments 1 to 6 described above, and various modified embodiments can be effected within the range of the spirit and scope of the invention.
For example, the above embodiments describe a case wherein the present invention is applied to γ-correction of a liquid crystal and YUV/RGB conversion. However, the present invention can be applied to other various conversion processes.
The present invention can also be applied to a display element driving device other than a data driver, a display device other than a liquid-crystal display device, and an information processing apparatus other than a multi-media terminal. In addition, the present invention can be applied to not only active-matrix-type liquid-crystal display devices using thin-film transistors, thin-film non-linear elements (e.g., MIMs), and the like and data drivers for the active-matrix-type liquid-crystal display devices, but also all liquid-crystal display devices including simple-matrix-type liquid-crystal display devices and data drivers for the liquid-crystal display devices.
| Number | Date | Country | Kind |
|---|---|---|---|
| 8-067304 | Feb 1996 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP97/00609 | 2/28/1997 | WO | 00 | 2/5/1998 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO97/32295 | 9/4/1997 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 4845482 | Howard et al. | Jul 1989 | A |
| 4873516 | Castleberry | Oct 1989 | A |
| 5017914 | Uchida et al. | May 1991 | A |
| 5250931 | Misawa et al. | Oct 1993 | A |
| 5251051 | Fujiyoshi et al. | Oct 1993 | A |
| 5604511 | Ohi | Feb 1997 | A |
| 5625373 | Johnson | Apr 1997 | A |
| 5739816 | Kobayashi et al. | Apr 1998 | A |
| 5764216 | Tanaka et al. | Jun 1998 | A |
| 5796384 | Kim | Aug 1998 | A |
| 5933199 | Yoon | Aug 1999 | A |
| 5940057 | Lien et al. | Aug 1999 | A |
| 6023257 | Koyama | Feb 2000 | A |
| 6154121 | Cairns et al. | Nov 2000 | A |
| Number | Date | Country |
|---|---|---|
| 2-217-128 | Oct 1989 | GB |
| A 57-052228 | Mar 1982 | JP |
| A 58-097918 | Jun 1983 | JP |
| A 59-107628 | Jun 1984 | JP |
| A 62-10696 | Jan 1987 | JP |
| U 63-82228 | May 1988 | JP |
| A 1-233919 | Sep 1989 | JP |
| A 3-35218 | Feb 1991 | JP |
| A 3-89393 | Apr 1991 | JP |
| A 3-190429 | Aug 1991 | JP |
| A 3-214818 | Sep 1991 | JP |
| A 4-11282 | Jan 1992 | JP |
| A 4-502520 | May 1992 | JP |
| A 4-195189 | Jul 1992 | JP |
| A 4-268818 | Sep 1992 | JP |
| A-04-314094 | Nov 1992 | JP |
| A 5-102857 | Apr 1993 | JP |
| A 5-281920 | Oct 1993 | JP |
| A 5-303080 | Nov 1993 | JP |
| A 6-059648 | Mar 1994 | JP |
| A 6-95619 | Apr 1994 | JP |
| A 6-152424 | May 1994 | JP |
| A 6-222741 | Aug 1994 | JP |
| A 6-268522 | Sep 1994 | JP |
| A-06-301365 | Oct 1994 | JP |
| A 7-295520 | Nov 1995 | JP |
| A 7-295521 | Nov 1995 | JP |
| A 8-237125 | Sep 1996 | JP |
| A 8-286641 | Nov 1996 | JP |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 08945522 | Feb 1998 | US |
| Child | 10773703 | US |
