This application claims priority under 35 U.S.C. 119(a) to an application filed in the Korean Intellectual Priority Office on Sep. 27, 2010, and assigned Serial No. 10-2010-093330, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to dynamic resource allocation of processing units and, more particularly, to a method and apparatus that perform dynamic resource allocation by assigning processing units to task blocks so that both Central Processing Unit (CPU) resources and Graphics Processing Unit (GPU) resources are efficiently utilized.
2. Description of the Related Art
Processing units, such as CPUs, GPUs and Coarse-Grained Reconfigurable Architectures (CGRA), may be realized using computational software. A CPU, GPU and CGRA are described in greater detail below with reference to
As illustrated in
Recently, processors having multiple cores or GPUs having multiple PEs have been widely employed. In particular, high-end processing units, such as GPUs, may include dozens to hundreds of PEs.
As the number of processing units increases, it is crucial to efficiently manage resources, including these processing units, to enhance overall system performance.
In general, GPU processing is initiated when the CPU invokes the GPU. In order for the GPU to execute a task, the CPU may set a GPU register. Hardware threads have been utilized to execute multiple operations in parallel in the GPU. Using these hardware threads, processing elements may be grouped, and groups of processing elements may execute in parallel. As described above, systems generally evolve toward maximizing parallel operation execution.
However, existing techniques tend to sequentially utilize the CPU and the GPU.
Referring to
As described above, in sequential resource utilization, the CPU and the GPU are not utilized simultaneously and not all processing elements of the GPU are used. When a task is not partitioned in the GPU, the whole GPU may be occupied by a single task. Since most application programs do not utilize all the processing elements of the GPU, GPU resources may be wasted, degrading system performance.
The present invention has been made to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an aspect of the present invention provides a method and apparatus that perform dynamic resource allocation by assigning processing units to task blocks so that both CPU resources and GPU resources are efficiently utilized.
According to one aspect of the present invention, a method is provided for dynamic resource allocation for a system having at least one processing unit. Information on a task to which resources are to be allocated is received and the task is partitioned into one or more parallel task units. The one or more parallel task units are converted into a task block having a shape that is formed based on estimated execution times of the one or more parallel task units and whether dependency exists between the one or more parallel task units. Resources are allocated to the task block by placing the task block on a resource allocation plane having a time axis and a processing unit axis. The task is executed according to resource allocation information determined by the resource allocation plane.
According to another aspect of the present invention, an apparatus is provided for dynamic resource allocation in a system having at least one processing unit. The apparatus includes a dynamic resource allocation block that receives information on a task to which resources are to be allocated, partitions the task into one or more parallel task units, converts the one or more parallel task units into a task block having a shape that is formed based on estimated execution times of the one or more parallel task units and whether dependency exists between the one or more parallel task units, and allocating resources to the task block by placing the task block on a resource allocation plane having a time axis and a processing unit axis. The apparatus also includes at least one processing unit that executes the task according to resource allocation information determined by the resource allocation plane.
According to a further aspect of the present invention, an article of manufacture is provided for dynamic resource allocation for a system having at least one processing unit. The article of manufacture includes a machine readable medium containing one or more programs which when executed implement the steps of receiving information on a task to which resources are to be allocated and partitioning the task into one or more parallel task units; converting the one or more parallel task units into a task block having a shape that is formed based on estimated execution times of the one or more parallel task units and whether dependency exists between the one or more parallel task units; allocating resources to the task block by placing the task block on a resource allocation plane having a time axis and a processing unit axis; and executing the task according to resource allocation information determined by the resource allocation plane.
The above and other aspects, features and advantages of the present invention will be more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:
Embodiments of the present invention are described in detail with reference to the accompanying drawings. The same or similar components may be designated by the same or similar reference numerals although they are illustrated in different drawings. Detailed descriptions of constructions or processes known in art may be omitted to avoid obscuring the subject matter of the present invention.
The present invention provides a dynamic resource allocation method and apparatus that enable efficient utilization of CPU and GPU resources.
The CPU 410, GPU 420 and CGRA 430 are examples of processing units capable of processing tasks. In particular, the CPU 410 may be a multi-core processor 415 having multiple cores. The GPU 420 may not only perform graphics operations but may also process high-volume tasks in cooperation with the CPU 410. In order to achieve these functions, the GPU 420 may include multiple PEs. Processing units, including the CPU 410 and the GPU 420, provide information on a task to be processed to the dynamic resource allocation block 450, receive results of resource allocation from the dynamic resource allocation block 450, and process the task according to scheduling information.
The multiple cores of the CPU and the PEs of the GPU may have different structures and functions. However, because a core and a PE may be the same in view of task execution, they are both referred to as a PE in the following description. This may also be applied to other processing units composed of cores, or cores and PEs.
The memory 440 stores programs and related data necessary for overall operations of the dynamic resource allocation system.
The dynamic resource allocation block 450 converts a task to be processed by PEs into a task block. The task to be processed is partitioned into multiple parallel task units, and the parallel task units are arranged into a task block based on dependency between the parallel task units.
The dynamic resource allocation block 450 performs resource allocation by assigning PEs, which may execute in parallel, to the task block. In order to perform resource allocation, the dynamic resource allocation block 450 may receive current states (i.e., an active state or an idle state) of PEs from the PEs of the CPU and GPU. The dynamic resource allocation block 450 performs resource allocation only to PEs that are currently in the idle state.
The dynamic resource allocation block 450 is capable of performing resource allocation for a new task block and resource allocation for a task block that had its previous execution end early or late due to an error in an estimated execution time. Processes for generation of a task block and resource allocation are described in detail below with reference to
An application or application program may generate at least one task for execution, and the at least one task may be executed by at least one PE. For parallel processing of a single task using multiple PEs, as shown in
Dependency between parallel task units indicates that one parallel task unit requires the processing results of another parallel task unit. When there is no dependency between the parallel task units, the parallel task units may be processed at the same time by parallel PEs as illustrated by
When there is dependency between two or more of the parallel task units, there are timing limitations in the processing order of the parallel task units. Accordingly, a task block has a trapezoidal form, as illustrated in
Referring to
The dynamic resource allocation block 450 obtains information on estimated execution times of the parallel task units from the operating system or the compiler, in step S620. The dynamic resource allocation block 450 may determine the length of each parallel task unit, which is proportional to the execution time thereof. Execution histories may be used to determine the length of a parallel task unit.
The dynamic resource allocation block 450 examines dependency between the parallel task units, in step S630. When a parallel task unit uses the processing results of another parallel task unit, dependency is present between the two parallel task units. The processing order of the parallel task units may be determined by the dependency therebetween.
The dynamic resource allocation block 450 determines a polygonal shape covering a region in which the parallel task units are arranged according to dependency, in step S640. When no dependency is present between the parallel task units, the polygonal shape may be set to a square or a rectangle. When dependency is present between the parallel task units, the polygonal shape may be set to a parallelogram. The shape of the parallelogram may contribute to improving the computation speed and efficiency. The slope of the parallelogram may vary according to the amount of dependency between parallel task units.
The resource allocation plane of
Placement of task blocks on the resource allocation plane may have complexity of O(n3) according to the number of used processing elements, the number of tasks, expected execution times, and the slope due to dependency. O denotes the complexity and n denotes the number of used processing elements, the number of tasks, expected execution times, and the slope due to dependency.
A task block generated by the procedure of
Referring to
The dynamic resource allocation block 450 moves the task block downwards (increasing the PE index) until the task block does not conflict with a task block that has already been placed on the resource allocation plane, in S820. Step S820 of
The dynamic resource allocation block 450 moves the task block horizontally to the left (decreasing the time value) until the task block conflicts with a task block that has already been placed on the resource allocation plane, in step S830. Step S830 of
The dynamic resource allocation block 450 moves the task block downwards (increasing the PE index) until the task block does not conflict with a task block that has already been placed on the resource allocation plane, in step S840. Step S840 of
The dynamic resource allocation block 450 checks whether all the PEs have been examined, in step S850. When all the processing elements have not been examined, the dynamic resource allocation block 450 returns to step S830 and continues the placement process. In
When all the PEs have been examined, the dynamic resource allocation block 450 places the task block at a position on the resource allocation plane corresponding to coordinates with the smallest time value among the coordinates recorded at each step.
Through the above-described procedure, the dynamic resource allocation block 450 places a task block on the resource allocation plane so that both CPU resources and GPU resources are efficiently utilized, enhancing overall system performance.
The control unit 1010 performs and controls a series of operations, as described with respect to
The control unit 1010 uses the processing bank 1020 to place task blocks on the resource allocation plane. The control unit 1010 outputs a task selection signal Isel and a register unit selection signal Csel. The task selection signal Isel is used to identify a task block to be placed, and the register unit selection signal Csel is used to move a task block vertically (without a change in time) on the resource allocation plane.
The processing bank 1020 has a horizontal axis of time and a vertical axis of PEs, and includes many registers on crossings between discrete times and PE indexes.
The resource allocation information is mapped on the processing bank 1020 as indicated by the dotted lines in registers of the processing bank 1020. For example, resource allocation information 1030A corresponds to task block 1030B. Specifically, task block 1030B uses three processing elements from PE0 (“PE Start=0”, “PE Count=3”), starts at time 2 (“Time Start=2”), and has a slope of 2 (“Slope=2”).
The processing bank 1020 performs actual operations, and main parts thereof may be implemented using combinational logic circuits for fast computation, which is described in detail with reference to
As shown in
The task selection signal Isel, from the control unit 1010 of
Referring to
A task block (I) is selected according to the task selection signal fed to the rear registers 1220. The selected rear register 1220 is ANDed with all the front registers 1210 (“Step 2”, “Step 4” or “Step 6” in
Accordingly, resource allocation to a task block based on the descriptions corresponding to
After comparison for all task selection and register unit selection signals, when the final output is set to ‘0’, the task block is shifted in time from the current time (Tn) to the preceding time (Tn+1) and the task block is moved to a register unit enabled by the register unit selection signal.
Referring to
The dynamic resource allocation block 450 converts a task to be processed into a task block and assigns idle processing elements to the task block, in step S1330. The dynamic resource allocation block 450 forwards the resource allocation information to PEs of the CPU and GPU, in steps S1340 and S1350. PEs of the CPU and GPU perform task processing at given times according to the resource allocation information and record processing results, in steps S1360 and S1370.
The dynamic resource allocation block 450 receives the task processing results from the PEs, in step S1380. The dynamic resource allocation block 450 checks whether all tasks are processed, in step S1390. When all tasks are not processed, the dynamic resource allocation block 450 returns to the initial steps S1310 and S1320 and continues task processing. When all tasks are processed, the dynamic resource allocation block 450 terminates the methodology.
As described above with respect to
In step S1410, it is determined whether dynamic resource allocation involves the addition of a new task. When it involves the addition of a new task, resource allocation is handled for subsequent times after a current time, in step S1430. When it does not involve the addition of a new task, it is determined whether there was an error in estimated time information, in step S1420. When there was an error in estimated time information, resource allocation is handled for subsequent times after the current time, in step S1430. When there was no error in estimated time information, the methodology of
In
The processing bank 1020 checks whether all new task block IDs have been placed, in step S1505. When all task block IDs have been placed, the processing bank 1020 sends processing results to the control unit 1010, in step S1510, and ends the resource allocation procedure, in step S1515.
When all task block IDs have not been placed, the processing bank 1020 starts to place a next task block ID, in step S1520. The processing bank 1020 selects a next task block ID according to the task selection signal from the control unit 1010 and starts to perform resource allocation for the next task block.
The processing bank 1020 performs resource allocation using the register unit selection signal from the control unit 1010. Specifically, as the register unit selection signal is incremented from 1 to 2, 3, 4, . . . , the task block is moved downwards without changing the time on the resource allocation plane.
The processing bank 1020 checks whether all operations related to the register unit selection signal have been processed for all time units, in step S1525. When not all operations have been processed, the processing bank 1020 performs Tn and Tn+1 operations for each value of the register unit selection signal, in step S1530. Specifically, it is determined whether the task block is movable to the left in one time unit on the time axis of the resource allocation plane. In step S1535 it is determined whether an ‘OR’ operation result is ‘1’, indicating that there is a conflict with a previously placed task block. When the operation result is ‘1’, the processing bank 1020 increments the value of the register unit selection signal, in step S1540. Specifically, the task block is moved downwards on the resource allocation plane. Step 1540 of
When the operation result is ‘0’, the processing bank 1020 shifts the task block in time from Tn+1 to Tn, in step S1545. Specifically, the task block is moved to the left on the horizontal axis of the resource allocation plane, which corresponds to “Step 3” of
After repeating the above operations, the processing bank 1020 stores coordinates ((time, PE index) or (Tn, value of register unit selection signal)) of the task block that has been maximally moved to the left, in step S1555, before returning to step S1530.
When it is determined that the operation of
According to the embodiments of the present invention described above, CPU resources and GPU resources in the system can be used in parallel at the same time, increasing overall system efficiency.
Software components including instructions or code for performing the methodologies described herein may be stored in one or more of the associated memory devices (e.g., Read Only Memory (ROM), fixed or removable memory) and, when ready to be utilized, loaded in part or in whole (e.g., into Random Access Memory (RAM)) and executed by the CPU.
While the present invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.
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