Patent Application
20080077741
The above object and features of the present invention will be more apparent from the following description of the preferred embodiments given with reference to the accompanying drawings, wherein:
According to a first embodiment of the invention, there is provided a method of dynamic management of memory in accordance with a priority class receiving as input frame data of a plurality of classes of different degrees of priority and storing or discarding the frame data in/from a memory of the frame data in accordance with the priority class of the frame data, the method of dynamic management of memory comprising partitioning an area of the memory into a plurality of areas to form memory banks and having the different priority classes share the memory banks, dynamically assigning empty memory banks to the storage of frame data of the different priority classes, and controlling the writing, reading, and discarding of the frame data with respect to each memory bank assigned for each priority class.
According to a second embodiment, there is provided a method of dynamic management of memory in accordance with a priority class of the first embodiment further comprising defining a capacity smaller than a largest capacity among memory capacities for the priority classes required for storage of frame data for each of the priority classes input in a burst within a predetermined time as the capacity of the memory banks, and storing a plurality of frame data for each priority class input in a burst by assigning the plurality of memory banks.
According to a third embodiment, there is provided a method of dynamic management of memory in accordance with a priority class of the first embodiment further comprising setting a lowest limit of usable memory and a maximum limit of usable memory for each of the priority classes and, when assigning the memory banks to the storage of the frame data of the different priority classes, assigning at least a memory bank having the lowest limit of usable memory for a priority class for which the lowest limit of usable memory is set and assigning memory banks up to the maximum limit of usable memory for a priority class in which the maximum limit of usable memory is set.
According to a fourth embodiment, there is provided a method of dynamic management of memory in accordance with a priority class of the first embodiment further comprising, when storing frame data of a higher priority class in a memory bank which has been already assigned to the storage of frame data of a low priority class, sequentially writing frame data of the higher priority class from the area where the frame data of the low priority class has been already read out from the memory bank and continuing to read out frame data of the low priority class without discarding the frame data of the low priority class until a write pointer indicating the address for writing the frame data of the higher priority class catches up with a read pointer indicating the address for reading the frame data of the low priority class from the memory bank.
According to a fifth embodiment, there is provided an apparatus for dynamic management of memory in accordance with a priority class receiving as input frame data of a plurality of classes of different degrees of priority and storing or discarding the frame data in or from the memory in accordance with the priority class of the frame data, the apparatus for dynamic management of memory in accordance with a priority class comprising memory banks configured by partitioning the area of the memory into a plurality of areas and a write controller and a read controller for controlling the writing, reading, and discarding of the frame data in units of the memory banks and having the different priority classes share the memory banks, dynamically assigning empty memory banks to the storage of frame data of the different priority classes, and controlling the writing, reading, and discarding of the frame data with respect to each memory bank assigned for each priority class.
According to the present invention, by having different priority classes share memory banks obtained by partitioning the area of the memory into a plurality of areas and dynamically assigning memory banks to the priority classes, individual memories become unnecessary, and the memory for storing the data need only have a capacity between the conventional individual memory management system and shared memory management system. The memory capacity of each priority class can be dynamically changed, so when a larger memory is required by a class of a higher degree of priority, memory capacity can be assigned to the memory area for that higher class, and when a memory area of a class of a low degree of priority is required, memory capacity can be assigned to the memory area for that low class. By assigning memory in accordance with the degree of priority in accordance with the situation with a relatively small memory capacity, the memory can be effectively and actively used.
Further, by controlling the assignment of memory to the different priority classes in units of memory banks, a relatively simple control circuit can dynamically assign and change memory in accordance with the priority class. Further, by providing a plurality of memory banks having smaller memory capacities than that required for the storage of frame data input in bursts and storing a plurality of frame data input in bursts by using a plurality of memory banks, the memory can be efficiently used.
Further, by assigning at least a memory bank having the lowest limit of usable memory to a priority class for which the lowest limit of usable memory is set and assigning memory banks up to the maximum limit of usable memory to a priority class for which the maximum limit of usable memory is set, use of all memory banks for the storage of frame data of a high degree of priority is prevented. Even when a fault causing delay of reading of frame data of a high degree of priority occurs, this can be prevented from affecting the storage of frame data of a low priority class. At the same time, service guaranteeing the lowest limit of bandwidth for the low priority class can be provided.
Further, when storing frame data of a higher priority class in a memory bank in which frame data of a low priority class is already stored, by continuing to read the frame data without discarding the frame data of the low priority class until the write pointer for writing the frame data of a higher priority class catches up with the read pointer for reading the frame data of a low priority class, more effective utilization of the memory can be achieved.
The preferred embodiments of the present invention will be described in further detail below while referring to the attached figures.
The dynamic memory management system according to the present invention uses memory having a capacity exceeding 15 Mbits as the total memory capacity. In the example of configuration shown in
While explained in the following embodiments as well, as an initial default capacity of the buffer area for the storage of data of classes A, B, C, and D, one memory bank, that is, the 5 Mbits, is assigned to each class, but the policer (write controller) 1-2 and the scheduler (read controller) 1-3 control the writing and reading so as to also enable the use of those areas as spare areas for the storage of data of other classes. Further, it is assumed that two memory banks of 5 Mbits are prepared for use as spare areas from the first. Therefore, a memory having 30 Mbits' worth of capacity in total is used.
The first state shown in (ii) of
Even when there is a further change from the second state shown in (iii) of
Therefore, as an embodiment of the present invention improving on this, an explanation will be given below of a method for dynamic assignment of class buffers and spare areas. This method assigns memory banks on the left side by the initial default to the storage of data of the classes A, B, C, and D as class buffers as shown in (i) of
(ii) of
At this time, the buffer area originally assigned to the class C by the initial default becomes an empty area and is released as a spare area usable by any class. (v) of
The write controller 4-2 refers to the memory empty space management bit 4-3 showing the empty state of each memory bank and judges whether or not there is an empty space in the memory bank. When there is an empty space in the memory bank, the data of the received frame is written in it. When there is no empty space in the memory bank, the data of the received frame is discarded.
When the class data is received and there is an empty space in the memory bank, in order to make the empty memory bank the data storage area, the memory empty space management bit 4-3 of the memory bank is set to indicate the congested state, the discrimination information of the memory bank (3 bits representing six memory banks) is set in the memory bank information portion 4-4 corresponding to the class, the valid data is stored in the memory bank, and a valid bit 4-5 indicating that reading is necessary is set.
Then, “1” is added to a remainder counter 4-6 indicating the number of received frames stored corresponding to the class. Further, the write controller 4-2 judges if a received frame length exceeds an empty area count of the memory bank. When the received frame length exceeds the empty area count of the memory bank, the frame is not written into the memory bank. Namely, one received frame is not stored over a plurality of memory banks.
Further, if the minimum frame length of the received frame is for example 64 bytes, when the empty area count of the memory bank is 15 or less, that is, the remaining amount of write addresses of the memory bank is 15 or less, the frame is also not written into the memory bank. This is because, when assuming that each word (32 bits) of data is stored at one address of the memory bank, 16 addresses' worth of empty area is required for storing the 64 bytes of data and 1 frame's worth of the data or more cannot be stored when the empty area count is 15 or less.
The write address controller (Wadr_ctr) 4-7 in the policer is provided corresponding to each of the classes A, B, C, and D. Each outputs the address value of the memory bank 4-8 incremented by “1” whenever 32 bits (1 word) of frame data is written into the memory bank 4-8.
Then, when the last data of the received frame is written into the memory bank 4-8, the write address controller (Wadr_ctr) 4-7 stops the count. When receiving the next frame, it increments the stopped address value by “1” then stops the count when the header data to the last data of the received frame are written in the memory bank 4-8 in a repetition of the operation.
When the write controller 4-2 writes the data up to near the last address of one memory bank 4-8, it performs processing for referring to the memory empty space management bit 4-3 to judge whether or not there is another empty memory bank and writing the data of the next received frame into the empty memory bank.
The read controller 4-10 in the scheduler performs the control so as to sequentially read out data from the class of the highest degree of priority. Namely, it continuously reads out all data of the class A by the read address controller (Radr_ctr) of the class A until the value of the remainder counter 4-6 becomes zero. When finishing reading out the data of the class A, its starts the reading of the data of the class B by the read address controller (Radr_ctr) 4-9 of the next class B.
When finishing reading all data of the class B, the read address controller (Radr_ctr) 4-9 of the next class C starts to read the data of the class C, then when finishing reading all of the data of the class C, the read address controller (Radr_ctr) 4-9 of the next class D reads the data of the class D for read processing in that order.
In the read control, when the read processing proceeds up to the last address area of each memory bank 4-8 or when the value of the remainder counter 4-6 corresponding to each class becomes zero, the memory empty space management bit 4-3 corresponding to the memory bank and the valid bit 4-5 are cleared. The remainder counter 4-6 is provided for each class, is incremented by “1” whenever 1 frame's worth of the data is written into the memory, and is decremented by “1” whenever 1 frame's worth of the data is read out from the memory.
On the reading side, when the read operation proceeds up to the last address of one memory bank 4-8 and the value of the remainder counter 4-6 of the class of a high degree of priority is not zero, the valid bit 4-5 of the memory bank information 4-4 of that class is referred to. When that valid bit is set, the read processing of the data continues from the memory bank in which the data of that class is stored.
When the valid bit of the class of a high degree of priority is not set, the read processing of the data of the class of next highest degree of priority is carried out. As in the above processing, the write control and read control are executed with reference to information of the remainder counter 4-6, memory empty space management bit 4-3, memory bank information 4-4, and valid bit 4-5.
A specific example of the class judgment in the class discriminator 4-1 is shown in
0/1: Class A, 2/3: Class B, 4/5: Class C, 6/7: Class D.
Note that in the MPLS frame, S (Bottom of Stack) is a field indicating the last label in the label stack, “S=0” indicates that labels follow, and “S=1” indicates the last label in the label stack. TTL (Time to Live) indicates a remaining lifetime of this packet. This value is decremented whenever it passes through a router up to the destination of the network. The packet is discarded when the value becomes 0.
Note that, in the above frame, “CFI” is a canonical format indicator (“0”: little endien, “1”: big endien). At present, it is a field for writing a DSCP value of DiffServ. “VLANID” is a VLAN ID number. This VLANID is used to recognize a specific user and perform routing to the destination. However, the present invention is not limited to an MPLS frame or VLAN frame etc. and may employ a configuration using a bit of another frame format for the class judgment.
Further, a specific example of designation of the length value of the internal processing frame in the present invention is shown in
A specific example of the operation of the present invention will be explained next. The following example of operation is an example of operation when partitioning the memory into six areas as a first example of the configuration. The memory may be partitioned into any number of areas, but in the case of partitioning it into six, memories for {memory bank information (3 bits)+valid bit (1 bit)}×6 (number of partitions)×4 (classes)=96 bits of management information and for the memory management bit (1 bit) indicating presence of a memory bank×6 (number of partitions)=6 bits become necessary. These fluctuate according to the number of partitions.
As another configuration, when partitioning the memory into for example 10 areas, memories for {memory bank information (4 bits)+valid bit (1 bit)}×10 (number of partitions)×4 (classes)=200 bits and for a memory management bit (1 bit) indicating presence of memory×10 (number of partitions)=10 bits become necessary.
The data of the write address controller (Wadr_ctr) 4-7 and the data of the read address controller (Radr_ctr) 4-9 require a number of bits for indicating the address space of the entire memory. For example, assuming that each memory bank writes one word (=32 bits) of data into each address and each memory bank has the capacity of 5 Mbits, each memory bank has an address space of 156250 as apparent from the following equation.
5 Mbits*1 word(=32 bits)=156250
Each of the six memory banks has an address space of 156250, therefore the address space of the entire memory becomes 937500 (=156250×6). Because 937500 (dec)=E4E1C (hex), 20 bits become necessary in order to represent the address space of 937500.
The remainder counter needs a number of bits enabling count of the number of frames when frames having the minimum frame length are stored in the entire memory until it is full. Assuming that the minimum frame length of 1 frame is 64 bytes, since 64 bytes correspond to 16 words, 58594 (=937500÷16) becomes the maximum number of frames able to be stored in the entire memory. Because 58594 (dec)=E4E2 (hex), the counter for counting 58594 frames may be a counter of 16 bits.
First, as a first case, the state of completion of an operation for receiving and writing 64 bytes of data of the class A is shown in
Further, the remainder counter (16 bits) of the class A is incremented by only “1”, and the memory empty space management bit indicating the presence of empty space of the memory bank #1 is set at “1” (=no empty space). Further, as the first area for storing the data of the class A, the memory bank information “000” indicating the memory bank #1 and the valid bit “1” indicating that the valid data is stored in that area are set.
Next, as a second case, the state of completion of an operation for receiving and writing 64 bytes of data of the class A after the operation of the first case described above is shown in
The read controller refers to the memory bank information “000” of the first area and increments the count of the read address controller (Radr_ctr) address from 0 to 15 and sequentially reads out the data so as to read out the data of the class A from the memory bank #1. When finishing reading all of the data, it returns the valid bit “1” of the first area to “0”, sets the value of the remainder counter (16 bits) from 1 to 0, and makes the memory management bit indicating the presence of empty space “0” (empty space exists). In this way, the write processing and read processing of data are carried out with respect to 1 frame of received data.
Next, as a third case, the state of completion of an operation for receiving and writing 1500 bytes of data of the class B is shown in
The counter of the write address controller (Wadr_ctr) of the class B counts 1500 bytes (1500÷4=375) worth of addresses from the initial value 156250 whereby the value becomes 156624 (=156250+375−1). The basic operation is the same as the processing operation in the class A mentioned before (first case).
As a fourth case, the state of completion of an operation for receiving and reading 1500 bytes of data of the class B is shown in
In the fifth case, when reading the data of the class B, the data of the class C is written. The 64 bytes of write data are small in amount of data in comparison with 1500 bytes of the read data, therefore this processing of writing is completed earlier in this example of operation. The counter value etc. become the state shown in the figure.
The state where the data of the class B is stored in the memory bank #2, and the data of the class C is stored in the memory bank #3 is shown. The write operation and the read operation are independently processed in this way, therefore the write processing of the data into the memory bank is possible while reading the data from the memory bank.
Further, as a sixth case, the state of completion of an operation for receiving and writing 1500 bytes of data of the class B and a second operation for receiving and writing 64 bytes of data of the class C is shown in
For this reason, the value of the remainder counter of the class C becomes 2. The memory bank information of the class C is “002” indicating the memory bank #3, and the valid bit thereof is in the state of “1”. Note that, the data length such as 1500 bytes is recognized by referring to the data length information stored in the header of the frame. The read controller reads out any frame length.
For example, the overall address space of the memory bank #4 is 468750 to 624999. When data is stored in 468750 to 624625 of that, the addresses of the remaining area become 624626 on, and the address space of the empty area becomes 374 or less, the memory bank #4 is deemed to be full.
This is because 4 bytes of data are stored at 1 address, the above 374 address space can only store a frame up to 1496 bytes (=374×4 bytes), and, when a frame of the maximum length, that is, a frame of 1500 bytes, is received, that empty area cannot store all of the frame data, therefore, when the empty area becomes less than the maximum frame length, the memory bank is deemed full. By setting this, the storage of one frame separated into a plurality of memory banks is prevented, and the address control by the write address controller (Wadr_ctr) and the read address controller (Radr_ctr) can be more simplified.
In the read processing, it is confirmed whether or not the value of the remainder counter of the class A is other than 0 (step 15-8). When it is other than 0, the read processing of the data of the class A is started (step 15-9). The remainder counter is provided for each class. The remaining count thereof is confirmed from the class having the highest degree of priority, then the read processing is started. The count up (0→15) of the read address controller (Radr_ctr) is carried out for the class A (step 15-10), the data is read out from the memory bank #1 (step 15-11), then the transmission of that data is started.
When finishing reading 64 bytes of data of the class A, the memory bank information of the class A is cleared and the valid bit is cleared (“1”→“0”) (step 15-12), the memory empty space management bit of the memory bank #1 is set at “0” (empty) (step 15-13), the remainder counter of the class A is changed from 1 to 0 (step 15-14), and the transmission of the frame is completed (step 15-15).
Basically the write processing and the read processing are carried out in this way. The operation is the same even when frame lengths are different. Further, the write processing and the read processing independently operate. For the write processing, the write processing is carried out when there is empty space in the memory bank. For the read processing, the read processing is started when the remainder counter is other than 0.
In the above operation, when the same degree of bandwidth is secured for the output as with the bandwidth of the input, the memory never keeps just the data of the received frames. However, the data output from the scheduler sometimes stops being read according to the state of the destination of connection thereof.
For example, this happens when the channel of the destination of connection is congested or when a fault occurs. In such cases, the data stops being read from the memory. Data is only written into the memory. Therefore, the data begins to gradually build up in the memory. Below, the operation when the data begins to be stored in the memory and the write controller writes the data of one class over a plurality of memory banks will be explained.
Here, if the maximum length of an input frame is for example 1500 bytes, when the remaining space of a memory bank becomes 1500 bytes or less, it is judged that the memory bank is full and control is performed to write the data into the next memory bank. This can be automatically judged on the basis of the write address.
The following example is an explanation given relating to the memory bank #4. As explained in
Further, in the remainder counter as well, the count differs according to the frame length—which changes between the minimum frame length of 64 bytes and the maximum frame length of 1500 bytes, therefore a value within a range from the count 9765 (=5 Mbits÷64 bytes) in the case of all 64-byte length (min) frames to a count 416 (=5 Mbits÷1500 bytes) in a case of all 1500-byte (max) frames becomes the number of frames stored in one memory bank. Here, assuming that N number of memory banks are used to store the frames, the number of all frames becomes a number from N×416 to 9765.
Next,
Next, the writing and discarding of data of the memory in accordance with the degree of priority will be explained.
In this example of operation, the data of the memory banks #4 and #5 in which the data of the class D are written are discarded. Then, valid bits of the first and second areas corresponding to the memory banks #4 and #5 of the memory bank information of the class D are cleared to “0”, bits of the memory banks #4 and #5 in the memory empty space management bit are cleared to “0”, and the remainder counter for the class D is cleared to 0. In this way, the memory bank in which the valid bit of the class having the lowest degree of priority becomes “1” is returned to the state with empty space.
In this example of operation, the valid bit of the class C is cleared to “0”. The memory bank information is “010” indicating the memory bank #3, therefore the value of the memory bank #3 in the memory management bits is cleared to “0”. Further, the remainder counter of the class C is made 0.
Next, embodiments modifying the basic configuration of the present invention mentioned above will be explained. A first modification is an example of configuration setting a memory area guaranteeing the lowest limit of area for each class and a memory area of the maximum limit able to be used. The memory area of the lowest limit and the memory area of the maximum limit can be freely set for all classes, but in this example of configuration, only the classes C and D are overwritten in the memory and discarded. The classes A and B are not overwritten once they are written into the memory.
Classes A and B of high degrees of priority are always written into the memory even when there is no empty space in the memory by being written over data with low priority, but an upper limit is previously set for the memory area usable when there is no empty space in the memory. A memory area is guaranteed up to the above upper limit as the maximum limit of usable memory area when there is no empty space in the memory. For classes C and D, the previously determined lowest limit memory area is guaranteed, but the use of an area usable more than that becomes possible within the range of the empty area only in a case where there is an empty space in the memory. By setting this, the high priority class can be prevented from monopolistically eating up the memory area.
As an example of setting the lowest limit of usable memory, each class can use a memory amount of 4 Mbits as the lowest limit. Due to this, all classes are guaranteed the use of the lowest limit of memory without being influenced by other high priority classes. Further, as an example of setting the maximum limit of usable memory, the high degree of priority can always use up to 10M of the memory.
In a second example of configuration explained below, 15 memory banks each having a capacity of 2 Mbits are used as shown in
Accordingly, the following example of operation will be explained by assuming that each memory bank has 10 address spaces by simple address conversion of 1 frame, and the write address controller (Wadr_ctr) and the read address controller (Radr_ctr) count up one address worth of data at the time of writing and reading 1 frame.
In
From the above, the write address controller (Wadr_ctr) of the class D jumps from 30 in the initial setting to the header address 100 of the bank #11 and counts up to 109 therefrom. Then, it clears the valid bit of the memory bank #11 (discrimination information “11011”) of the first area of the memory bank information of the class C to “0”, sets “1011” indicating the memory bank #11 in the first area thereof as the memory bank information of the class D, and sets the valid bit thereof at “1”. Further, the simplified remainder counter of the class C subtracts 10 frames from 50 to obtain 40 and sets it, while the simplified remainder counter of the class D adds 10 frames to 0 to obtain 10 and sets it.
For this reason, the write address controller (Wadr_ctr) of the class D moves to the header address 110 of the bank #12 and counts up to 119 therefrom. Then, it clears the valid bit of the memory bank #12 (discrimination information “1100”) of the second area of the memory bank information of the class C to “0”, sets “1100” indicating the memory bank #12 in that second area, and sets the valid bit thereof at “1”. Further, the simplified remainder counter of the class C subtracts 10 frames from 40 to obtain 30 and sets it, while the simplified remainder counter of the class D adds 10 frames' worth to 10 to obtain 20 and sets it.
Namely, the data of the class A is written into an empty area of the memory bank in which the data of the class C is stored. The data of the class C is held as is until the position of the write pointer comes to the position of the read pointer of C. When it comes to the position of the read pointer of the data of the class C, priority is given to the data of the class A and all of the data of the class C are discarded, but the data of the class A and the class C use the same memory bank until the pointers are superimposed.
If the data of the class C finished being read before the write pointer of the data of the class A catches up with the read pointer of the data of the class C, the data of the class C is not discarded. The memory is shared in the same memory bank, so and the memory can be effectively utilized.
In
In this way, it is possible to write data of classes of different degrees of priority into the same memory bank. In the previously explained embodiments, the data of classes of different degrees of priority could not be stored in the same memory bank, but by referring to the pointer for each class as described above, the data of different classes can be stored up to just before the superimposition of pointers on each other in the same memory bank, so the effective usage of the memory becomes possible.
This is because, by comparing the address of the write address controller (Wadr_ctr) of the class A and the address of the read address controller (Radr_ctr) of the class C, when the address of the write address controller (Wadr_ctr) of the class A is less than the address of the read address controller (Radr_ctr) of the class C, data of different classes can be made to co-exist in the same memory bank.
When writing 4 packets of the class A in total from the above second state, a third state shown in (iii) of the same figure is exhibited, and a state where the write pointer of the class A catches up with the read pointer of the class C is exhibited. A configuration is formed wherein, when writing 1 packet of the class A from this third state, all of the packets of the class C are not discarded, but packets are discarded in units of 1 packet, although packets of the class A are written into the memory with a high priority, also packets of the class C are kept alive as much as possible.
A memory for storing the information for this pointer management becomes necessary. The capacity of the memory becomes as follows. As a memory replacing the memory bank information used for each class mentioned before, for the class C and the class D, a memory having for example 20 storage areas of the point management information having a bit width of 24 bits is prepared. Here, the bit width 24 bits is a sum of the 20 bits' worth of the header point, 3 bits' worth of the discrimination information of the memory bank, and 1 bit's worth of the valid bit.
Assuming that six memory banks each having a capacity of 5 Mbits are used for 20 bits of the header pointer, and the data of 32 bits (=1 word) is stored pe address, there are 156250 addresses per memory bank, the whole six memory banks have an address space of 937500 (=156250×6) (dec)=E4E1C (hex), and 20 bits become necessary for representing this.
However, the data at the addresses 312516 to 312531 at which the second frame of the class C are stored are not discarded, but the valid bit of the second frame of the pointer management information is held at “1” as it is, and the remainder counter of the class C is counted down from 2 to 1.
When further receiving 64 bytes of data of the class A, the data at the addresses 312516 to 312531 at which the above second frame of the class C had been stored are discarded, and the data (64 bytes) of the class A are stored at those addresses 312516 to 312531. Then, the remainder counter of the class C is counted down from 1 to 0, and the valid bit of the second frame of the pointer management information of the class C is cleared to “0”.
By managing the write pointer and the read pointer in units of frames (packets) in this way, it becomes possible to refer to the header address of the frame written at any address of the memory bank, compare the pointer value thereof and the write address of a newly received frame, carrying out the priority processing frame by frame, and thus realize effective utilization of the memory.
While the invention has been described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that numerous modifications could be made thereto by those techniques in the art without departing from the basic concept and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-255950 | Sep 2006 | JP | national |
