Patent Application
20080064355
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
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While the mobile station 16 is associated with the base station 14, the mobile station 16 must maintain some level of frequency synchronization with the base station 14. Typically, the mobile station 16 will attempt to synchronize to a signal received from the base station 14. In accordance with the GSM cellular standard, for example, a mobile station is required to maintain a frequency accuracy of 0.1 parts-per-million (ppm) with respect to a signal received from an associated base station. Other wireless standards may have different requirements. Techniques for correcting the frequency of an internally generated signal, based on a received signal, are needed that are capable of satisfying such frequency accuracy requirements.
The sampler 34 samples the baseband signal output by the mixer 32 to generate a digital representation thereof. As shown, in at least one embodiment, the reference signal output by the VCXO 42 is used to clock the sampler 34. The reference signal may also be used to clock other circuits and components within the corresponding device or system. The digital samples generated by the sampler 34 are delivered to the input of the digital baseband receiver 36 which digitally processes the samples to extract communication information from them. This extracted information may then be directed to, for example, a user interface or other destination.
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To adjust the frequency of the LO signal, the controller 38 has two options. In a first option, the controller 38 may send a correction signal to the fractional-N synthesizer 48 that will cause the synthesizer 48 to change the non-integer multiplier it is using to generate the LO signal. In another possible option, the controller 38 may deliver a correction signal to the VCXO 42 to change the frequency of the reference signal generated thereby. Any change in the frequency of the reference signal will translate to a change in the frequency of the LO signal. Because the VCXO 42 requires an analog input signal, a D/A converter 40 may be used to convert the digital control signal output by the controller 38 to analog.
The fractional-N synthesizer 48 is capable of adjusting the frequency of the LO signal to a relatively high degree of accuracy. Frequency correction commands sent to the VCXO 42, on the other hand, can result in a much higher level of frequency error. Error levels of up to 30% (or more) overshoot or undershoot in the commanded frequency change are experienced when correction messages are sent to some VCXOs. Therefore, if a relatively large frequency offset is detected, and the VCXO is used to correct for the offset, the resultant frequency error after correction may still be far outside the frequency accuracy requirements of the system (e.g., 0.1 ppm in GSM, etc.). In one possible approach to address this problem, all frequency corrections may be performed using the more accurate fractional-N synthesizer 48. However, as discussed previously, in some embodiments, the VCXO 42 may also provide the clock signal for the sampling function (and possibly other elements) within the corresponding system. Therefore, exclusive use of fractional-N corrections can allow timing errors to accumulate in the system. In accordance with one aspect of the present invention, techniques are provided that are capable of performing frequency correction within a system in a manner that meets prescribed frequency accuracy requirements while also reducing the accumulation of time drift errors in the system.
In at least one embodiment of the invention, when the controller 38 receives a new frequency offset estimate, the controller 38 will immediately send a correction signal to the fractional-N synthesizer 48 in order to correct for the entire offset. Because the fractional-N synthesizer 48 is relatively accurate, the LO frequency will usually have relatively little frequency error after the correction is made and the frequency accuracy requirements of the corresponding wireless standard, if any, will most likely be satisfied. After this initial correction is made using the fractional-N synthesizer 48, the correction may be slowly transferred from the fractional-N synthesizer 48 to the VCXO 42 over time. That is, instead of initially making a large correction to the frequency of the VCXO 42 to correct for the frequency offset, a large correction is first made to the fractional-N synthesizer 48 and then this correction is transferred to the VCXO 42 in small amounts (Δf) over time. For example, suppose a relatively large frequency offset of 600 Hz is estimated at a particular time (e.g., just after a handoff operation has occurred). A 600 Hz correction can then be made to the LO frequency using the fractional-N synthesizer. The correction can then be transferred from the fractional-N synthesizer 48 to the VCXO 42, at fixed intervals, in 30 Hz increments (for example).
When the controller 38 transfers correction from the fractional-N synthesizer 48 to the VCXO 42, it may send a first correction signal to the VCXO 42 to achieve a frequency change of Δf and a second correction signal to the fractional-N synthesizer 48 to achieve a frequency change of −Δf (or vice versa). In at least one embodiment of the invention, the intervals at which the controller 38 causes small amounts of correction to be transferred to the VCXO 42 are the intervals at which frequency offset estimates are made. For example, in one possible system, a frequency offset may be estimated once every M (e.g., 16) received frames. In this system, the transfer of correction may also be made once every M frames. In this manner, every time a transfer is made, there will be another frequency offset estimation (and corresponding correction) performed before the next transfer is made.
In at least one embodiment of the present invention, the small amount of correction (Δf) that is transferred from the fractional-N synthesizer 48 to the VCXO 42 may be selected in a manner that is designed to meet a frequency accuracy requirement of a corresponding system, assuming a worst case correction error in the VCXO 42. For example, in one possible implementation, it may be determined that 10 Hz of frequency error is an acceptable amount that will not cause a receiver to violate a corresponding frequency accuracy requirement (e.g., 0.1 ppm, etc.). It may also be known that the worst case frequency change error of a VCXO being used in the system is +/−30%. The amount of the small correction Δf may therefore be set to 10 Hz/0.3=33 Hz or, rounded down, 30 Hz. This number may also be further reduced to provide additional assurance of frequency accuracy.
In one possible approach, the small transfers of correction from the fractional-N to the VCXO are performed until the original correction made to the fractional-N synthesizer has been fully transferred. If additional corrections are made using the fractional-N synthesizer after the initial correction, the small transfers of correction may continue until the sum of all corrections made using the fractional-N synthesizer have been transferred to the VCXO. Some of these corrections may be frequency increases and some may be frequency decreases. In at least one embodiment, the frequency change caused by the VCXO is not allowed to exceed Δf (either an increase or a decrease) at any one transfer. The amount of correction may be less than Δf, however, when, for example, there is less than Δf of accumulated correction to transfer.
After the fractional-N synthesizer correction has been made, some of the correction may be transferred from the fractional-N synthesizer to the VCXO (block 58). For example, in one approach, a small amount of correction Δf may be transferred from the fractional-N synthesizer to the VCXO, if such a transfer is warranted. Such a transfer may be warranted if, for example, the magnitude of the accumulated amount of correction that was performed by the local fractional-N synthesizer, and that has yet to be transferred to the VCXO, is greater than Δf. The accumulated amount of correction may be the sum of all of the corrections (both positive and negative) done by the fractional-N synthesizer since, for example, initiation. If the magnitude of the accumulated, untransferred correction of the fractional-N synthesizer is less than Δf but more than zero, than that specific amount may be transferred to the VCXO in block 58. The transfer may be a frequency increase or a decrease.
In at least one embodiment, a transfer of correction from the fractional-N to the VCXO may be made whenever the accumulated, untransferred correction of the fractional-N synthesizer is non-zero. A memory location may be allocated to keep track of the amount of accumulated, untransferred correction of the fractional-N synthesizer. In at least one embodiment, the transfer of correction to the VCXO is performed just after the initial correction made in the fractional-N synthesizer (in block 56). As described previously, a transfer of correction of Δf from the fractional-N to the VCXO may be made by changing the frequency of the locally generated signal by +Δf using the VCXO and changing the frequency of the locally generated signal by −Δf using the fractional-N synthesizer (or vice versa). In one approach, blocks 56 and 58 may be effected together by, for example, first changing the frequency of the locally generated signal using the fractional-N by [estimated offset −Δf] and then changing the frequency using the VCXO by +Δf (or vice versa). After the transfer of Δf of correction from the fractional-N synthesizer to the VCXO, the method 50 may return to block 54 and again wait for a frequency offset estimate to be obtained (block 54). When the estimate is received, the corrections may again be performed as described above.
In at least one implementation, the above-described techniques may be used to allow a less expensive voltage controlled crystal oscillator (VCXO) to be used than may previously have been possible, thereby reducing implementation costs. As is known, less expensive oscillators often display higher frequency correction error than do higher cost oscillators. By using the inventive techniques, many of the problems associated with this higher correction error may be overcome. Use of the inventive techniques may, in some cases, increase the amount of time that will elapse before oscillator-caused timing errors are corrected, thus allowing some drift to occur in the sampling clock. However, in some embodiments, this small amount of drift will typically be corrected within the time tracking loop of the digital baseband receiver 36. Although described above in connection with VCXOs, it should be appreciated that aspects of the invention may also be implemented with other types of voltage controlled oscillator (VCO).
In the embodiments described above, the inventive techniques are implemented within communications-based applications. It should be appreciated that aspects of the invention may also be used within non-communications applications to correct the frequencies of locally generated signals. That is, features of the invention may be used whenever an oscillator having a lower frequency correction accuracy is being used to drive a fractional-N synthesizer having a higher frequency correction accuracy.
When implemented within communication systems, the techniques and structures of the present invention may be implemented in any of a variety of different forms. For example, features of the invention may be embodied within cellular telephones and other handheld wireless communicators; laptop, palmtop, desktop, and tablet computers having wireless capability; personal digital assistants (PDAS) having wireless capability; pagers; satellite communicators; cameras having wireless capability; audio/video devices having wireless capability; network interface cards (NICs) and other network interface structures; integrated circuits; as instructions and/or data structures stored on machine readable media; and/or in other formats. Examples of different types of machine readable media that may be used include floppy diskettes, hard disks, optical disks, compact disc read only memories (CD-ROMs), digital video disks (DVDs), Blu-ray disks, magneto-optical disks, read only memories (ROMs), random access memories (RAMs), erasable programmable ROMs (EPROMs), electrically erasable programmable ROMs (EEPROMs), magnetic or optical cards, flash memory, and/or other types of media suitable for storing electronic instructions or data. As used herein, the term “logic” may include, by way of example, software or hardware and/or combinations of software and hardware.
It should be appreciated that the individual blocks illustrated in the block diagrams herein may be functional in nature and do not necessarily correspond to discrete hardware elements. For example, in at least one embodiment, two or more of the blocks in a block diagram may be implemented in software within a single digital processing device. The digital processing device may include, for example, a general purpose microprocessor, a digital signal processor (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and/or others, including combinations of the above. Hardware, software, firmware, and hybrid implementations may be used.
In the foregoing detailed description, various features of the invention are grouped together in one or more individual embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects may lie in less than all features of each disclosed embodiment.
Although the present invention has been described in conjunction with certain embodiments, it is to be understood that modifications and variations may be resorted to without departing from the spirit and scope of the invention as those skilled in the art readily understand. Such modifications and variations are considered to be within the purview and scope of the invention and the appended claims.
