Method and apparatus for encoding and decoding data

Abstract

A base model matrix is defined for the largest code length of each code rate. The set of shifts {p(i,j)} in the base model matrix are used to determine the shift sizes for all other code lengths of the same code rate. Shift sizes {p(f; i, j)} for a code size corresponding to expansion factor zf are derived from {p(i,j)} by scaling p(i,j) proportionally, and a model matrix defined by {p(f,i,j)} is used to determine the parity-check bits for the f-th code.

Description

FIELD OF THE INVENTION

The present invention relates generally to encoding and decoding data and in particular, to a method and apparatus for encoding and decoding data utilizing low-density parity-check (LDPC) codes.

BACKGROUND OF THE INVENTION

A low-density parity-check (LDPC) code is a linear block code specified by a parity-check matrix H. In general, an LDPC code is defined over a Galois Field GF(q), q≧2. If q=2, the code is a binary code. All linear block codes can be described as the product of a k-bit information vector s_l×k with a code generator matrix G_k×n to produce an n-bit codeword x_l×n, where the code rate is r=k/n. The codeword x is transmitted through a noisy channel, and the received signal vector y is passed to the decoder to estimate the information vector s_l×k.

Given an n-dimensional space, the rows of G span the k-dimensional codeword subspace C, and the rows of the parity-check matrix H_m×n span the m-dimensional dual space C^⊥, where m=n−k. Since x=sG and GH^T=0, it follows that xH^T=0 for all codewords in subspace C, where “T” (or “T”) denotes matrix transpose. In the discussion of LDPC codes, this is generally written as Hx^T=0^T,  (1) where 0 is a row vector of all zeros, and the codeword x=[s p]=[s₀, s₁, . . . , s_k−1, p₀, p₁, . . . , p_m−1], where p₀, . . . , p_m−1 are the parity-check bits and s₀, . . . , s_k−1 are the systematic bits, equal to the information bits within the information block.

For an LDPC code the density of non-zero entries in H is low, i.e., there are only a small percentage of 1's in H, allowing better error-correcting performance and simpler decoding than using a dense H. A parity-check matrix can be also described by a bipartite graph. The bipartite graph is not only a graphic description of the code but also a model for the decoder. In the bipartite graph, a codeword bit (therefore each column of H) is represented by a variable node on the left, and each parity-check equation (therefore each row of H) is represented by a check node on the right. Each variable node corresponds to a column of H and each check node corresponds to a row of H, with “variable node” and “column” of H referred to interchangeably, as are “check node” and “row” of H. The variable nodes are only connected to check nodes, and the check nodes are only connected to variable nodes. For a code with n codeword bits and m parity bits, variable node v_j is connected to check node c_i by an edge if codeword bit j participates in check equation i, i=0, 1, . . . , m−1, j=0, 1, . . . , n−1. In other words, variable node j is connected to check node i if entry h_ij of the parity-check matrix H is 1. Mirroring Equation (1), the variable nodes represent a valid codeword if all check nodes have even parity.

An example is shown below to illustrate the relationship between the parity-check matrix, the parity-check equations, and the bipartite graph. Let an n=12, rate-½ code be defined by $\begin{array}{cc}H=\underset{n}{\underbrace{\left[\begin{array}{cccccccccccc}1& 0& 1& 0& 0& 0& 1& 1& 0& 0& 0& 0\\ 0& 1& 0& 0& 1& 0& 0& 1& 1& 0& 0& 0\\ 0& 0& 1& 0& 0& 1& 1& 0& 1& 1& 0& 0\\ 1& 0& 0& 1& 0& 0& 0& 0& 0& 1& 1& 0\\ 0& 1& 0& 0& 1& 0& 0& 0& 0& 0& 1& 1\\ 0& 0& 0& 1& 0& 1& 1& 0& 0& 0& 0& 1\end{array}\right]\}}}m,& \left(2\right)\end{array}$ with the left side portion corresponding to k (=6) information bits s, the right side portion corresponding to m (=6) parity bits p. Applying (1), the H in (2) defines 6 parity-check equations as follows: $\begin{array}{cc}\{\begin{array}{c}{x}_0+x_2+x_6+x_7=0\\ x_1+x_4+x_7+x_8=0\\ x_2+x_5+x_6+x_8+x_9=0\\ x_0+x_3+x_9+x_{10}=0\\ x_1+x_4+x_{10}+x_{11}=0\\ x_3+x_5+x_6+x_{11}=0\end{array}.& \left(3\right)\end{array}$ H also has the corresponding bipartite graph shown in FIG. 1.

A bipartite graph of a good finite length LDPC code inevitably has cycles. A cycle of length 2d (denoted as cycle-2d) is a path of 2d edges which passes through d variable nodes and d check nodes and connects each node to itself without repeating any edge. Short cycles, especially cycle-4, degrade the performance of an iterative decoder and are normally avoided in the code design.

When the code size becomes large, it is difficult to encode and decode a randomly constructed LDPC code. Instead of directly building a large m×n pseudo-random H matrix, a structured LDPC design starts with a small m_b×n_b base matrix H_b, makes z copies of H_b, and interconnects the z copies to form a large m×n H matrix, where m=m_b×z, n=n_b×z. Using the matrix representation, to build H from H_b each 1 in H_b is replaced by a z×z permutation submatrix, and each 0 in H_b is replaced by a z×z all-zero submatrix. It has been shown that the permutation can be very simple without compromising performance. For instance, a simple circular right shift, where the permutation submatrix is obtained by circularly right shifting the columns of an identity matrix by a given amount, can be used without degrading decoding performance. Since circular left shift (x mod z) times is equivalent to circular right shift ((z−x) mod z) times, this text only discusses circular right shift and refers to it as a circular shift for brevity. With this constraint, each H matrix can be uniquely represented by an m_b×n_b model matrix H_bm, which is obtained by replacing each h_ij=0 in H_b by p(i,j)=−1 to denote a z×z all-zero matrix, and replacing each h_i,j=1 in H_b by a circular shift size p(ij)≧0.

Thus instead of using the expanded matrix H, a code is uniquely defined by the model matrix H_bm. Both encoding and decoding can be performed based on a much smaller m_b×n_b H_bm and vectors of bits, with each vector having size z.

This procedure essentially maps each edge of H_b to a vector edge of size z in H (represented by p(i,j) of H_bm), each variable node of H_b to a vector variable node of length z in H (corresponding to a column of H_bm), and each check node of H_b to a vector check node of length z in H (corresponding to a row of H_bm). In a structured design, the randomness is built in H through two stages: (a) the pseudo-random base matrix H_b; (b) the pseudo-random shift of the edges within each vector edge. Storage and processing complexity of a structured design are low because both stages of randomization are very simple.

Frequently a system such as that defined in the IEEE 802.16 standard is required to provide error-correcting codes for a family of codes of size (n_f, k_f), where all the codes within the family have the same code rate R=k_f/n_f and the code size scaled from a base size, n_f=z_f×n_b, k_f=z_f×k_b, f=0, 1, . . . , f_max, where (f_max+1) is the total number of members in the code family, and z_f is the expansion factor for the f-th code in the family. For these systems, it is possible to derive codes for all (n_f, k_f) from one base matrix H_b and a set of appropriate z_f. Let p(f, i, j) be the shift size of the vector edge located at position (i, j) within the f-th model matrix H_bm(f) of expansion factor z_f. Thus the set of shift sizes {p(f, i, j)} and the model matrix H_bm(f) can be referred to interchangeably.

However, it is not clear how to define shift sizes p(f, i, j) for each H_bm(f). One way to define a family of codes is to search for the base matrix H_b and/or p(f, i, j), 0≦i≦m−1, 0≦j≦n−1, independently for all given f However, this approach requires that H_b and/or p(f i, j), 0≦i≦m−1, 0≦j≦n−1, be specified and stored for all f.

Since H_b defines the basic structure and message interconnection of the LDPC decoder, it would be preferred to reuse H_b for all codes in a family. When the same H_b is shared by all codes in a family,

• • Shift size p(f, i, j)=−1 when entry (i, j) of H_b is 0. Shift size p(f, i, j)=−1 is used to denote a z_f×z_f all-zero submatrix that is used to replace entry (i, j) of model matrix H_bm(f) in expanding to the binary parity-check matrix H(f). If entry (i, j) of H_b is 0, p(f, i, j) is the same for any f, i.e., p(f, i, j)≡−1.
  • Shift size p(f, i, j)≧0 when entry (i, j) of H_b is 1. Shift size p(f, i, j)≧0 is used to denote a z_f×z_f identity submatrix circular right shifted by p(f, i, j) columns. The submatrix is used to replace entry (i, j) of model matrix H_bm(f) in expanding to the binary parity-check matrix H(f). The value of p(f, i, j) may be different for different f, i.e., entry (i, j) of H_bm(f) may be different for different f.

As to the value of non-negative p(f, i, j), it has been proposed to use p(f, i, j)=p(i, j) mod z_f for any z_f, where the set of shift sizes {p(i, j)} is the same for all z_f. Thus only one set of {p(i, j)} needs to be specified, and it potentially reduces the complexity of implementing codes of different z_f. However, due to the effect of the modulo operation, a set of {p(i, j)} designed to avoid bad cycle patterns for one z_f may cause a large number of cycles and low weight codewords for another z_f, resulting in degraded error-correcting performance for some (n_f, k_f).

Therefore, there is a need for a method to derive shift sizes {p(f, i, j)} from one set of {p(i, j)} while maintaining the desired code properties for all code sizes (n_f, k_f).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the bipartite graph of an (12, 6) H matrix.

FIG. 2 is a block diagram of an encoder.

FIG. 3 is a block diagram of a decoder.

FIG. 4 is a flow chart showing the operation of the encoder of FIG. 2.

FIG. 5 is a flow chart showing the operation of the decoder of FIG. 3.

DETAILED DESCRIPTION OF THE DRAWINGS

To address the above-mentioned need, a base model matrix is defined for the largest code length of each code rate. The set of shifts {p(i, j)} in the base model matrix are used to determine the shift sizes for all other code lengths of the same code rate. Shift sizes {p(f, i, j)} for a code size corresponding to expansion factor z_f are derived from {p(i, j)} by scaling p(i, j) proportionally, and a model matrix defined by {p(f, i, j)} is used to determine the parity-check bits for the f-th code.

The present invention encompasses a method for operating a transmitter that generates parity-check bits based on an information block. The method comprises the steps of defining a base model matrix having a set of shift sizes p(i, j) for a largest code length, and determining shift sizes p(f,i,j) for all other code lengths based on the set of shift sizes p(i,j), where f is an index of code lengths, p(f, i, j)=F(p(i, j), z₀/z_f), z₀ is an expansion factor of the largest code length, z_f is an expansion factor of the f-th code length. An information block is received and a model matrix is used to determine parity-check bits. The model matrix is defined by p(f,i,j).

The present invention additionally encompasses an apparatus comprising storage means for storing a base model matrix having a set of shift sizes p(i,j) for a largest code length. The apparatus additionally comprises a microprocessor receiving an information block s=(s₀, . . . , s_kf−1) and the base model matrix. The microprocessor determines shift sizes p(f,i,j) for all other code lengths based on the set of shift sizes p(i,j), where f is an index of code lengths, p(f, i, j)=F(p(i, j), z₀/z_f), z₀ is the expansion factor of a largest code length, z_f is the expansion factor of the f-th code length. The microprocessor outputs parity-check bits based on a model matrix defined by p(f,i,j) and an information block s=(s₀, . . . , s_kf−1).

The present invention additionally encompasses a method for operating a receiver that estimates an information block s=(s₀, . . . , s_kf−1). The method comprises the steps of receiving a signal vector, defining a base model matrix having a set of shift sizes p(i,j) for a largest code length, and determining shift sizes p(f,i,j) for all other code lengths based on the set of shift sizes p(i,j), where f is an index of code lengths, p(f, i, j)=F(p(i, j), z₀/z_f), z₀ is the expansion factor of a largest code length, z_f is the expansion factor of the f-th code length. The information block s=(s₀, . . . , s_kf−1) is then estimated based on a model matrix defined by p(f,i,j) and the received signal vector.

Finally, the present invention encompasses an apparatus comprising storage means for storing a base model matrix having a set of shift sizes p(i, j) for a largest code length. The apparatus additionally comprises a decoder receiving a signal vector and determining shift sizes p(f,i,j) for all other code lengths based on the set of shift sizes p(i,j), where f is an index of code lengths, p(f, i, j)=F(p(i, j), z₀/z_f), z₀ is the expansion factor of a largest code length, z_f is the expansion factor of the f-th code length. The decoder outputs an estimate for an information block s=(s₀, . . . , s_kf−1) based on a model matrix defined by p(f,i,j) and the received signal vector.

It has been shown that the properties of an expanded matrix H are closely related to the properties of the base matrix H_b and the shift sizes p(i, j). Certain undesirable patterns of the shift sizes p(i, j) would preserve the cycles and codeword patterns of H_b and repeat them multiple times in the expanded matrix H due to the quasi-cyclic nature of the code design, leading to unacceptable error-correcting performance.

Since low weight codewords contain short cycles if H_b does not have any weight-1 column, it is sufficient to make sure that short cycles are broken for all code sizes (n_f, k_f) of interest in order to achieve good decoding performance.

It is found that a cycle of H_b is duplicated in the expanded matrix if the following condition is satisfied. If 2c edges form a cycle of length 2c in base matrix H_b, then the corresponding 2c vector edges form z cycles of length 2c in the expanded matrix H if and only if $\begin{array}{cc}\underset{j=0,\dots ,c-1}{\sum _{i=2j}}p\left(i\right)=\underset{j=0,\dots ,c-1}{\sum _{i=2j+1}}p\left(i\right)\left(\mathrm{mod}z\right),p\left(i\right)\ge 0& \left(4\right)\end{array}$ where z is the expansion factor, p(i) is the circular shift size of edge i in the model matrix H_bm, and edges 0, 1, 2, . . . , 2c−1 (in this order) form a cycle in H_b.

While a fixed set of shift sizes {p(i, j)} that avoids satisfying Equation (4) for one z_f value may in fact satisfy Equation (4) for another z_f value, the linearity of Equation (4) shows that one may avoid satisfying it for all z_f if {p(i, j)} scales in proportion to z_f.

Suppose one set of shift sizes {p(i, j)} is to be used to expand a given base matrix H_b for two expansion factors z₀ and z₁, α=z₀/z₁>1. Assume that the shift size set {p(i, j)}≡{p(0, i, j)} avoids cycles of length 2c for expansion factor z₀, $\begin{array}{cc}\underset{j=0,\dots ,c-1}{\sum _{i=2j}}p\left(i\right)\ne \underset{j=0,\dots ,c-1}{\sum _{i=2j+1}}p\left(i\right)\left(\mathrm{mod}{z}_0\right),\mathrm{then}& \left(5\right)\\ \underset{j=0,\dots ,c-1}{\sum _{i=2j}}\frac{p\left(i\right)}{\alpha }\ne \underset{j=0,\dots ,c-1}{\sum _{i=2j+1}}\frac{p\left(i\right)}{\alpha }\left(\mathrm{mod}{z}_1\right),& \left(6\right)\end{array}$ where p(i) is the circular shift size of edge i in the model matrix H_bm(0), and edges 0, 1, 2, . . . , 2c-1 (in this order) form a cycle in H_b. Equation (6) indicates that if the set of scaled shift sizes {p(i, j)/α} are used for expansion factor z₁ then the H matrix expanded from z₁ would avoid the cycles of length 2c as well. Since 2c can be any cycle length, using the scaled shift sizes {p(i, j)/α} would avoid all cycle types for z₁ that are avoided by set {p(i, j)} for z₀.

The discussions above ignored the limitation that the shift sizes after scaling still have to be integers. For example, either the flooring function └x┘ (which is the largest integer smaller than or equal to x), the ceiling function ┌x┐ (which is the smallest integer larger than or equal to x), or the rounding function [x] (which is the integer that differs from x the least), has to be performed on all p(i,j)/α to obtain an integer. In general, given the shift sizes p(i, j)≡p(0, i, j) for z₀, the shift sizes for z₁ can be derived as a function F(.) of p(i, j) and α, p(1, i, j)=F(p(i, j), α)=F(p(i, j), z₀/z₁).  (7)

For example, if the rounding function is used on top of (6), and the shift sizes designed for z₀ is p(i, j), then the set of shift sizes applied to z₁ is $\begin{array}{cc}p\left(1,i,j\right)=\{\begin{array}{cc}p\left(i,j\right),& p\left(i,j\right)\le 0\\ \left[\frac{p\left(i,j\right)z_1}{z_0}\right]=\left[\frac{p\left(i,j\right)}{\alpha }\right],& p\left(i,j\right)>0\end{array}.& \left(8\right)\end{array}$

Although normally all positive p(i, j) would be scaled, the scaling such as (8) may be applied to only a subset of {p(i, j)}. For example, those that are not involved in any cycles do not have to be scaled, e.g., the edges of the weight-1 columns of H_b if they exist. Depending on the definition of the function F(.) and if the scaling is applied to all non-negative p(i, j), the base matrix of H_bm(0) and H_bm(1) may or may not be the same.

The analysis above is readily applied to finding p(f, i, j) if the system needs more than two expansion factors. In this case, a mother model matrix (also called a base model matrix) H_bm(0) having a set of shift sizes p(0, i, j) for the largest code length is defined, from which the model matrix H_bm(f) having shift sizes p(f, i, j) for the f-th code family member is derived, f=1, . . . , f_max. Assuming z₀=max(z_f) and p(0, i, j)=p(i, j), α_f=z₀/z_f should be used in expressions like (8) in deriving p(f, i, j) from p(i, j), so that the same cycles of the base matrix are avoided for the entire range of z_f. In particular, assuming all p(i, j) are found, p(f, i, j)=F(p(i, j), α_f)=F(p(i, j), z₀/z_f).  (9) in general is used to derive p(f,i,j) from p(i,j). Further, as an example, the function F(.) may be defined as $\begin{array}{cc}p\left(f,i,j\right)=\{\begin{array}{cc}p\left(i,j\right),& p\left(i,j\right)\le 0\\ \left[\frac{p\left(i,j\right)z_f}{z_0}\right]=\left[\frac{p\left(i,j\right)}{{\alpha }_f}\right],& p\left(i,j\right)>0\end{array},& \left(10\right)\end{array}$ assming z₀=max(z_f) and using the rounding function, corresponding to (8). Similarly, the flooring function └x┘ or the ceiling function ┌x┐ can be used in place of the rounding function [x].

Note that the design procedure above applies to any type of base matrix H_b. For example, it can be applied to an H_b composed of two portions, H_b=└(H_b1)_mb×kb¦(H_b2)_mb×mb┘,  (11) whose deterministic portion H_b2 can be further partitioned into two sections, where vector h_b has odd weight w_h>2, and H′_b2 has a deterministic staircase structure: $\begin{array}{cc}\begin{array}{c}{H}_{\mathrm{b2}}=\left[h_b|H_{\mathrm{b2}}^{\prime }\right]\\ =\left[\begin{array}{cccccc}{h}_b\left(0\right)& 1& & & & \\ h_b\left(1\right)& 1& 1& & 0& \\ ⋮& & 1& ⋰& & \\ ⋮& & & ⋰& 1& \\ ⋮& & 0& & 1& 1\\ h_b\left(m_b-1\right)& & & & & 1\end{array}\right].\end{array}& \left(12\right)\end{array}$ In other words, H′_b2 comprise matrix elements for row i, column j equal to $H_{\mathrm{b2}}^{\prime }\left(i,j\right)=\{\begin{array}{cc}1,& i=j\mathrm{or}i=j+1;\\ 0,& \mathrm{otherwise}.\end{array}$ Encoder Implementation for a Family of Codes

Since all members of the family designed above are derived from a mother model matrix H_bm≡H_bm(0), thus all having the same structure, the encoding process for each member of the family is similar. A portion of or the entire model matrix could be stored and interpreted as instructions to a barrel shifter to perform circular shifts of the grouped information sequence.

Since all members of the family are derived from a mother model matrix H_bm≡H_bm(0), the implementation of an encoder for the family only requires that the mother matrix be stored. Assuming the rounding function [x] is used, for the f-th member of the family, the circular shifts p(i,j) of the mother model matrix are replaced by circular shifts [p(i,j)/(z₀/z_f)] for all p(i,j)>0, where z_f indicates the expansion factor of the f-th member of the family that is being encoded. A straightforward implementation of this is to store the values α_f⁻¹=(z₀/z_f)⁻¹ (or α_f=z₀/z_f for each member of the family in a read-only memory and compute the values [p(i,j)/(z₀/z_f)], p(i,j)>0, on-the-fly using a multiplier. Alternatively, shift size sets {p(f, i, j)}, f=0, 1, . . . , f_max, for each member of the family may be precomputed using (8) (or more generally, (7)), and stored in the read-only memory.

The barrel shifter can be modified to provide circular shifts for all word sizes z_f corresponding to the family members. Whereas this barrel shifter modification will complicate the barrel shifter logic and necessitate slower clock rates, an alternative requiring extra logic resources is to instantiate a different barrel shifter for each word size z_f.

FIG. 2 is a block diagram of encoder 200. As shown, encoder 200 comprises microprocessor 201, lookup table 203, and logic circuitry 205 to determine an expansion factor z_f. Although shown existing external to one another, one of ordinary skill in the art will recognize that the functionality of logic circuitry 205 may be implemented within microprocessor 201. Microprocessor 201 preferably comprises a digital signal processor (DSP), such as, but not limited to MSC8300 and DSP56300 DSPs. Additionally, lookup table 203 serves as storage means to store a matrix, and comprises read-only memory; however, one of ordinary skill in the art will recognize that other forms of memory (e.g., random-access memory, magnetic storage memory, etc.) may be utilized as well. In a second embodiment, the functionality of the microprocessor 201, lookup table 203, and logic circuitry 205 can be incorporated into an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). In particular, the lookup table 203 can be implemented in a form of memory corresponding to the existence or non-existence of signal paths in a circuit.

As discussed above, encoded data generally takes the form of a plurality of parity-check bits in addition to the systematic bits, where together the parity-check and systematic bits form a codeword x. In the first embodiment of the present invention, a base model matrix H_bm is stored in lookup table 203, and is accessed by microprocessor 201 to find the parity-check bits. In particular, microprocessor 201 determines appropriate values for the parity-check bits p=(p₀, . . . , p_mf−1) based on the information block s=(s₀, . . . , s_kf−1), the expansion factor z_f, and the base model matrix H_bm. The expansion factor z_f is determined by logic 205 using z_f=k_f/k_b=n_f/n_b, and is used to group bits into length-z_f vectors as well as finding α_f=z₀/z_f. After the parity-check bits are found, they and the systematic bits are then passed to a transmitter and transmitted to a receiver.

FIG. 3 is a block diagram of decoder 300 in accordance with one embodiment of the present invention. As shown, decoder 300 comprises microprocessor 301, lookup table 303, and logic circuitry 305 to determine an expansion factor z_f. In a first embodiment of the present invention, microprocessor 301 comprises a digital signal processor (DSP), such as, but not limited to MSC8300 and DSP56300 DSPs. Additionally, lookup table 303 acts as storage means for storing the base model matrix H_bm, and comprises read-only memory. However, one of ordinary skill in the art will recognize that other forms of memory (e.g., random-access memory, magnetic storage memory, etc.) may be utilized as well. In a second embodiment, the functionality of the microprocessor 301 and the lookup table 303 can be incorporated into an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). In particular, the lookup table 303 can be implemented in a form of memory corresponding to the existence or non-existence of signal paths in a circuit.

The received signal vector (received via a receiver) y=(y₀, . . . , y_nf−1) corresponds to the codeword x transmitted through a noisy channel, where the encoded data x, as discussed above, is a codeword vector of the f-th member of the code family. In the first embodiment of the present invention, a base model matrix H_bm is stored in lookup table 303, and is accessed by microprocessor 301 to decode y and estimate the information block s=(s₀, . . . , s_kf−1). In particular, microprocessor 301 estimates the information block (s₀, . . . , s_kf−1) based on the received signal vector y=(y₀, . . . , y_nf−1) and the base model matrix H_bm. The expansion factor z_f is determined by logic 305 using z_f=k_f/k_b=n_f/n_b, and is used to group received signals and bits into length-z_f vectors as well as finding α_f=z₀/z_f.

FIG. 4 is a flow chart showing the operation of encoder 200, and in particular, microprocessor 201. The logic flow begins at step 401 where an information block (s₀, . . . , s_kf−1) is received by microprocessor 201. At step 403, values of parity-check bits are determined based on the information block and H_bm(f), where H_bm(f) is uniquely defined by {p(f, i, j)}. In particular, the shift size set {p(i,j)} of the base model matrix H_bm is read out from memory. The microprocessor utilizes {p(i, j)} and α_f to determine {p((, i, j)}. The parity-check bits (p₀, . . . , p_mf−1) are determined by solving Equation (1). At step 405 the information block and the parity-check bits are transmitted through a channel.

FIG. 5 is a flow chart showing the operation of decoder 300, and in particular, microprocessor 301. The logic flow begins at step 501 where the received signal vector y=(y₀, . . . , y_nf−1) is received. At step 503, estimates of the information block s=(s₀, . . . , s_kf−1) are determined based on H_bm(f), where H_bm(f) is uniquely defined by {p(f, i, j)}. In particular, the shift size set {p(i,j)} of the base model matrix H_bm is read out from memory. The microprocessor utilizes {p(i, j)} and α_f to determine {p(f, i, j)}. As discussed, the microprocessor processes the received signal vector in accordance with the shift sizes {p(f, i, j)} (or equivalently, H_bm(f) to obtain estimates of the information block. In a preferred embodiment, the microprocessor performs the processing according to a message-passing algorithm using the bipartite graph of the code.

While the invention has been particularly shown and described with reference to a particular embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, when the code size range is very large, e.g., α approaches z/2, it would become very difficult to find the proper shift size set {p(i, j)}. Therefore if the code size range is too large, i.e., a is large, one may use multiple sets of {p(i, j)}, each covering a range of z_f for the code family. In another example, although the discussion assumed that the mother model matrix H_bm(0), z₀=max(z_f), and p(0, i, j)=p(i, j) are used for the 0-th code family member, those skilled in the art would understand that H_bm(0), z₀, and p(i, j) may be defined for a code size not in the code family, but are used to derive the shift sizes p(f, i, j) for the code family of interest. In another example, although the discussion assumed that z₀=max(z_f), those skilled in the art would understand that a z₀ value not equal to max(z_f) may be used in shift size derivations. It is intended that such changes come within the scope of the following claims.

Claims

1. A method for operating a transmitter that generates parity-check bits based on an information block, the method comprising the steps of: defining a base model matrix having a set of shift sizes p(i, j) for a largest code length; determining shift sizes p(f, i, j) for all other code lengths based on the set of shift sizes p(i, j), where f is an index of code lengths, p(f ,i, j)=F(p(i, j),z0/zf), z0 is an expansion factor of the largest code length, zf is an expansion factor of the f-th code length; receiving the information block s=(s0, . . . , skf−1); using a model matrix defined by p(f, i, j) to determine the parity-check bits; and transmitting the parity-check bits along with the information block.

2. The method of claim 1 wherein:

3. The method of claim 1 wherein

4. The method of claim 1 wherein

5. The method of claim 1 where the parity-check bits are found based on a parity-check matrix H(f) which is expanded from a model matrix Hbm(f) defined by p(f,i,j) with expansion factor zf.

6. The method of claim 5 wherein the parity-check matrix H(f) is expanded by replacing each negative element of Hbm(f) with a zero submatrix of size z×z to produce H(f).

7. The method of claim 5 wherein H(f) is expanded by replacing each non-negative element of Hbm(f) with a non-zero permutation submatrix to produce H.

8. The method of claim 5 wherein Hbm(f) and Hbm(0) use a same base matrix Hb.

9. The method of claim 5 wherein Hbm(f) and Hbm(0) use different base matrices.

10. The method of claim 1 wherein the base model matrix is built from a base matrix comprising a section Hb1 and a section Hb2, with Hb2 comprising a first part having a column hb having an odd weight greater than 2, and a second part H′b2 comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+1, 0 elsewhere.

11. An apparatus comprising: storage means for storing a base model matrix having a set of shift sizes p(i,j) for a largest code length; and a microprocessor receiving an information block s=(s0, . . . , skf−1) and the base model matrix and determining shift sizes p(f,i,j) for all other code lengths based on the set of shift sizes p(i,j), where f is an index of code lengths, p(f, i, j)=F(p(i, j), z0/zf), z0 is the expansion factor of a largest code length, zf is the expansion factor of the f-th code length; the microprocessor outputting parity-check bits based on a model matrix defined by p(f,i,j) and an information block s=(s0, . . . , skf−1).

12. The apparatus of claim 11 wherein:

13. The apparatus of claim 11 further comprising a read-only memory having values for p(f ,i, j)=F(p(i, j), z0/zf).

14. The apparatus of claim 11 further comprising a read-only memory having values for z0/zf.

15. A method for operating a receiver that estimates an information block s=(s0, . . . , skf−1), the method comprising the steps of: receiving a signal vector; defining a base model matrix having a set of shift sizes p(i, j) for a largest code length; determining shift sizes p(f,i,j) for all other code lengths based on the set of shift sizes p(i,j), where f is an index of code lengths, p(f, i, j)=F(p(i, j), z0/zf), z0 is the expansion factor of a largest code length, zf is the expansion factor of the f-th code length; and estimating the information block s=(s0, . . . , s0, . . . , skf−1) based on a model matrix defined by p(f,i,j) and the received signal vector.

16. The method of claim 15 wherein:

17. An apparatus comprising: storage means for storing a base model matrix having a set of shift sizes p(i,j) for a largest code length; and a decoder receiving a signal vector and determining shift sizes p(f,i,j) for all other code lengths based on the set of shift sizes p(i,j), where f is an index of code lengths, p(f, i, j)=F(p(i, j), z0/zf), z0 is the expansion factor of a largest code length, zf is the expansion factor of the f-th code length; the decoder outputting an estimate for an information block s=(s0, . . . , skf−1) based on a model matrix defined by p(f,i,j) and the received signal vector.

18. The method of claim 17 wherein: