The present application relates to semi-resonant and resonant converters, in particular estimating load current for semi-resonant and resonant converters.
Resonant and semi-resonant DC-DC converters, including isolated and non-isolated topologies, are used in a variety of applications such as telecommunications, processors, etc. because of their zero-voltage (current) switching characteristic and their ability to utilize parasitic components. Among numerous topologies, the semi-resonant converter with transformer/tapped-inductor is an attractive topology for high voltage conversion ratio without isolation. Lower cost and higher efficiency are the main advantages of such converters over other solutions.
The output current of many resonant and semi-resonant DC-DC converters has a half cycle sinusodial-like shape each switching cycle. A classic example of such a sinusodial-like output current occurs in discontinuous conduction mode (DCM) in which current through the output inductor falls to zero during part of the switching period. Many resonant and semi-resonant DC-DC converters also have a variable switching frequency such that the switching period can vary from cycle to cycle. For these types of resonant and semi-resonant converters with sinusodial-like output current and variable switching frequency, it is difficult to obtain the cycle average value of the output current which is equal to the load current in semi-resonant converters. The cycle average is used for adaptive voltage positioning (AVP), phase current balancing and phase dropping/adding in multi-phase systems. Because of the sinusodial-like shape of the output current, conventional low pass filtering techniques for obtaining the cycle average value of the output current are not adequate, since very low bandwidth filters would be needed for obtaining the average value of the output current. Very low bandwidth filters add latency to the control loop and may degrade the transient performance of the converter. In addition, very low bandwidth filters yield an inaccurate total current which is obtained by summing the filtered values in each channel, especially at higher load frequency transients. Also, very low bandwidth filters are not suitable for use in peak current limit control or other control mechanisms utilizing the current information, nor are they suitable for use in current balancing/sharing control.
As such, there is a need for an improved technique for obtaining the cycle average value of output current for resonant and semi-resonant DC-DC converters having a variable switching frequency and output current having a sinusodial-like shape.
According to an embodiment of a voltage converter, the voltage converter comprises a variable switching frequency power stage, a passive circuit and a control circuit. The power stage includes a high-side switch and a first low-side switch coupled to the high-side switch at a switching node of the power stage. The passive circuit couples the switching node to an output node of the voltage converter. The control circuit is operable to control cycle-by-cycle switching of the power stage and sample current at a point between the switching node and the output node, the sampled current having a half cycle sinusodial-like shape each switching cycle. For the present switching cycle, the control circuit is operable to calculate an average of the sampled current for the immediately preceding switching cycle and estimate the average sampled current for the present switching cycle based on the average sampled current calculated for the immediately preceding switching cycle.
According to an embodiment of a method of current sensing for a voltage converter which includes a power stage having a high-side switch and a first low-side switch coupled to the high-side switch at a switching node of the power stage and a passive circuit coupling the switching node to an output node of the voltage converter, the power stage having a variable switching frequency, the method comprises: sampling current at a point between the switching node and the output node, the sampled current having a half cycle sinusodial-like shape each switching cycle; and for the present switching cycle, calculating an average of the sampled current for the immediately preceding switching cycle and estimating the average sampled current for the present switching cycle based on the average sampled current calculated for the immediately preceding switching cycle.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
Embodiments described herein obtain an accurate cycle average of sampled current of a resonant or semi-resonant DC-DC converter having a variable switching frequency. The average sampled current is estimated using information taken from a low-side sync switch or any other sense element through which the current to be sampled flows. The average sampled current for the immediately preceding switching cycle is calculated, and the average sampled current for the present switching cycle is estimated based on the average sampled current calculated for the immediately preceding switching cycle. The current estimate can be adjusted to improve accuracy. Latency is minimized to a maximum one cycle in one embodiment and even less in another embodiment. The techniques described herein are suitable for handling high frequency load transients, are easy to implement in digital/analog control, do not require digital/analog low pass filtering, provide accurate total current estimate, are suitable for current mode control schemes, are suitable for peak current limit control, are suitable for current balance control in multi-phase applications, and allow for adjusting the average current value with variable frequency operation.
A current estimator 110 included in or associated with the control circuit 106 obtains an accurate cycle average of the sampled current Isam each switching cycle. Because the voltage converter 100 has a variable switching frequency and a sampled current Isam with a half cycle sinusodial-like shape, low pass filtering to obtain the cycle average sampled current is not employed, since a very low bandwidth filter would be needed. Instead, the current estimator 110 calculates the average sampled current for the immediately preceding switching cycle [n−1] and estimates the average sampled current for the present switching cycle [n] based on the average sampled current calculated for the immediately preceding switching cycle [n−1]. The average of the sampled current Isam approximately equals the output current lo delivered to the load. The control circuit 106 can adjust the current estimate to improve accuracy as described in more detail later.
The power stage 104 of the hybrid pulse-width modulation/resonant voltage converter includes a high-side power switch Q1, and first and second low-side power switches Q2, Q3. A driver stage 112 is provided for driving the high-side power switch Q1 and the low-side power switches Q2, Q3 of the power stage 104. The driver stage 112 and the power stage 104 can be integrated on the same semiconductor die, or provided as separate dies. The power switches Q1, Q2, Q3 can be integrated on the same semiconductor die, or provided as separate dies.
The high-side power switch Q1 and the low-side power switches Q2, Q3 may be implemented as silicon or other group IV based metal-oxide-semiconductor field-effect transistors (MOSFETs), for example. Accordingly, each power switch Q1, Q2, Q3 is shown to include drain (D), source (S), and gate (G). The high-side power switch Q1, and the low-side power switches Q2, Q3 are depicted as silicon or other group IV FETs in the exemplary implementation shown by
As shown in
As further shown in
The semi-resonant/hybrid voltage converter circuit configuration shown in
During the next interval of the switching cycle, the high-side power switch Q1 is turned off, i.e., the “off time” or “Toff” as used herein, and the first and second low-side power switches Q2, Q3 are turned on, e.g. by setting HS=0, LS1=1 and LS2=1 for the gate signals of the standard MOSFETs shown in
The resonance formed between resonant capacitor Cr and leakage inductance Lr during the off time of the high-side power switch Q1 results in a resonant current (IR) flowing through the secondary winding S of the transformer 114 which charges output capacitor Co. If the off time of the high-side power switch Q1 is optimized with respect to the resonant frequency, the second low-side power switch Q2 can be turned off when its current is very small or substantially zero. The secondary current Is rises during Toff due to the secondary side current of the transformer 114 which equals IM+(N1/N2)(IM−IR), where N1 is the number of primary side winding turns and N2 is the number of secondary winding turns of the transformer 114. The point at which IR crosses IM signals to the control circuit 106 the end of the present switching cycle, so that the control circuit 106 knows when to force the voltage converter 100 into next cycle starting with dead time DT0 in which power switches Q1, Q2, Q3 are turned off.
Io=
Is
=
IQ3=IM+(N1/N2)(IM−IR)=(N/N2)(IM−IR) (1)
where denotes the average value.
The secondary current Is and the current IQ3 of the second low-side power switch Q3 both have a half cycle sinusodial-like shape for each switching cycle as shown in
The current estimator 110 included in or associated with the control circuit 106 obtains an accurate cycle average value of the secondary current Is according to the embodiment illustrated in
In both cases, the current estimator 110 includes an ADC (analog-to-digital converter) 116 for digitally sampling the measured current (Is or IQ3) and an integrator 118 for integrating the digitally sampled current values while the high-side switch Q1 is off and the first low-side switch Q2 is on. For example, the integrator 118 can be triggered by the rising edge of the signal LS1 which is applied to the gate of the first low-side power switch Q2 and which represents the beginning of Toff for the present switching cycle. The integrator 118 has a predetermined sampling rate Tclk which is set so that the number of samples taken each switching cycle ensures the average sampled current calculated for each switching cycle meets an accuracy threshold.
The current estimator 110 also includes a counter 120 for measuring the period of the voltage converter 100, which can vary from cycle-to-cycle. The counter 120 is reset at the rising edge of the signal HS, which is applied to the gate of the high-side power switch Q1 and represents the beginning of Ton for the present switching cycle. The final value of the counter 120 is stored by a latch 122 and used for the next switching cycle.
The current estimator 110 further includes an average calculator 124 for calculating an accurate cycle average of the sampled current Is or IQ3, both of which correspond to the output current Io. The average calculator 124 divides the integrated current from the integrator 1128 by the measured period of the switching cycle which is a function of the counter value stored in the latch 122. The ADC 116, integrator 118, counter 120, latch 122 and average calculator 124 can be implemented digitally as part of the converter control circuit 106. Operation of the current estimator 110 is described next in more detail with reference to
Tsw
m
[n−1]=Lc[n−1]*Tclk (2)
where Lc[n−1] is the last value of the counter 120 at the end of switching cycle [n−1] and Tclk is the frequency of the input clock signal to the counter 120.
At the beginning of the next switching cycle [n], the period Tswm[n−1] of the immediately preceding switching cycle [n−1] is already known. As such, the period Tswm[n−1] of the immediately preceding switching cycle [n−1] can be used as an estimate of the period Tswm[n] of the present switching cycle [n] as given by:
Tsw
m
[n]=L
c
[n−1]*Tclk (3)
The dashed line in
The integrator 118 also includes a latch for capturing the final value In of the integrator counter at the end of each switching cycle [n−1], [n], etc., i.e. the counter value just before the beginning of the next dead time period DT0. The final value In[n−1] of the integrator counter stored in the integrator latch for the immediately preceding switching cycle [n−1] is used during the next switching cycle [n] to calculate the average sampled current Isamavg[n] for switching cycle [n] as given by:
where Lc[n−1]*Tclk is the period of the immediately preceding switching cycle [n−1] as given by equation (3).
The dashed line in
The value of the estimated average sampled current Isamavg can change from cycle-to-cycle as shown in
If, however, Ton[n] and Ton[n−1] are different, the sampled current for the present switching cycle [n] is different than the sampled current for the immediately preceding switching cycle [n−1]. For example, if Ton[n]>Ton[n−1], then the actual average current for switching cycle [n] was higher than calculated. Conversely, if Ton[n]<Ton[n−1], then the actual average current for switching cycle [n] was lower than calculated.
The control circuit 106 can determine if the high-side switch Q1 is on for a different duration of time in the present switching cycle [n] than in the immediately preceding switching cycle [n−1]. This information is known and readily available during the present switching cycle [n−1] as part of standard voltage converter control. The control circuit 106 can then adjust the average sampled current estimated for the present switching cycle [n] as a function of the difference in on-time for the high-side switch Q1 at the end of Ton time. In one embodiment, the adjusted average sampled current Isamavg_adj[n] for the present switching cycle [n] is determined as given by:
Isam
avg
_
adj
[n]=Isam
avg
[n]+Kp(Ton[n]−Ton[n−1]) (5)
According to this embodiment, the control circuit 106 adjusts the average sampled current Isamavg[n] estimated for the present switching cycle [n] as a function of the difference in on-time for the high-side switch Q1 by multiplying the difference in on-time for the high-side switch Q1 by a weighting factor Kp so as to compute an adjustment value, and adding the adjustment value to the average sampled current Isamavg[n] estimated for the present switching cycle [n]. If there is no difference or if the difference is within some predetermined margin, then Isamavg_adj[n]=Isamavg[n] and no adjustment is made. The dashed line in
If, however, Ipk[n] and Ipk[n−1] differ by a certain amount or percentage, the sampled current for the present switching cycle [n] is different than the sampled current measured for the immediately preceding switching cycle [n−1]. For example, if Ipk[n]>Ipk[n−1], then the actual average current for switching cycle [n] was higher than calculated. Conversely, if Ipk[n]<Ipk[n−1], then the actual average current for switching cycle [n] was lower than calculated.
The control circuit 106 can determine if the peak current Ipk[n] measured for the present switching cycle [n] is different than the peak current Ipk[n−1] measured for the present switching cycle [n]. This information is readily ascertainable from the sample current values generated by the integrator 118 of the current estimator 110. The control circuit 106 adjusts the average sampled current estimated for the present switching cycle [n] as a function of the difference in the peak currents. In one embodiment, the adjusted average sampled current Isamavg_adj[n] for the present switching cycle [n] is determined as given by:
Isam
avg
_
adj
[n]=Isam
avg
[n]+Kp(PhC[n]|peak−PhC[n−1]|peak) (6)
where PhC[n]|peak is the peak current measured by the ADC 116 of the current estimator 110 at approximately Toff[n]/2 for the present switching cycle [n], and PhC[n−1]|peak is the peak current measured by the ADC 116 at approximately Toff[n−1]/2 for the immediately preceding switching cycle [n−1].
According to this embodiment, the control circuit 106 adjusts the average sampled current Isamavg[n] estimated for the present switching cycle [n] as a function of the difference in measured peak current by multiplying the difference in the current peaks by a weighting factor Kp so as to compute an adjustment value, and adding the adjustment value to the average sampled current Isamavg[n] estimated for the present switching cycle [n]. If there is no difference or if the difference is within some predetermined margin, then Isamavg_adj[n]=Isamavg[n] and no adjustment is made. Other scaling techniques can be employed by the control circuit 106 to adjust the average sampled current estimated for the present switching cycle as a function of peak current.
The control circuit 106 can employ both the on-time based approach illustrated in
In general, the cycle average current Isamavg calculated by the current estimator 110 can be used by the control circuit 106 for various purposes such as adaptive voltage positioning (AVP), phase current balancing, phase adding/dropping, peak current limit, etc. These techniques are well known techniques in the voltage converter art, and therefore no further explanation is given in this regard.
As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.