Claims
- 1. In a pipeline computer system comprising a plurality of floating point instructions, a method for executing floating point instructions, said method comprising the steps of:
- a) storing a first plurality of floating point data in a primary direct mapped cache, said primary cache comprising n.sub.1 cache lines, each having a first cache line size of m.sub.1 floating point data word(s) and a first access time of t.sub.1 clock cycle(s), where m.sub.1 and t.sub.1 are both small integers greater than or equal to 1;
- b) storing a second plurality of floating point data in a secondary fully associative cache, said secondary cache comprising n.sub.2 cache lines, each having a second cache line size of m.sub.2 floating point data words and a second access time of t.sub.2 clock cycles, where n.sub.2 is a small integer, m.sub.2 is greater than m.sub.1, and t.sub.2 is a small integer greater than t.sub.1.
- c) storing a third plurality of floating point data in a tertiary cache, said tertiary cache comprising n.sub.3 cache lines, each having a third cache line size of m.sub.3 floating point data words and a third access time of t.sub.3 clock cycles, where m.sub.3 is greater than m.sub.2 and t.sub.3 is a small integer greater than t.sub.2 ;
- d) executing at least one fetching and one decoding floating point phase to fetch and decode a floating point instruction, said floating point instruction being preceded by a floating point data loading instruction to load at least one floating point data word from a selected one of said primary, secondary and tertiary cache;
- e) executing d floating point delay phases, said d floating point delay phases requiring at least t.sub.1 +t.sub.2 clock cycles; and
- f) executing at least one floating point execution phase to execute said decoded floating point instruction.
- 2. The method as set forth in claim 1, wherein,
- m.sub.1 and t.sub.1 both equal 1;
- m.sub.2 equals 64 and t.sub.2 equals 2; and
- d equals 3.
- 3. The method as set forth in claim 2, wherein n.sub.2 equals 16.
- 4. In a pipelined computer system comprising a plurality of floating point instructions, an apparatus for executing floating point instructions, said apparatus comprising:
- a) a primary direct mapped cache for storing a first plurality of floating point data in a primary direct mapped cache, said primary cache comprising n.sub.1 cache lines, each having a first cache line size of m.sub.1 floating point data word(s) and a first access time of t.sub.1 clock cycle(s), where m.sub.1 and t.sub.1 are both small integers greater than or equal to 1;
- b) a secondary fully associative cache for storing a second plurality of floating point data in a secondary fully associative cache, said secondary cache comprising n.sub.2 cache lines, each having a second cache line size of m.sub.2 floating point data words and a second access time of t.sub.2 clock cycles, where n.sub.2 is a small integer, m.sub.2 is greater than m.sub.1 and t.sub.2 is a small integer greater than t.sub.1 ;
- c) a tertiary cache for storing a third plurality of floating point data in a tertiary cache, said tertiary cache comprising n.sub.3 cache lines, each having a third cache line size of m.sub.3 floating point data words and a third access time of t.sub.3 clock cycles, where m.sub.3 is greater than m.sub.2 and t.sub.3 is a small integer greater than t.sub.2 ; and
- d) a floating point pipeline coupled to said primary, secondary, and tertiary caches for executing at least one fetching and one decoding floating point phase to fetch and decode a floating point instruction, d floating point delay phases, said d floating point delay phases requiring at least t.sub.1 +t.sub.2 clock cycles, and at least one floating point execution phase to execute said decoded floating point instruction, said floating point instruction being preceded by a floating point data loading instruction to load at least one floating point data word from a selected one of said primary, secondary and tertiary cache.
- 5. The apparatus as set forth in claim 4, wherein,
- m.sub.1 and t.sub.1 are both equal 1;
- m.sub.2 equals 64 and t.sub.2 equals 2; and
- d equals 3.
- 6. The apparatus as set forth in claim 5, wherein n.sub.2 equals 16.
- 7. A computer system comprising:
- a) a primary direct mapped cache for storing a first plurality of floating point data in a primary direct mapped cache, said primary cache comprising n.sub.1 cache lines, each having a first cache line size of m.sub.1 floating point data word(s) and a first access time of t.sub.1 clock cycle(s), where m.sub.1 and t.sub.1 are both small integers greater than or equal to 1;
- b) a secondary fully associative cache for storing a second plurality of floating point data in a secondary fully associative cache, said secondary cache comprising n.sub.2 cache lines, each having a second cache line size of m.sub.2 floating point data words and a second access time of t.sub.2 clock cycles, where n.sub.2 is a small integer, m.sub.2 is greater than m.sub.1 and t.sub.2 is a small integer greater than t.sub.1 ;
- c) a tertiary cache for storing a third plurality of floating point data in a tertiary cache, said tertiary cache comprising n.sub.3 cache lines, each having a third cache line size of m.sub.3 floating point data words and a third access time of t.sub.3 clock cycles, where m.sub.3 is greater than m.sub.2 and t.sub.3 is a small integer greater than t.sub.2 ; and
- d) a floating point pipeline coupled to said primary, secondary, and tertiary caches for executing at least one fetching and one decoding floating point phase to fetch and decode a floating point instruction, d floating point delay phases, said d floating point delay phases requiring at least t.sub.1 +t.sub.2 clock cycles, and at least one floating point execution phase to execute said decoded floating point instruction, said floating point instruction being preceded by a floating point data loading instruction to load at least one floating point data word from a selected one of said primary, secondary and tertiary cache.
- 8. The computer system as set forth in claim 7, wherein,
- m.sub.1 and t.sub.1 are both equal 1;
- m.sub.2 equals 64 and t.sub.2 equals 2; and
- d equals 3.
- 9. The computer system as set forth in claim 8, wherein n.sub.2 equals 16.
Parent Case Info
This is a continuation of application Ser. No. 07/401,021, filed Aug. 31, 1989, now abandoned.
US Referenced Citations (11)
Foreign Referenced Citations (3)
Number |
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Feb 1989 |
EPX |
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Continuations (1)
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Number |
Date |
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Parent |
401021 |
Aug 1989 |
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