Patent Application
20140174812
This disclosure relates generally to techniques for reducing far end crosstalk. Specifically, this disclosure relates to reducing far end crosstalk by introducing capacitive coupling of neighboring signal nets.
Computing devices may include a motherboard such as a printed circuit board (PCB). The motherboard may hold various components of the computing device such as a central processing unit (CPU) and memory, and may provide connections for other peripheral components. The CPU may be coupled to the motherboard via a packaging technology such as a land grid array (LGA), a pin grid array (PGA), and the like. A LGA is packaging for integrated circuits that is notable for having the pins on a socket rather than an integrated circuit that may be present in other packaging, such as in a PGA. In many packaging technologies, crosstalk is generated within the packaging. Crosstalk creates distortion in signals communicated through the channels.
The same numbers are used throughout the disclosure and the figures to reference like components and features. Numbers in the 100 series refer to features originally found in
The present disclosure relates generally to techniques for reducing crosstalk between contacts. A package configured to couple inputs/outputs (I/O's) associated with electrical components to a printed circuit board (PCB) includes a first contact, a second contact, and a third contact. In embodiments, the contacts may include additional contacts, and is not limited to three contacts. Each of the contacts is coupled to a vertical conductor, such as a microvia, that communicatively couples the contacts to electrical components disposed at various layers in the package. The second contact and the third contact experience crosstalk generated at a first vertical conductor coupled to the first contact. The crosstalk generated at the first vertical conductor is inductive. The inductive crosstalk tends to create noise in signals nets associated with the second and third contacts, respectively. For example, the second contact can be associated with a signal net that can receive inductive crosstalk from the first vertical conductor. The inductive crosstalk is reduced by forming a capacitive coupler between the first and second contact and second and third contact respectively. The capacitive coupler introduces capacitive crosstalk configured to compensate for the inductive crosstalk, and thereby reduce or cancel the inductive crosstalk generated at the first vertical conductor.
The first contact 202 is coupled to a first vertical conductor 208. The second contact 204 is coupled to a second vertical conductor 210. The third contact 206 is coupled to a third vertical conductor 212. The vertical conductors 208, 210, 212 couples the circuit components of the package 102 to signal lines of the PCB 100. The contacts 202, 204, 206 may configured in different shapes and sizes. A “vertical conductor,” as referred to herein, is a conductive element, such as a via, a socket, a pin, and the like. In some embodiments, vertical conductors 208, 210, 212 are disposed having a different orientation with respect to the term “vertical,” and is “horizontal,” “diagonal,” or among other orientations. The vertical conductor 212 can experience crosstalk that can create noise in a signal at a different vertical conductor. For example, crosstalk can be generated at the first vertical conductor 208 and received at the second vertical conductor 210 and the third vertical conductor 212, as indicated by the arrows of the dashed circle 214. In some embodiments, the crosstalk generated is based on the proximity of the first vertical conductor 208 to the either the second vertical conductor 210 or the third vertical conductor 212. The crosstalk generated at the first vertical conductor 208 is inductive crosstalk.
The package 102 can also include a capacitive coupler 216 disposed between the first contact 202, the second contact 204, and the third contact 206. The capacitive coupler 216 can be configured to reduce or cancel the inductive crosstalk generated at the first vertical conductor 208 and received at the second vertical conductor 210 and the third vertical conductor 212. The capacitive coupler 216 may include a conductive plate 218 disposed above the second contact 204. The capacitive coupler 216 can include another conductive plate 220 disposed above the third contact 206. As shown in
The crosstalk can be inductive crosstalk generated at the first vertical conductor and received at the second vertical conductor and the third vertical conductor. The inductive crosstalk can be reduced or cancelled by the capacitive coupling. In some embodiments, the capacitive coupling is a sequential coupling. In this embodiment, the method 700 includes forming a capacitive coupling from the first contact to the second contact, and forming a capacitive coupling from the second contact to the third contact. In some embodiments, the capacitive coupling is a parallel coupling. For example, the method 700 can include forming a capacitive coupling from the first contact to the second contact; and forming a capacitive coupling from the first contact to the third contact.
In some embodiments, at block 708, forming the capacitive coupling comprises forming a conductive plate disposed above the second contact to form a parallel-plate capacitor with the second contact. In other embodiments, forming, at block 708, the capacitive coupling comprises forming a conductive plate disposed above the third contact to form a parallel-plate capacitor with the third contact.
In some embodiments, the degree to which the capacitive coupling reduces or cancels inductive crosstalk depends on the size of the conductive plates of the capacitive coupling. In this embodiment, the method 700 includes forming a conductive plate of the capacitive coupler, wherein the reduction of the crosstalk depends on the size of the conductive plate.
An embodiment is an implementation or example. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” “various embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the present techniques. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
It is to be noted that, although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of circuit elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.
In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
It is to be understood that specifics in the aforementioned examples may be used anywhere in one or more embodiments. For instance, all optional features of the computing device described above may also be implemented with respect to either of the methods or the computer-readable medium described herein. Furthermore, although flow diagrams and/or state diagrams may have been used herein to describe embodiments, the techniques are not limited to those diagrams or to corresponding descriptions herein. For example, flow need not move through each illustrated box or state or in exactly the same order as illustrated and described herein.
The present techniques are not restricted to the particular details listed herein. Indeed, those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present techniques. Accordingly, it is the following claims including any amendments thereto that define the scope of the present techniques.
