METHOD AND APPARATUS FOR FAST BRANCH-FREE VECTOR DIVISION COMPUTATION

Abstract

Methods and apparatus for double precision division/inversion vector computations on Single Instruction Multiple Data (SIMD) computing platforms are described. In one embodiment, an input argument is represented by an exponent portion and a fraction portion. These portions are scaled, inverted, and multiplied to generate an inverse version of the input argument. In an embodiment, the inversion of the exponent portion may be done by changing the sign of the exponent. Other embodiments are also described.

Description

FIELD

The present disclosure generally relates to the field of computing. More particularly, an embodiment of the invention generally relates to techniques for fast branch-free vector division computation.

BACKGROUND

Compared to other simple arithmetic operations, hardware implementations for division operations have been quite slow, for example, due to larger latency. Some speedup could be achieved in vector cases due to various kind of parallelism existence on modern architectures, such as via SIMD (Single-Instruction, Multiple-Data) parallelism, superscalar, and out-of-order execution. For example, reciprocal approximation with further Newton-Raphson refinement iterations method (such as discussed at http://en.wikipedia.org/wiki/Newton%E2%80%93Raphson_method) generally works well for single precision (SP) case providing up to a two-fold speedup over hardware division operation in some implementations. However, this approach loses most of its benefits on double precision (DP) side because of absence of double precision reciprocal operation in current SSE architectures. Consequently, additional DP to SP and SP to DP conversions may need to be performed, along with exponent field manipulations. Further, the SP and DP above-described approximations generally require special processing of denominator with infinite (INF) or zero values, reducing parallelism and reducing potential performance gains.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is provided with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.

FIG. 1 illustrates a flow diagram of a method according to an embodiment of the invention.

FIGS. 2A-2C illustrate pseudo code segments, which may be used in some embodiments.

FIG. 3 illustrates a block diagram of a fast vector division, according to an embodiment.

FIGS. 4 and 5 illustrate block diagrams of embodiments of computing systems, which may be utilized to implement some embodiments discussed herein.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments of the invention may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments of the invention. Further, various aspects of embodiments of the invention may be performed using various means, such as integrated semiconductor circuits (“hardware”), computer-readable instructions organized into one or more programs (“software”), or some combination of hardware and software. For the purposes of this disclosure reference to “logic” shall mean either hardware, software (including for example micro-code that controls the operations of a processor), or some combination thereof.

Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.

Also, in the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. In some embodiments of the invention, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.

Some of the embodiments discussed herein may provide improved performance for double precision division/inversion vector computations, e.g., without requiring branches or special actions which were previously necessary. The vector division computations may be performed on SIMD computing platforms. Generally, SIMD is a technique employed to achieve data level parallelism. In particular, multiple data may be processed in multiple corresponding lanes of an SIMD vector processor (such as processors 402 and 502/504 of FIGS. 4 and 5, respectively) in accordance with a single instruction.

In some implementations, only one division operation is performed for several inversions. Taking the following as an example (proposed by I. I. Zavarzin, V. F. Kuryakin, V. V. Lunev, D. M. Obuvalin, V. G. Ryzhih in “Optimizatsiya Vychislenij Vektornyh Funktsyj.” VANT. ser. Matematicheskoe modelirovanie fizicheskih protsessov. 1997. Vol. 4 (Russian language magazine)):

$\frac{1}{x_1}=x_2·x_3·x_4·R,\frac{1}{x_2}=x_1·x_3·x_4·R,\frac{1}{x_3}=x_1·x_2·x_4·R,\frac{1}{x_4}=x_1·x_2·x_3·R,$

• • where

$R=\frac{1}{x_1·x_2·x_3·x_4}$

The inversion of every argument may be computed using three additional multiplications by R and three other arguments which is generally faster than four hardware divisions that involve large latency and large throughput value. More specifically, for the general case of N values, the next maximum possible performance gain estimation for this technique (D, M—throughput values for Division and Multiplier, respectively) may be:

$\mathrm{gain}=\frac{D}{\frac{D}{N}+\frac{\left(N-1\right)·M}{N}+\left(N-1\right)·M}$

A weakness of this approach lies in high possibility to encounter overflow or underflow for the product x₁·x₂·x₃·x₄ because of argument exponents variety which may result in incorrect outputs for the whole four-arguments bundle. For example, if x₁=0.0, but x₂≠0.0, x₃≠0.0, x₄≠0.0, then R=INF and three of four results are incorrect:

$\frac{1}{x_2}=\frac{1}{x_3}=\frac{1}{x_4}=\mathrm{INF}$

To address this problem, there needs to be a guarantee that the sum of all input exponents is not going to cause underflow or overflow. This makes the work interval quite narrow and requires argument comparisons with possible branches for special cases that cannot be processed properly in the main path. In an embodiment, the above-mentioned problems may be addressed by argument scaling and reconstruction.

More specifically, FIG. 1 illustrates a flow diagram of a method 100 in accordance with one embodiment. At an operation 102, one or more arguments (e.g., x₁, x₂, etc.) are received. The arguments may be represented as x=(−1)^sbⁿ·f, where the terms are defined as follows:

• • s={0,1}—sign for “s” in (−1)^s,
  • b—base (e.g., for binary case b=2),
  • n—exponent(E_max≦n≦E_min), where E_max and E_nin respectively refer to the minimum and maximum exponents for corresponding data type according to ANSI/IEEE Std

f=2⁰+f₁·2⁻¹+f₂·2⁻²+ . . . +f_p·2^−p=1·f₁f₂ . . . f_pB−mantissa(1≦f<2).

$\frac{1}{x}=\frac{1}{{\left(-1\right)}^s2^n·f}={\left(-1\right)}^s·2^{-n}·\frac{1}{f}.$

The inversion can be determined:

Assume that (x₁, x₂, x₃, x₄) are input arguments where x_i=(−1)^si 2ⁿⁱ·f₁ for i= 1,4. These are scaled at operation 104 by 2⁰ⁱ as z_i=1.0·f_i=2⁰·f_i. The scaled arguments are multiplied at operation 106 (e.g., M=z₁z₂z₃z₄) and the multiplication is inversed at operation 108 (e.g., R=1/M). For example, every

$\frac{1}{z_i}$

for i= 1,4 is calculated by:

$\frac{1}{z_i}=\frac{\prod _{j\ne i}z_j}{z_1z_2z_3z_4}$

At an operation 110, the result is reconstructed as

$\frac{1}{x_i}={\left(-1\right)}^{s_i}·2^{m_i}·\frac{1}{z_i}$

where

$m_i=\sum _{j\ne i}n_j-\sum _{j=\stackrel{\_}{1,4}}n_j=-n_i,$

in an embodiment, by an “insertion” of negated input exponent 2⁻ⁿⁱ and source sign into

$\frac{1}{z_i}.$

This approach provides sufficient accuracy and processes Institute of Electrical and Electronics Engineers, Inc. (IEEE) special values within the main path. As much as z_iε[1,2), no results with over/under-flow may occur during computation, e.g., a product of any two values z_i·z_jε[1,4), of any three values z_i·z_j·z_kε[1,8), of all four arguments z₁·z₂·z₃·z₄ε[1,16) and

$\frac{1}{z_i}\in \left(0.5,1\right],$

etc.

Furthermore, every multiplication may be done by rounding to working precision with error as much as 0.5 ulp (Unit in the Last Place or Unit of Least Precision; see, e.g., http://en.wikipcdia.org/wiki/Ulp; see, also, e.g., “On the definition of ulp(x)” by Jean-Michel Muller, INRIA Technical Report 5504), so the error of calculating z₁·z₂·z₃·z₄ will not be higher than 3·0.5=1.5 ulp.

In an embodiment, to find

$\frac{1}{z_i}=\frac{\prod _{j\ne i}z_j}{z_1z_2z_3z_4}$

another three multiplications may be used with additional 3·0.5=1.5 ulp and one inversion which is error-free this case. Thus, error of the result

$\frac{1}{z_i}$

will be less or equal to (3+3)*0.5=3.0 ulp. Final reconstruction

$\frac{1}{x_i}={\left(-1\right)}^{s_i}·2^{m_i}·\frac{1}{z_i}$

does not add any additional errors due to IEEE floating point numbers representation. Resulting 3.0 ulp is within requirements for ICL (Intel Compiler), SVML (Short Vector Math Library), MKL (Math Kernel Library) and IPP (Intel Performance Primitives) vector math libraries LA (Low Accuracy) default flavor—up to four ulp that corresponds to two incorrect mantissa bits which is enough for large majority of applications.

Furthermore, even though a case with a four-value bundle is discussed herein, these techniques could be applied to any bundle size.

FIGS. 2A to 2C illustrate pseudo codes to perform fast branch-free vector division computation, according to some embodiments. More specifically, FIG. 2A illustrates arguments, results, casts, and other definitions. FIG. 2B illustrates pseudo code for scaling arguments and saving original exponent values, along with multiplication of scaled arguments, e.g., as discussed with reference to FIG. 1. FIG. 2C illustrates pseudo code for result reconstruction. In some embodiments, for full division r[i] may be multiplied by numerators.

FIG. 3 illustrates a block diagram of a fast vector division, according to an embodiment. As shown, exponent and fraction portions of a floating point number 302 are separately handled 304. While in the shown example, the number (labeled as “arg”) is indicated within a shown range, other ranges may be used depending on the implementation, processor, datapath width, etc. Moreover, to obtain the inversion of an argument, inversion of exponent 306 and inversion of mantissa 308 may be determined separately, and then the final result is determined based on their product. In one embodiment, the inversion of exponent may be based on a sign replacement (310 and 312), such as discussed with reference to FIGS. 1-2C. This may be done via integer operations and without any accuracy loss in some embodiments. To inverse the fraction (314 and 316), it may be represented as a floating point number with zero exponent. Lastly, the final result is determined 318 based on the multiplication of the inverted fraction and exponent (which is considered to be a precise result since at least one of multipliers has a zero fraction).

FIG. 4 illustrates a block diagram of an embodiment of a computing system 400. In various embodiments, one or more of the components of the system 400 may be provided in various electronic devices capable of performing one or more of the operations discussed herein with reference to some embodiments of the invention. For example, one or more of the components of the system 400 may be used to perform the operations discussed with reference to FIGS. 1-3, e.g., by generating values corresponding to division/inversion by enhanced performance through use of SIMD, etc. in accordance with the operations discussed herein. Also, various storage devices discussed herein (e.g., with reference to FIGS. 4 and/or 5) may be used to store data, operation results, etc. In one embodiment, data associated with operations of method 300 of FIG. 3 may be stored in memory device(s) (such as memory 412 or one or more caches (e.g., L1 caches in an embodiment) present in processors 402 of FIG. 4 or 502/604 of FIG. 5). These processors may then apply the operations discussed herein for fast division/inversion (such as one or more of the operations of FIGS. 1-3). Accordingly, in some embodiments, processors 402 of FIG. 4 or 502/604 of FIG. 5 may be vector processors that are capable of supporting SIMD operations.

Moreover, the computing system 400 may include one or more central processing unit(s) (CPUs) 402 or processors that communicate via an interconnection network (or bus) 404. The processors 402 may include a general purpose processor, a network processor (that processes data communicated over a computer network 403), or other types of a processor (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC)). Moreover, the processors 402 may have a single or multiple core design. The processors 402 with a multiple core design may integrate different types of processor cores on the same integrated circuit (IC) die. Also, the processors 402 with a multiple core design may be implemented as symmetrical or asymmetrical multiprocessors. Additionally, the processors 402 may utilize an SIMD architecture. Moreover, the operations discussed with reference to FIGS. 1-3 may be performed by one or more components of the system 400.

A chipset 406 may also communicate with the interconnection network 404. The chipset 406 may include a memory control hub (MCH) 408. The MCH 408 may include a memory controller 410 that communicates with a memory 412. The memory 412 may store data, including sequences of instructions that are executed by the CPU 402, or any other device included in the computing system 400. In one embodiment of the invention, the memory 412 may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of storage devices. Nonvolatile memory may also be utilized such as a hard disk. Additional devices may communicate via the interconnection network 404, such as multiple CPUs and/or multiple system memories.

The MCH 408 may also include a graphics interface 414 that communicates with a display 416. The display 416 may be used to show a user results of operations associated with the fast division/inversion discussed herein. In one embodiment of the invention, the graphics interface 414 may communicate with the display 416 via an accelerated graphics port (AGP). In an embodiment of the invention, the display 416 may be a flat panel display that communicates with the graphics interface 414 through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display 416. The display signals produced by the interface 414 may pass through various control devices before being interpreted by and subsequently displayed on the display 416.

A hub interface 418 may allow the MCH 408 and an input/output control hub (ICH) 420 to communicate. The ICH 420 may provide an interface to I/O devices that communicate with the computing system 400. The ICH 420 may communicate with a bus 422 through a peripheral bridge (or controller) 424, such as a peripheral component interconnect (PCI) bridge, a universal serial bus (USB) controller, or other types of peripheral bridges or controllers. The bridge 424 may provide a data path between the CPU 402 and peripheral devices. Other types of topologies may be utilized. Also, multiple buses may communicate with the ICH 420, e.g., through multiple bridges or controllers. Moreover, other peripherals in communication with the ICH 420 may include, in various embodiments of the invention, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), USB port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), or other devices.

The bus 422 may communicate with an audio device 426, one or more disk drive(s) 428, and a network interface device 430, which may be in communication with the computer network 403. In an embodiment, the device 430 may be a NIC capable of wireless communication. Other devices may communicate via the bus 422. Also, various components (such as the network interface device 430) may communicate with the MCH 408 in some embodiments of the invention. In addition, the processor 402 and the MCH 408 may be combined to form a single chip. Furthermore, the graphics interface 414 may be included within the MCH 408 in other embodiments of the invention.

Furthermore, the computing system 400 may include volatile and/or nonvolatile memory (or storage). For example, nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g., 428), a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media that are capable of storing electronic data (e.g., including instructions). In an embodiment, components of the system 400 may be arranged in a point-to-point (PtP) configuration such as discussed with reference to FIG. 5. For example, processors, memory, and/or input/output devices may be interconnected by a number of point-to-point interfaces.

More specifically, FIG. 5 illustrates a computing system 500 that is arranged in a point-to-point (PtP) configuration, according to an embodiment of the invention. In particular, FIG. 5 shows a system where processors, memory, and input/output devices are interconnected by a number of point-to-point interfaces. The operations discussed with reference to FIGS. 1-4 may be performed by one or more components of the system 500.

As illustrated in FIG. 5, the system 500 may include several processors, of which only two, processors 502 and 504 are shown for clarity. The processors 502 and 504 may each include a local memory controller hub (MCH) 506 and 508 to couple with memories 510 and 512. The memories 510 and/or 512 may store various data such as those discussed with reference to the memory 412 of FIG. 4.

The processors 502 and 504 may be any suitable processor such as those discussed with reference to the processors 402 of FIG. 4. The processors 502 and 504 may exchange data via a point-to-point (PtP) interface 514 using PtP interface circuits 516 and 518, respectively. The processors 502 and 504 may each exchange data with a chipset 520 via individual PtP interfaces 522 and 524 using point to point interface circuits 526, 528, 530, and 532. The chipset 520 may also exchange data with a high-performance graphics circuit 534 via a high-performance graphics interface 536, using a PtP interface circuit 537.

At least one embodiment of the invention may be provided by utilizing the processors 502 and 504. For example, the processors 502 and/or 504 may perform one or more of the operations of FIGS. 1-4. Other embodiments of the invention, however, may exist in other circuits, logic units, or devices within the system 500 of FIG. 5. Furthermore, other embodiments of the invention may be distributed throughout several circuits, logic units, or devices illustrated in FIG. 5.

The chipset 520 may be coupled to a bus 540 using a PtP interface circuit 541. The bus 540 may have one or more devices coupled to it, such as a bus bridge 542 and I/O devices 543. Via a bus 544, the bus bridge 543 may be coupled to other devices such as a keyboard/mouse 545, the network interface device 530 discussed with reference to FIG. 5 (such as modems, network interface cards (NICs), or the like that may be coupled to the computer network 403), audio I/O device, and/or a data storage device 548. The data storage device 548 may store code 549 that may be executed by the processors 502 and/or 504.

In various embodiments of the invention, the operations discussed herein, e.g., with reference to FIGS. 1-5, may be implemented as hardware (e.g., logic circuitry), software (including, for example, micro-code that controls the operations of a processor such as the processors discussed with reference to FIGS. 4-5), firmware, or combinations thereof, which may be provided as a computer program product, e.g., including a tangible machine-readable or computer-readable medium having stored thereon instructions (or software procedures) used to program a computer (e.g., a processor or other logic of a computing device) to perform an operation discussed herein. The machine-readable medium may include a storage device such as those discussed herein.

Additionally, such tangible computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in tangible propagation medium via a communication link (e.g., a bus, a modem, or a network connection).

Thus, although embodiments of the invention have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.

Claims

1. A method comprising: scaling a plurality of arguments to generate a plurality of corresponding scaled arguments;multiplying the plurality of scaled arguments to generate a first value;inverting the first value to generate a second value; andreconstructing a plurality of results based on a multiplication of the second value with one or more of the plurality of scaled arguments,wherein the plurality of results correspond to inverted versions of the plurality of arguments.

2. The method of claim 1, wherein inverting the first value is performed by changing a sign of an exponent portion of the first value.

3. The method of claim 1, further comprising converting a floating point version of the plurality of arguments to an integer value.

4. The method of claim 1, wherein scaling the plurality of arguments comprises scaling the plurality of arguments by 1.0.

5. The method of claim 1, further comprising storing generated values in a memory.

6. An apparatus comprising: a memory to store a plurality of data values corresponding to an SIMD (Single Instruction, Multiple Data) instruction; anda processor having a plurality of SIMD lanes, wherein each of the plurality of the SIMD lanes is to process one of the plurality of data stored in the memory in accordance with the SIMD instruction, wherein the processor is to: scale an exponent portion and a fraction portion of a first value of the plurality of data values to respectively generate a second value and a third value;invert the second value and the third value to respectively generate a fourth value and a fifth value; andmultiply the fourth value and the fifth value to generate an inverse version of the first value, wherein the second value is to be inverted by changing a sign of the exponent portion of the first value.

7. The apparatus of claim 6, wherein the processor is to determine the exponent portion and fraction portion of the first value.

8. The apparatus of claim 6, wherein the processor is to scale the exponent and fraction portions of the first value by 1.0 to generate the second and third values.

9. The apparatus of claim 6, wherein the processor is to convert a floating point version of the plurality of data values to an integer value.

10. The apparatus of claim 6, wherein the memory comprises a cache.

11. The apparatus of claim 6, wherein the processor comprises one or more processor cores.

12. The apparatus of claim 6, wherein the processor is to cause storage of generated values in the memory.

13. The apparatus of claim 6, further comprising a display device to display the inverse version of the first value.

14. A computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to: scale a plurality of arguments to generate a plurality of corresponding scaled arguments;multiply the plurality of scaled arguments to generate a first value;invert the first value to generate a second value; andreconstruct a plurality of results based on a multiplication of the second value with one or more of the plurality of scaled arguments.

15. The computer-readable medium of claim 14, wherein the plurality of results correspond to inverted versions of the plurality of arguments.

16. The computer-readable medium of claim 14, further comprising one or more instructions that when executed on a processor configure the processor to invert the first value by changing a sign of an exponent portion of the first value.

17. The computer-readable medium of claim 14, further comprising one or more instructions that when executed on a processor configure the processor to convert a floating point version of the plurality of arguments to an integer value.

18. The computer-readable medium of claim 14, further comprising one or more instructions that when executed on a processor configure the processor to scale the plurality of arguments by 1.0.

19. The computer-readable medium of claim 14, further comprising one or more instructions that when executed on a processor configure the processor to store generated values in a memory.

20. The computer-readable medium of claim 14, further comprising one or more instructions that when executed on a processor configure the processor to multiply an inverted exponent portion and an inverted fraction portion of the plurality of arguments.