The present invention relates to an IFFT/FFT signal processing method for converting frequency-domain signals into time-domain signals and vice versa. An IFFT/FFT signal processor for performing this method is used for example in any OFDM-based communication system, e.g. WLAN systems according to 802.11a,g standard, where this device plays a key role in the signal processing queue. OFDM (Orthogonal Frequency Division Multiplexing) is a transmission technique based upon the idea of frequency-division multiplexing (FDM), where multiple signals are sent out at the same time, but on different frequencies. In OFDM, a single transmitter transmits on many different orthogonal (independent) frequencies (typically dozens to thousands). An OFDM baseband signal is the sum of a number of orthogonal sub-carriers, with data on each sub-carrier being independently modulated commonly using some type of quadrature amplitude modulation (QAM) or phase-shift keying (PSK). This composite baseband signal is typically used to modulate a main RF carrier. Although the invention is well understood in the context of increasingly popular WLAN systems as HiperLAN2, 802.11a, 802.11g and soon 802.11n to name but a few, it is obvious that it can be applied to any signal processing or communication system implementing an IFFT/FFT processor.
The 802.11n standard, which is currently in the process of being specified, is expected to supersede the 802.11a/g standard by the end of 2006. As we speak, two contending proposals (called TGnSync and Wwise) have been made and are debated. Although none of them has achieved a decisive advantage over the other yet, several features are already looming:
These facts mean that 802.11n modems will need to embed a dual-mode (i.e. 64-point+128-point) IFFT/FFT processor. A 128-point IFFT/FFT is therefore needed to complete the 64-point IFFT/FFT block inherited in a 802.11n modem to make a dual-mode IFFT/FFT processor.
A straightforward solution consists in designing and coding a 128-point FFT from scratch and join it with the existing 64-point FFT to make the dual-mode processor spoken of above. This means we must develop from scratch a 128-point IFFT/FFT block and juxtapose it with the 64-point one. Two separate IFFT/FFT processors which are by the way very likely to feature different radices are thus required to constitute the dual-mode IFFT/FFT processor spoken above. It goes without saying that this solution is very expensive in every aspect since a pretty sizeable project has to be initiated and carried out to fulfill this goal. This approach involves, among other things, finding the necessary human resources, conducting a theoretical study, designing the corresponding Matlab fixed-point model, writing the VHDL file, performing the bit-true verification, etc. Gate count wise, it is anticipated that the size of the dual-mode IFFT/FFT processor will more than double (even triple should we say). The same can be said for the power consuption.
It is the object of the invention to provide an IFFT/FFT signal processing method and a related signal processor for computing an 2N-point Fourier transform.
This object is achieved by providing an IFFT/FFT signal processing method and a signal processor as described in the independent claims.
Other features which are considered to be characteristic for the invention are set forth in the dependent claims.
According to the invention, a signal processing method is provided that makes use of an existing N-point FFT processor as well as other blocks such as a CORDIC or a filter to compute a 2N-point FFT.
The invention reuses an existing N-point IFFT/FFT block and integrate it into a greater scheme through either generalizing the butterfly concept or performing adequate low-pass filtering. Thus we can easily compute a 2N-point IFFT/FFT. This approach requires a minimal investment of time, staff and technology and will therefore result in significant savings in terms of men months, gate count (the die size should not grow more than 20 to 40%), power consumption (which matters a lot nowadays) and ultimately cost.
Four embodiments of the invention are proposed. Please note that we restricted ourselves to solely describing the direct FFT. The inverse FFT can be derived from the following block diagrams without any difficulty.
and a upper part frequency domain signal
These two signals
are fed to an adder circuit 6 and added together to form a frequency domain signal comprising the “even” subcarriers 0:2:126 of the OFDM baseband signal.
At the same time, the lower part signal xlower(n) and the upper part signal xupper(n) are input to a CORDIC (Coordinate Rotation Digital Computer) rotator 5 where they are rotated by a phase sequence of
The rotated lower part signal Xlower(bis)(n) and the rotated upper part signal xupper(bis)(n) are each input to a 64-point FFT signal processor 3, 4 and subjected in parallel (or consecutively) to a 64-point FFT with 2/4/8 mixed radix. This results in a rotated lower part frequency domain signal
and a rotated upper part frequency domain signal
These two signals
are fed to an adder circuit 7 and added together to form a frequency domain signal comprising the “odd” subcarriers 1:2:127 of the OFDM baseband signal.
According to a second embodiment of the invention shown in
and a upper part frequency domain signal
These two signals
are fed to an adder 6 and added together to form a frequency domain signal comprising the “even” subcarriers 0:2:126 of the OFDM baseband signal.
At the same time, the two signals
are are individually fed to filter circuits 8, 9 and subjected to a frequency domain filtering Hlower and Hupper, respectively. The complex coeficcients of the frequency domain filters 8, 9 are obtained as follows (matlab notation);
The filtered lower part frequency domain signal
and the filtered upper part frequency domain signal
are then fed to an adder circuit 7 and added together to form a frequency domain signal comprising the “odd” subcarriers 1:2:127 of the OFDM baseband signal.
According to a third embodiment of the in invention as depicted in
In a second branch, the upper signal part xuppe(n) is subtracted from the lower part signal xlower(n) by means of an adder 11 (substactor). The resulting singal is input to a 64-point FFT signal processor 2 and subjected to a 64-point FFT with 2/4/8 mixed radix. This results in a frequency domain signal which is input to a filter circuit 9 and further subjected to a frequency domain filtering
The resulting filtered frequency domain signal comprises the “odd” subcarriers 0:2:127 of the OFDM baseband signal.
In the following, the mathematical equations associated with the three embodiments of the invention are set forth. Let us start with some useful notations:
The drawing
By virtue of the definition of the discrete Fourier transform, we have:
For “even” subcarriers, i.e. when k=2m with 0≦m≦M−1, we have:
It is easy to see that the above equation underlies the three previously depicted embodiments of invention when it comes to calculating the “even” subcarriers.
Now, for “odd” subcarriers, i.e. when k=2m+1 with 0≦m≦M−1, we have:
The above equation underlies the first embodiment when it comes to calculating the “odd” subcarriers. It can also be rewritten as follows:
Where * demotes the convolution product.
The above equation underlies the second embodiment when it comes to calculating the “odd” subcarriers.
The above equation underlies the third embodiment when it comes to calculating the “odd” subcarriers.
According to a forth embodiment of the invention,
With reference to
With reference to
The processing of the upper and the lower subcarriers can be performed sequentially or in parallel using one or two 64-point FFT signal processors.
Number | Date | Country | Kind |
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10 2005 045 519.0 | Sep 2005 | DE | national |