Patent Application
20120139592
This disclosure relates to methods and systems for synthesizing a fixed frequency signal, as well as producing a modulated signal.
Modern electronics often require multiple timing signals to clock a multitude of different signal processing circuits. Traditional circuits produce each of the required timing signals with a dedicated frequency synthesizer that modifies an input clock signal supplied by an oscillator. Each conventional frequency synthesizer contains an analog phase locked loop with an associated voltage controlled oscillator. Further, each frequency synthesizer occupies layout area on a semiconductor die, requires power, and is subject to coupled noise and effects of spurious radiation. Most traditional frequency synthesizers also require a filter capacitor that is external to the semiconductor die.
There are long-felt industry needs for frequency synthesizers that, compared to conventional devices, occupy less layout area on an integrated circuit die, have lower power consumption, have greater timing accuracy, have greater noise immunity, have faster lockup times, are located completely on the integrated circuit die, and modulate more accurately. Thus, there are needs to improve upon classic circuit designs and methods.
Exemplary embodiments are directed to systems and methods for synthesizing a signal having fixed frequency, as well as systems and methods for producing a modulated signal. The exemplary embodiments address the long-felt needs in the industry described herein.
Systems and methods for digital frequency synthesis are provided. Embodiments of the digital frequency synthesizer can produce a fixed programmable frequency and/or a modulated signal. The digital frequency synthesizer provides many benefits, for example, the digital frequency synthesizer saves area on a silicon die because it eliminates a need for separate frequency synthesizers to support processing of each signal path, such as a receive signal path, transmit signal path, diversity signal path, GPS signal path, etc. Among other benefits, the reduction in circuitry leads to reduced power demand, fewer intermodulation issues, and a lower component count that reduces production costs. The digital frequency synthesizer also provides greater timing accuracy and locks up in nanoseconds, which is faster than conventional phase locked loop and voltage controlled oscillator circuits. When used as a modulator, the digital frequency synthesizer provides direct phase and frequency modulation. Compared to conventional modulator designs, the digital frequency synthesizer modulates more accurately and provides a wider bandwidth.
In an embodiment, the digital frequency synthesizer includes multiple delay cells coupled in series. A clock signal is input to the delay cells. The delay cells sequentially delay the input clock signal. The outputs of the delay cells, as a group, provide a parallel output signal having a series of delayed edges of the input clock signal. The digital frequency synthesizer also includes a linear feedback shift register (LFSR) that has multiple registers coupled in series, and is configured to cycle a logic “1” in an endless loop. The outputs of the LFSR as a group also provide a parallel output signal. Respective parallel outputs from the delay cells and the LFSR are input to respective AND gates. Outputs of the AND gates are combined in an OR gate to produce the digital synthesized output signal. The digital synthesized output signal, in turn, clocks each register in the LFSR.
Also provided is a method of generating a digital synthesized signal. The method includes inputting a clock signal at a first frequency into a plurality of delay cells for generating and outputting a series of delayed edges of the clock signal. A modified version of the clock signal is input into an LFSR to enable respective portions thereof. The series of delayed edges and outputs of the respective portions of the LFSR are combined in a logic circuit to generate the synthesized signal.
The accompanying drawings are presented to aid in the description of the various embodiments and are provided solely for illustration of the embodiments and not limitation thereof.
Aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments of the disclosure. Alternate embodiments can be devised without departing from the scope of the invention. Additionally, well-known elements may not be described in detail or will be omitted so as not to obscure the relevant details of the various embodiments.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments” or “embodiments of the invention” does not require that all embodiments include a discussed feature, advantage or mode of operation.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of various embodiments. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Further, many embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, the sequences of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the invention can be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, the corresponding form of any such embodiments can be described herein as, for example, “logic configured to” perform the described action.
Systems and methods for frequency synthesis are provided. Frequency synthesis is the generation, from an input generated by a fixed frequency oscillator, of a signal having a frequency in a range of frequencies. The disclosed digital frequency synthesizer can multiply, divide, and mix frequencies. Embodiments of the digital frequency synthesizer can produce a fixed programmable frequency and/or a modulated signal. Among other benefits, the digital frequency synthesizer saves area on a silicon die because it eliminates a need for separate frequency synthesizers to support processing of each signal path, such as a receive path, transmit path, diversity path, GPS path, etc. Savings of silicon area is also realized through a reduced need for external filter devices. The reduced quantity of circuitry leads to reduced power demand, fewer intermodulation issues, and a lower component count that reduces fabrication costs. The digital frequency synthesizer also provides greater timing accuracy with lower noise than conventional designs. In addition, the digital frequency synthesizer also locks up faster than conventional phase locked loop and voltage controlled oscillator circuits. When used as a modulator, the digital frequency synthesizer provides direct phase and frequency modulation. Compared to conventional modulators, the digital frequency synthesizer modulates more accurately and provides a wider bandwidth.
The digital frequency synthesizer functions based on direct digital synthesis and frequency to phase translation. A delay locked loop (DLL) generates precise, substantially equally delayed clock edges. The DLL has a quantity of “n” delay cells which each delay the input clock by a delay unit “n.” Selected delayed clock edges are passed to a combiner, which outputs a synthesized digital clock as the digital frequency synthesizer output. The clock edges can be selected to maintain the phase of the digital frequency synthesizer's output as fixed, relative to the input clock. For example, when the delayed clock edges are selected for every clock period, the frequency of the digital frequency synthesizer output equals approximately:
where Tlo is the period of the input clock/local oscillator. As a further example, when the delayed clock edges are selected for every fractional clock period “1/m,” the frequency of the digital frequency synthesizer output equals approximately:
Thus, when n=8, the maximum output frequency range can vary from the input clock frequency by approximately ±12.5%.
In the digital frequency synthesizer, the clock edges are selected by a multiplexer controlled by a phase control signal from an accumulator. The accumulator integrates an input frequency control signal to create the phase control signal. Thus, the frequency control signal determines the phase of the digital frequency synthesizer output. If the frequency control signal is fixed, then the frequency of the digital frequency synthesizer output is fixed. If the frequency control signal varies, then the frequency of the digital frequency synthesizer output varies accordingly (i.e., the frequency control signal modulates the clock signal input to the digital frequency synthesizer).
An oscillator 115, for example, a temperature-compensated crystal oscillator (TCXO), generates a reference clock signal. The reference clock signal is processed by a phase locked loop (PLL) 120 to stabilize the phase and frequency of the reference clock signal, and to form an input clock signal 125 having a frequency (Fin). As shown, the input clock signal 125 can be used by circuits that require a clock signal, other than the DFS 105, in the communication device 100. The DFS 105 produces a DFS output 130 that is a digital, frequency synthesized signal. The DFS 105 is described below in further detail.
A bidirectional linear feedback shift register (LFSR) 225 provides another input to the multiplexer 220. The LFSR 225 converts a phase control signal 230 to a parallel LFSR output signal (Qm) 235. If the phase control signal 230 is constant, then the DFS output 130 has a fixed frequency. If the phase control signal 230 varies, then the DFS output 130 frequency is modulated accordingly. The LFSR 225 also locks the parallel LFSR output signal (Qm) 235 to a DFS coarse output 240 because the LFSR's registers 245 are clocked with the DFS coarse output 240. The parallel LFSR output signal (Qm) 235 is forwarded to the multiplexer 220.
The multiplexer 220 selects a delayed clock signal from a single DLL output in the parallel DLL output 205 based on the parallel LFSR output signal (Qm) 235. The selection is made with AND gates 250. The multiplexer 220 provides the selected delayed clock signal to a combiner 255 via a parallel output.
The combiner 255 combines the parallel output of the multiplexer 220 to form the DFS coarse output 240. The combiner 255 outputs, as the DFS coarse output 240, any input signal provided by any line in the parallel output of the multiplexer 220. In an exemplary circuit, an OR gate 260 can be used as the combiner 255. The DFS coarse output 240 can optionally be further refined with a fine delay control circuit 265, or is output as the DFS output 130.
The fine delay control circuit 265 improves the timing accuracy of the DFS coarse output 240. The fine delay control circuit 265 includes at least one additional delay locked loop 270 to process the DFS coarse output 240 and produce the DFS output 130. The fine delay control circuit 265 is controlled by an accumulator 275.
The accumulator 275 receives a frequency control signal 280 and a divided clock 285 having a frequency of (Fin)/m, where “m” is a fractional relation of the synthesized signal to the clock signal. Dividing the clock is optional, i.e., “m” can equal one. In an example, the frequency control signal 280 has a frequency between substantially 62.5 MHz and substantially 250 MHz. The frequency control signal 280 can also be digitally pre-compensated to linearize the response of the DFS 105.
The accumulator 275 provides a re-synchronizing phase control signal 230 to the LFSR 225 and the fine delay control circuit 265 that is based on the frequency control signal 280. The phase control signal 230 enables the LFSR registers 245. Every overflow of the accumulator 275 represents an integer phase step. Timing of the phase control signal 230 relative to the frequency of the fractionally delayed clock edges 215 determines the selection rate of the fractionally delayed clock edges 215 by the multiplexer 220. The digital bitwidth of the accumulator 275 determines the frequency resolution of the DFS 105 as follows:
where Fin is the frequency of the input clock signal 125, “n” is the number of delay cells 210 and delay units (e.g., 8), and “m” is the fractional relation of the divided clock 285 to the clock signal (e.g., 4). An exemplary bitwidth is 28 bits. It is important to note that delay of the phase control signal 230 sent to the LFSR 225 due to the accumulator 275 should be compensated.
A divider 290 is an optional circuit that divides the input clock signal 125 by the factor “m” to provide the divided clock 285 to the accumulator 275.
The LFSR 225 includes LFSR registers 245, identified in
During operation, the single logic “1” bit is cycled through the loop formed by the LFSR registers 245. The phase control signal 230 determines both a direction in which the logic “1” is cycled through the loop of LFSR registers 245, as well as if the logic “1” is shifted or held constant. The output of the LFSR registers 245 in the LFSR 225 produce a parallel LFSR output signal (Qm) 235 that is locked to the DFS coarse output 240. The parallel LFSR output signal (Qm) 235 is forwarded to the multiplexer 220.
The combiner 255 combines the parallel output of the multiplexer 220 to form the DFS coarse output 240. The combiner 255 outputs, as the DFS coarse output 240, any input signal provided by any line in the parallel output of the multiplexer 220. In an example, as depicted in
In a non-limiting example where the DFS 105 provides a DFS output 130 having a fixed frequency equal to the frequency of the input clock signal 125, the input clock signal 125 has a frequency of four gigahertz, the divider 290 divides the input clock signal 125 by an “m” value equal to four, thus the divided clock 285 has a frequency of 1 GHz. The DLL 200 has eight delay units, yielding a delay time for each delay cell 210 of 31.25 picoseconds. The accumulator 275 has a bitwidth of twenty-eight hits and provides the phase control signal 230 at one gigahertz to the LFSR 225. The fine delay control circuit 265 has two additional series-coupled DLLs 270. Accordingly, the DFS coarse output 240 and the DFS output 130 have a frequency of four gigahertz with an accuracy of 0.122 picoseconds. All numerical data in this example is approximate.
In step 705, an input clock signal at a first frequency (Fin) is input into a plurality of delay cells for generating and outputting a series of delayed edges of the clock signal. In an example, the clock signal can have a frequency in a range from substantially 106 Hz to substantially 1012 Hz.
In step 710, the phase of the output of the delay cells is locked with a delay locked loop. Step 710 is optional.
In step 715, a modified version of the clock signal is input into a linear feedback shift register (LFSR) to enable respective portions thereof. Enabling respective portions of the LFSR can comprise controlling a shift direction of the LFSR with the modified version of the clock signal.
In step 720, a divided version of the input clock signal is input into an accumulator. Dividing the clock is optional, the input clock signal can be input, undivided, to the accumulator. The divided version of the input clock signal is determined according to Fin/(n*m*bitwidth). The factor “n” is an integer relation of the synthesized signal to the input clock signal, “m” is the fractional relation of the synthesized signal to the input clock signal, and is determined first. “Bitwidth” is the accumulator's digital bitwidth. If “m” equals one, the clock is not divided. The modified version of the clock signal is generated based on the input clock signal and the divided version of the clock signal. Alternatively, the modified version of the input clock signal is generated based on the divided version of the clock signal and a baseband signal. Step 720 is optional.
In step 725, the series of delayed edges and outputs of the respective portions of the LFSR 225 is combined in a logic circuit to generate the synthesized signal.
In step 730, the synthesized signal is input into a second plurality of delay cells 210 to improve the accuracy of the synthesized signal. Step 730 is optional.
In step 735, the synthesized signal is input into a fine delay control circuit 265. The fine delay control circuit is controlled with the modified version of the input clock signal. Step 735 is optional.
Those of skill in the art will appreciate that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the invention.
The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, die storage medium. In the alternative, the storage medium can be integral to the processor.
Accordingly, an embodiment can include a computer readable media embodying a method for synthesizing a frequency. Further, it will be appreciated that the various embodiments are not limited to illustrated examples and any means for performing the functionality described herein are included in the embodiments.
While the foregoing disclosure shows illustrative embodiments, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the embodiments described herein need not be performed in any particular order. Furthermore, although elements of the various embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
