Claims
- 1. An isolation circuit for providing dc isolation between first and second circuits that may be referenced to different ground potentials, comprising:a transformer having first and second transformer coils; said first coil of said transformer being connected to a ground of said first circuit and to an output node of said first circuit, and said second coil of said transformer to a ground of said second circuit and an input node of said second circuit; a first capacitance connected between said output node of said first circuit and a second side of said first coil of said transformer, and a second capacitance connected between said input node of said second circuit and a second side of said second coil of said transformer; a signal output buffer in said first circuit connected to said output node; a signal input buffer in said second circuit, said signal input buffer being connected to said input node and being constructed to hold a desired state at said input node despite charge leakage from said capacitances; wherein said signal input buffer comprises a first inverter and a bus holder comprising a second inverter connected in a reverse direction across the first inverter.
- 2. The circuit of claim 1 wherein each of said first and second capacitances is a single capacitor.
- 3. The circuit of claim 1 wherein said first and second circuits to be isolated are on first and second integrated circuit devices.
- 4. The integrated circuit of claim 1 wherein said bus holder circuit is internal to said integrated circuit containing said input buffer.
- 5. The integrated circuit of claim 1 wherein said bus holder provides less drive than said output buffer.
- 6. The integrated circuit of claim 1 wherein said bus holder comprises a p-channel MOS device and an n-channel MOS device connected between a supply voltage and a ground potential, said MOS devices having gates connected to an output of said first inverter and drains connected to an input of said first inverter.
- 7. The integrated circuit of claim 1 wherein said output node is an input/output node, and further comprising a second input buffer contained in said first circuit having an input connected to said input/output node, said second input buffer being constructed to hold a desired sate at said input/output node despite charge leakage from said capacitances.
Parent Case Info
This is a Divisional Application of Ser. No. 08/835,888, filed Apr. 8, 1997.
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Provisional Applications (1)
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Number |
Date |
Country |
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60/015063 |
Apr 1996 |
US |